xref: /linux/drivers/net/ethernet/renesas/rswitch.h (revision 06103dccbbd29408255a409f6f98f7f02387dc93)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Renesas Ethernet Switch device driver
3  *
4  * Copyright (C) 2022 Renesas Electronics Corporation
5  */
6 
7 #ifndef __RSWITCH_H__
8 #define __RSWITCH_H__
9 
10 #include <linux/platform_device.h>
11 #include "rcar_gen4_ptp.h"
12 
13 #define RSWITCH_MAX_NUM_QUEUES	128
14 
15 #define RSWITCH_NUM_AGENTS	5
16 #define RSWITCH_NUM_PORTS	3
17 #define rswitch_for_each_enabled_port(priv, i)		\
18 	for (i = 0; i < RSWITCH_NUM_PORTS; i++)		\
19 		if (priv->rdev[i]->disabled)		\
20 			continue;			\
21 		else
22 
23 #define rswitch_for_each_enabled_port_continue_reverse(priv, i)	\
24 	for (; i-- > 0; )					\
25 		if (priv->rdev[i]->disabled)			\
26 			continue;				\
27 		else
28 
29 #define TX_RING_SIZE		1024
30 #define RX_RING_SIZE		4096
31 #define TS_RING_SIZE		(TX_RING_SIZE * RSWITCH_NUM_PORTS)
32 
33 #define RSWITCH_MAX_MTU		9600
34 #define RSWITCH_HEADROOM	(NET_SKB_PAD + NET_IP_ALIGN)
35 #define RSWITCH_DESC_BUF_SIZE	2048
36 #define RSWITCH_TAILROOM	SKB_DATA_ALIGN(sizeof(struct skb_shared_info))
37 #define RSWITCH_ALIGN		128
38 #define RSWITCH_BUF_SIZE	(RSWITCH_HEADROOM + RSWITCH_DESC_BUF_SIZE + \
39 				 RSWITCH_TAILROOM + RSWITCH_ALIGN)
40 #define RSWITCH_MAP_BUF_SIZE	(RSWITCH_BUF_SIZE - RSWITCH_HEADROOM)
41 #define RSWITCH_MAX_CTAG_PCP	7
42 
43 #define RSWITCH_TIMEOUT_US	100000
44 
45 #define RSWITCH_TOP_OFFSET	0x00008000
46 #define RSWITCH_COMA_OFFSET	0x00009000
47 #define RSWITCH_ETHA_OFFSET	0x0000a000	/* with RMAC */
48 #define RSWITCH_ETHA_SIZE	0x00002000	/* with RMAC */
49 #define RSWITCH_GWCA0_OFFSET	0x00010000
50 #define RSWITCH_GWCA1_OFFSET	0x00012000
51 
52 /* TODO: hardcoded ETHA/GWCA settings for now */
53 #define GWCA_IRQ_RESOURCE_NAME	"gwca0_rxtx%d"
54 #define GWCA_IRQ_NAME		"rswitch: gwca0_rxtx%d"
55 #define GWCA_NUM_IRQS		8
56 #define GWCA_INDEX		0
57 #define AGENT_INDEX_GWCA	3
58 #define GWCA_IPV_NUM		0
59 #define GWRO			RSWITCH_GWCA0_OFFSET
60 
61 #define GWCA_TS_IRQ_RESOURCE_NAME	"gwca0_rxts0"
62 #define GWCA_TS_IRQ_NAME		"rswitch: gwca0_rxts0"
63 #define GWCA_TS_IRQ_BIT			BIT(0)
64 
65 #define FWRO	0
66 #define TPRO	RSWITCH_TOP_OFFSET
67 #define CARO	RSWITCH_COMA_OFFSET
68 #define TARO	0
69 #define RMRO	0x1000
70 enum rswitch_reg {
71 	FWGC		= FWRO + 0x0000,
72 	FWTTC0		= FWRO + 0x0010,
73 	FWTTC1		= FWRO + 0x0014,
74 	FWLBMC		= FWRO + 0x0018,
75 	FWCEPTC		= FWRO + 0x0020,
76 	FWCEPRC0	= FWRO + 0x0024,
77 	FWCEPRC1	= FWRO + 0x0028,
78 	FWCEPRC2	= FWRO + 0x002c,
79 	FWCLPTC		= FWRO + 0x0030,
80 	FWCLPRC		= FWRO + 0x0034,
81 	FWCMPTC		= FWRO + 0x0040,
82 	FWEMPTC		= FWRO + 0x0044,
83 	FWSDMPTC	= FWRO + 0x0050,
84 	FWSDMPVC	= FWRO + 0x0054,
85 	FWLBWMC0	= FWRO + 0x0080,
86 	FWPC00		= FWRO + 0x0100,
87 	FWPC10		= FWRO + 0x0104,
88 	FWPC20		= FWRO + 0x0108,
89 	FWCTGC00	= FWRO + 0x0400,
90 	FWCTGC10	= FWRO + 0x0404,
91 	FWCTTC00	= FWRO + 0x0408,
92 	FWCTTC10	= FWRO + 0x040c,
93 	FWCTTC200	= FWRO + 0x0410,
94 	FWCTSC00	= FWRO + 0x0420,
95 	FWCTSC10	= FWRO + 0x0424,
96 	FWCTSC20	= FWRO + 0x0428,
97 	FWCTSC30	= FWRO + 0x042c,
98 	FWCTSC40	= FWRO + 0x0430,
99 	FWTWBFC0	= FWRO + 0x1000,
100 	FWTWBFVC0	= FWRO + 0x1004,
101 	FWTHBFC0	= FWRO + 0x1400,
102 	FWTHBFV0C0	= FWRO + 0x1404,
103 	FWTHBFV1C0	= FWRO + 0x1408,
104 	FWFOBFC0	= FWRO + 0x1800,
105 	FWFOBFV0C0	= FWRO + 0x1804,
106 	FWFOBFV1C0	= FWRO + 0x1808,
107 	FWRFC0		= FWRO + 0x1c00,
108 	FWRFVC0		= FWRO + 0x1c04,
109 	FWCFC0		= FWRO + 0x2000,
110 	FWCFMC00	= FWRO + 0x2004,
111 	FWIP4SC		= FWRO + 0x4008,
112 	FWIP6SC		= FWRO + 0x4018,
113 	FWIP6OC		= FWRO + 0x401c,
114 	FWL2SC		= FWRO + 0x4020,
115 	FWSFHEC		= FWRO + 0x4030,
116 	FWSHCR0		= FWRO + 0x4040,
117 	FWSHCR1		= FWRO + 0x4044,
118 	FWSHCR2		= FWRO + 0x4048,
119 	FWSHCR3		= FWRO + 0x404c,
120 	FWSHCR4		= FWRO + 0x4050,
121 	FWSHCR5		= FWRO + 0x4054,
122 	FWSHCR6		= FWRO + 0x4058,
123 	FWSHCR7		= FWRO + 0x405c,
124 	FWSHCR8		= FWRO + 0x4060,
125 	FWSHCR9		= FWRO + 0x4064,
126 	FWSHCR10	= FWRO + 0x4068,
127 	FWSHCR11	= FWRO + 0x406c,
128 	FWSHCR12	= FWRO + 0x4070,
129 	FWSHCR13	= FWRO + 0x4074,
130 	FWSHCRR		= FWRO + 0x4078,
131 	FWLTHHEC	= FWRO + 0x4090,
132 	FWLTHHC		= FWRO + 0x4094,
133 	FWLTHTL0	= FWRO + 0x40a0,
134 	FWLTHTL1	= FWRO + 0x40a4,
135 	FWLTHTL2	= FWRO + 0x40a8,
136 	FWLTHTL3	= FWRO + 0x40ac,
137 	FWLTHTL4	= FWRO + 0x40b0,
138 	FWLTHTL5	= FWRO + 0x40b4,
139 	FWLTHTL6	= FWRO + 0x40b8,
140 	FWLTHTL7	= FWRO + 0x40bc,
141 	FWLTHTL80	= FWRO + 0x40c0,
142 	FWLTHTL9	= FWRO + 0x40d0,
143 	FWLTHTLR	= FWRO + 0x40d4,
144 	FWLTHTIM	= FWRO + 0x40e0,
145 	FWLTHTEM	= FWRO + 0x40e4,
146 	FWLTHTS0	= FWRO + 0x4100,
147 	FWLTHTS1	= FWRO + 0x4104,
148 	FWLTHTS2	= FWRO + 0x4108,
149 	FWLTHTS3	= FWRO + 0x410c,
150 	FWLTHTS4	= FWRO + 0x4110,
151 	FWLTHTSR0	= FWRO + 0x4120,
152 	FWLTHTSR1	= FWRO + 0x4124,
153 	FWLTHTSR2	= FWRO + 0x4128,
154 	FWLTHTSR3	= FWRO + 0x412c,
155 	FWLTHTSR40	= FWRO + 0x4130,
156 	FWLTHTSR5	= FWRO + 0x4140,
157 	FWLTHTR		= FWRO + 0x4150,
158 	FWLTHTRR0	= FWRO + 0x4154,
159 	FWLTHTRR1	= FWRO + 0x4158,
160 	FWLTHTRR2	= FWRO + 0x415c,
161 	FWLTHTRR3	= FWRO + 0x4160,
162 	FWLTHTRR4	= FWRO + 0x4164,
163 	FWLTHTRR5	= FWRO + 0x4168,
164 	FWLTHTRR6	= FWRO + 0x416c,
165 	FWLTHTRR7	= FWRO + 0x4170,
166 	FWLTHTRR8	= FWRO + 0x4174,
167 	FWLTHTRR9	= FWRO + 0x4180,
168 	FWLTHTRR10	= FWRO + 0x4190,
169 	FWIPHEC		= FWRO + 0x4214,
170 	FWIPHC		= FWRO + 0x4218,
171 	FWIPTL0		= FWRO + 0x4220,
172 	FWIPTL1		= FWRO + 0x4224,
173 	FWIPTL2		= FWRO + 0x4228,
174 	FWIPTL3		= FWRO + 0x422c,
175 	FWIPTL4		= FWRO + 0x4230,
176 	FWIPTL5		= FWRO + 0x4234,
177 	FWIPTL6		= FWRO + 0x4238,
178 	FWIPTL7		= FWRO + 0x4240,
179 	FWIPTL8		= FWRO + 0x4250,
180 	FWIPTLR		= FWRO + 0x4254,
181 	FWIPTIM		= FWRO + 0x4260,
182 	FWIPTEM		= FWRO + 0x4264,
183 	FWIPTS0		= FWRO + 0x4270,
184 	FWIPTS1		= FWRO + 0x4274,
185 	FWIPTS2		= FWRO + 0x4278,
186 	FWIPTS3		= FWRO + 0x427c,
187 	FWIPTS4		= FWRO + 0x4280,
188 	FWIPTSR0	= FWRO + 0x4284,
189 	FWIPTSR1	= FWRO + 0x4288,
190 	FWIPTSR2	= FWRO + 0x428c,
191 	FWIPTSR3	= FWRO + 0x4290,
192 	FWIPTSR4	= FWRO + 0x42a0,
193 	FWIPTR		= FWRO + 0x42b0,
194 	FWIPTRR0	= FWRO + 0x42b4,
195 	FWIPTRR1	= FWRO + 0x42b8,
196 	FWIPTRR2	= FWRO + 0x42bc,
197 	FWIPTRR3	= FWRO + 0x42c0,
198 	FWIPTRR4	= FWRO + 0x42c4,
199 	FWIPTRR5	= FWRO + 0x42c8,
200 	FWIPTRR6	= FWRO + 0x42cc,
201 	FWIPTRR7	= FWRO + 0x42d0,
202 	FWIPTRR8	= FWRO + 0x42e0,
203 	FWIPTRR9	= FWRO + 0x42f0,
204 	FWIPHLEC	= FWRO + 0x4300,
205 	FWIPAGUSPC	= FWRO + 0x4500,
206 	FWIPAGC		= FWRO + 0x4504,
207 	FWIPAGM0	= FWRO + 0x4510,
208 	FWIPAGM1	= FWRO + 0x4514,
209 	FWIPAGM2	= FWRO + 0x4518,
210 	FWIPAGM3	= FWRO + 0x451c,
211 	FWIPAGM4	= FWRO + 0x4520,
212 	FWMACHEC	= FWRO + 0x4620,
213 	FWMACHC		= FWRO + 0x4624,
214 	FWMACTL0	= FWRO + 0x4630,
215 	FWMACTL1	= FWRO + 0x4634,
216 	FWMACTL2	= FWRO + 0x4638,
217 	FWMACTL3	= FWRO + 0x463c,
218 	FWMACTL4	= FWRO + 0x4640,
219 	FWMACTL5	= FWRO + 0x4650,
220 	FWMACTLR	= FWRO + 0x4654,
221 	FWMACTIM	= FWRO + 0x4660,
222 	FWMACTEM	= FWRO + 0x4664,
223 	FWMACTS0	= FWRO + 0x4670,
224 	FWMACTS1	= FWRO + 0x4674,
225 	FWMACTSR0	= FWRO + 0x4678,
226 	FWMACTSR1	= FWRO + 0x467c,
227 	FWMACTSR2	= FWRO + 0x4680,
228 	FWMACTSR3	= FWRO + 0x4690,
229 	FWMACTR		= FWRO + 0x46a0,
230 	FWMACTRR0	= FWRO + 0x46a4,
231 	FWMACTRR1	= FWRO + 0x46a8,
232 	FWMACTRR2	= FWRO + 0x46ac,
233 	FWMACTRR3	= FWRO + 0x46b0,
234 	FWMACTRR4	= FWRO + 0x46b4,
235 	FWMACTRR5	= FWRO + 0x46c0,
236 	FWMACTRR6	= FWRO + 0x46d0,
237 	FWMACHLEC	= FWRO + 0x4700,
238 	FWMACAGUSPC	= FWRO + 0x4880,
239 	FWMACAGC	= FWRO + 0x4884,
240 	FWMACAGM0	= FWRO + 0x4888,
241 	FWMACAGM1	= FWRO + 0x488c,
242 	FWVLANTEC	= FWRO + 0x4900,
243 	FWVLANTL0	= FWRO + 0x4910,
244 	FWVLANTL1	= FWRO + 0x4914,
245 	FWVLANTL2	= FWRO + 0x4918,
246 	FWVLANTL3	= FWRO + 0x4920,
247 	FWVLANTL4	= FWRO + 0x4930,
248 	FWVLANTLR	= FWRO + 0x4934,
249 	FWVLANTIM	= FWRO + 0x4940,
250 	FWVLANTEM	= FWRO + 0x4944,
251 	FWVLANTS	= FWRO + 0x4950,
252 	FWVLANTSR0	= FWRO + 0x4954,
253 	FWVLANTSR1	= FWRO + 0x4958,
254 	FWVLANTSR2	= FWRO + 0x4960,
255 	FWVLANTSR3	= FWRO + 0x4970,
256 	FWPBFC0		= FWRO + 0x4a00,
257 	FWPBFCSDC00	= FWRO + 0x4a04,
258 	FWL23URL0	= FWRO + 0x4e00,
259 	FWL23URL1	= FWRO + 0x4e04,
260 	FWL23URL2	= FWRO + 0x4e08,
261 	FWL23URL3	= FWRO + 0x4e0c,
262 	FWL23URLR	= FWRO + 0x4e10,
263 	FWL23UTIM	= FWRO + 0x4e20,
264 	FWL23URR	= FWRO + 0x4e30,
265 	FWL23URRR0	= FWRO + 0x4e34,
266 	FWL23URRR1	= FWRO + 0x4e38,
267 	FWL23URRR2	= FWRO + 0x4e3c,
268 	FWL23URRR3	= FWRO + 0x4e40,
269 	FWL23URMC0	= FWRO + 0x4f00,
270 	FWPMFGC0	= FWRO + 0x5000,
271 	FWPGFC0		= FWRO + 0x5100,
272 	FWPGFIGSC0	= FWRO + 0x5104,
273 	FWPGFENC0	= FWRO + 0x5108,
274 	FWPGFENM0	= FWRO + 0x510c,
275 	FWPGFCSTC00	= FWRO + 0x5110,
276 	FWPGFCSTC10	= FWRO + 0x5114,
277 	FWPGFCSTM00	= FWRO + 0x5118,
278 	FWPGFCSTM10	= FWRO + 0x511c,
279 	FWPGFCTC0	= FWRO + 0x5120,
280 	FWPGFCTM0	= FWRO + 0x5124,
281 	FWPGFHCC0	= FWRO + 0x5128,
282 	FWPGFSM0	= FWRO + 0x512c,
283 	FWPGFGC0	= FWRO + 0x5130,
284 	FWPGFGL0	= FWRO + 0x5500,
285 	FWPGFGL1	= FWRO + 0x5504,
286 	FWPGFGLR	= FWRO + 0x5518,
287 	FWPGFGR		= FWRO + 0x5510,
288 	FWPGFGRR0	= FWRO + 0x5514,
289 	FWPGFGRR1	= FWRO + 0x5518,
290 	FWPGFRIM	= FWRO + 0x5520,
291 	FWPMTRFC0	= FWRO + 0x5600,
292 	FWPMTRCBSC0	= FWRO + 0x5604,
293 	FWPMTRC0RC0	= FWRO + 0x5608,
294 	FWPMTREBSC0	= FWRO + 0x560c,
295 	FWPMTREIRC0	= FWRO + 0x5610,
296 	FWPMTRFM0	= FWRO + 0x5614,
297 	FWFTL0		= FWRO + 0x6000,
298 	FWFTL1		= FWRO + 0x6004,
299 	FWFTLR		= FWRO + 0x6008,
300 	FWFTOC		= FWRO + 0x6010,
301 	FWFTOPC		= FWRO + 0x6014,
302 	FWFTIM		= FWRO + 0x6020,
303 	FWFTR		= FWRO + 0x6030,
304 	FWFTRR0		= FWRO + 0x6034,
305 	FWFTRR1		= FWRO + 0x6038,
306 	FWFTRR2		= FWRO + 0x603c,
307 	FWSEQNGC0	= FWRO + 0x6100,
308 	FWSEQNGM0	= FWRO + 0x6104,
309 	FWSEQNRC	= FWRO + 0x6200,
310 	FWCTFDCN0	= FWRO + 0x6300,
311 	FWLTHFDCN0	= FWRO + 0x6304,
312 	FWIPFDCN0	= FWRO + 0x6308,
313 	FWLTWFDCN0	= FWRO + 0x630c,
314 	FWPBFDCN0	= FWRO + 0x6310,
315 	FWMHLCN0	= FWRO + 0x6314,
316 	FWIHLCN0	= FWRO + 0x6318,
317 	FWICRDCN0	= FWRO + 0x6500,
318 	FWWMRDCN0	= FWRO + 0x6504,
319 	FWCTRDCN0	= FWRO + 0x6508,
320 	FWLTHRDCN0	= FWRO + 0x650c,
321 	FWIPRDCN0	= FWRO + 0x6510,
322 	FWLTWRDCN0	= FWRO + 0x6514,
323 	FWPBRDCN0	= FWRO + 0x6518,
324 	FWPMFDCN0	= FWRO + 0x6700,
325 	FWPGFDCN0	= FWRO + 0x6780,
326 	FWPMGDCN0	= FWRO + 0x6800,
327 	FWPMYDCN0	= FWRO + 0x6804,
328 	FWPMRDCN0	= FWRO + 0x6808,
329 	FWFRPPCN0	= FWRO + 0x6a00,
330 	FWFRDPCN0	= FWRO + 0x6a04,
331 	FWEIS00		= FWRO + 0x7900,
332 	FWEIE00		= FWRO + 0x7904,
333 	FWEID00		= FWRO + 0x7908,
334 	FWEIS1		= FWRO + 0x7a00,
335 	FWEIE1		= FWRO + 0x7a04,
336 	FWEID1		= FWRO + 0x7a08,
337 	FWEIS2		= FWRO + 0x7a10,
338 	FWEIE2		= FWRO + 0x7a14,
339 	FWEID2		= FWRO + 0x7a18,
340 	FWEIS3		= FWRO + 0x7a20,
341 	FWEIE3		= FWRO + 0x7a24,
342 	FWEID3		= FWRO + 0x7a28,
343 	FWEIS4		= FWRO + 0x7a30,
344 	FWEIE4		= FWRO + 0x7a34,
345 	FWEID4		= FWRO + 0x7a38,
346 	FWEIS5		= FWRO + 0x7a40,
347 	FWEIE5		= FWRO + 0x7a44,
348 	FWEID5		= FWRO + 0x7a48,
349 	FWEIS60		= FWRO + 0x7a50,
350 	FWEIE60		= FWRO + 0x7a54,
351 	FWEID60		= FWRO + 0x7a58,
352 	FWEIS61		= FWRO + 0x7a60,
353 	FWEIE61		= FWRO + 0x7a64,
354 	FWEID61		= FWRO + 0x7a68,
355 	FWEIS62		= FWRO + 0x7a70,
356 	FWEIE62		= FWRO + 0x7a74,
357 	FWEID62		= FWRO + 0x7a78,
358 	FWEIS63		= FWRO + 0x7a80,
359 	FWEIE63		= FWRO + 0x7a84,
360 	FWEID63		= FWRO + 0x7a88,
361 	FWEIS70		= FWRO + 0x7a90,
362 	FWEIE70		= FWRO + 0x7A94,
363 	FWEID70		= FWRO + 0x7a98,
364 	FWEIS71		= FWRO + 0x7aa0,
365 	FWEIE71		= FWRO + 0x7aa4,
366 	FWEID71		= FWRO + 0x7aa8,
367 	FWEIS72		= FWRO + 0x7ab0,
368 	FWEIE72		= FWRO + 0x7ab4,
369 	FWEID72		= FWRO + 0x7ab8,
370 	FWEIS73		= FWRO + 0x7ac0,
371 	FWEIE73		= FWRO + 0x7ac4,
372 	FWEID73		= FWRO + 0x7ac8,
373 	FWEIS80		= FWRO + 0x7ad0,
374 	FWEIE80		= FWRO + 0x7ad4,
375 	FWEID80		= FWRO + 0x7ad8,
376 	FWEIS81		= FWRO + 0x7ae0,
377 	FWEIE81		= FWRO + 0x7ae4,
378 	FWEID81		= FWRO + 0x7ae8,
379 	FWEIS82		= FWRO + 0x7af0,
380 	FWEIE82		= FWRO + 0x7af4,
381 	FWEID82		= FWRO + 0x7af8,
382 	FWEIS83		= FWRO + 0x7b00,
383 	FWEIE83		= FWRO + 0x7b04,
384 	FWEID83		= FWRO + 0x7b08,
385 	FWMIS0		= FWRO + 0x7c00,
386 	FWMIE0		= FWRO + 0x7c04,
387 	FWMID0		= FWRO + 0x7c08,
388 	FWSCR0		= FWRO + 0x7d00,
389 	FWSCR1		= FWRO + 0x7d04,
390 	FWSCR2		= FWRO + 0x7d08,
391 	FWSCR3		= FWRO + 0x7d0c,
392 	FWSCR4		= FWRO + 0x7d10,
393 	FWSCR5		= FWRO + 0x7d14,
394 	FWSCR6		= FWRO + 0x7d18,
395 	FWSCR7		= FWRO + 0x7d1c,
396 	FWSCR8		= FWRO + 0x7d20,
397 	FWSCR9		= FWRO + 0x7d24,
398 	FWSCR10		= FWRO + 0x7d28,
399 	FWSCR11		= FWRO + 0x7d2c,
400 	FWSCR12		= FWRO + 0x7d30,
401 	FWSCR13		= FWRO + 0x7d34,
402 	FWSCR14		= FWRO + 0x7d38,
403 	FWSCR15		= FWRO + 0x7d3c,
404 	FWSCR16		= FWRO + 0x7d40,
405 	FWSCR17		= FWRO + 0x7d44,
406 	FWSCR18		= FWRO + 0x7d48,
407 	FWSCR19		= FWRO + 0x7d4c,
408 	FWSCR20		= FWRO + 0x7d50,
409 	FWSCR21		= FWRO + 0x7d54,
410 	FWSCR22		= FWRO + 0x7d58,
411 	FWSCR23		= FWRO + 0x7d5c,
412 	FWSCR24		= FWRO + 0x7d60,
413 	FWSCR25		= FWRO + 0x7d64,
414 	FWSCR26		= FWRO + 0x7d68,
415 	FWSCR27		= FWRO + 0x7d6c,
416 	FWSCR28		= FWRO + 0x7d70,
417 	FWSCR29		= FWRO + 0x7d74,
418 	FWSCR30		= FWRO + 0x7d78,
419 	FWSCR31		= FWRO + 0x7d7c,
420 	FWSCR32		= FWRO + 0x7d80,
421 	FWSCR33		= FWRO + 0x7d84,
422 	FWSCR34		= FWRO + 0x7d88,
423 	FWSCR35		= FWRO + 0x7d8c,
424 	FWSCR36		= FWRO + 0x7d90,
425 	FWSCR37		= FWRO + 0x7d94,
426 	FWSCR38		= FWRO + 0x7d98,
427 	FWSCR39		= FWRO + 0x7d9c,
428 	FWSCR40		= FWRO + 0x7da0,
429 	FWSCR41		= FWRO + 0x7da4,
430 	FWSCR42		= FWRO + 0x7da8,
431 	FWSCR43		= FWRO + 0x7dac,
432 	FWSCR44		= FWRO + 0x7db0,
433 	FWSCR45		= FWRO + 0x7db4,
434 	FWSCR46		= FWRO + 0x7db8,
435 
436 	TPEMIMC0	= TPRO + 0x0000,
437 	TPEMIMC1	= TPRO + 0x0004,
438 	TPEMIMC2	= TPRO + 0x0008,
439 	TPEMIMC3	= TPRO + 0x000c,
440 	TPEMIMC4	= TPRO + 0x0010,
441 	TPEMIMC5	= TPRO + 0x0014,
442 	TPEMIMC60	= TPRO + 0x0080,
443 	TPEMIMC70	= TPRO + 0x0100,
444 	TSIM		= TPRO + 0x0700,
445 	TFIM		= TPRO + 0x0704,
446 	TCIM		= TPRO + 0x0708,
447 	TGIM0		= TPRO + 0x0710,
448 	TGIM1		= TPRO + 0x0714,
449 	TEIM0		= TPRO + 0x0720,
450 	TEIM1		= TPRO + 0x0724,
451 	TEIM2		= TPRO + 0x0728,
452 
453 	RIPV		= CARO + 0x0000,
454 	RRC		= CARO + 0x0004,
455 	RCEC		= CARO + 0x0008,
456 	RCDC		= CARO + 0x000c,
457 	RSSIS		= CARO + 0x0010,
458 	RSSIE		= CARO + 0x0014,
459 	RSSID		= CARO + 0x0018,
460 	CABPIBWMC	= CARO + 0x0020,
461 	CABPWMLC	= CARO + 0x0040,
462 	CABPPFLC0	= CARO + 0x0050,
463 	CABPPWMLC0	= CARO + 0x0060,
464 	CABPPPFLC00	= CARO + 0x00a0,
465 	CABPULC		= CARO + 0x0100,
466 	CABPIRM		= CARO + 0x0140,
467 	CABPPCM		= CARO + 0x0144,
468 	CABPLCM		= CARO + 0x0148,
469 	CABPCPM		= CARO + 0x0180,
470 	CABPMCPM	= CARO + 0x0200,
471 	CARDNM		= CARO + 0x0280,
472 	CARDMNM		= CARO + 0x0284,
473 	CARDCN		= CARO + 0x0290,
474 	CAEIS0		= CARO + 0x0300,
475 	CAEIE0		= CARO + 0x0304,
476 	CAEID0		= CARO + 0x0308,
477 	CAEIS1		= CARO + 0x0310,
478 	CAEIE1		= CARO + 0x0314,
479 	CAEID1		= CARO + 0x0318,
480 	CAMIS0		= CARO + 0x0340,
481 	CAMIE0		= CARO + 0x0344,
482 	CAMID0		= CARO + 0x0348,
483 	CAMIS1		= CARO + 0x0350,
484 	CAMIE1		= CARO + 0x0354,
485 	CAMID1		= CARO + 0x0358,
486 	CASCR		= CARO + 0x0380,
487 
488 	EAMC		= TARO + 0x0000,
489 	EAMS		= TARO + 0x0004,
490 	EAIRC		= TARO + 0x0010,
491 	EATDQSC		= TARO + 0x0014,
492 	EATDQC		= TARO + 0x0018,
493 	EATDQAC		= TARO + 0x001c,
494 	EATPEC		= TARO + 0x0020,
495 	EATMFSC0	= TARO + 0x0040,
496 	EATDQDC0	= TARO + 0x0060,
497 	EATDQM0		= TARO + 0x0080,
498 	EATDQMLM0	= TARO + 0x00a0,
499 	EACTQC		= TARO + 0x0100,
500 	EACTDQDC	= TARO + 0x0104,
501 	EACTDQM		= TARO + 0x0108,
502 	EACTDQMLM	= TARO + 0x010c,
503 	EAVCC		= TARO + 0x0130,
504 	EAVTC		= TARO + 0x0134,
505 	EATTFC		= TARO + 0x0138,
506 	EACAEC		= TARO + 0x0200,
507 	EACC		= TARO + 0x0204,
508 	EACAIVC0	= TARO + 0x0220,
509 	EACAULC0	= TARO + 0x0240,
510 	EACOEM		= TARO + 0x0260,
511 	EACOIVM0	= TARO + 0x0280,
512 	EACOULM0	= TARO + 0x02a0,
513 	EACGSM		= TARO + 0x02c0,
514 	EATASC		= TARO + 0x0300,
515 	EATASENC0	= TARO + 0x0320,
516 	EATASCTENC	= TARO + 0x0340,
517 	EATASENM0	= TARO + 0x0360,
518 	EATASCTENM	= TARO + 0x0380,
519 	EATASCSTC0	= TARO + 0x03a0,
520 	EATASCSTC1	= TARO + 0x03a4,
521 	EATASCSTM0	= TARO + 0x03a8,
522 	EATASCSTM1	= TARO + 0x03ac,
523 	EATASCTC	= TARO + 0x03b0,
524 	EATASCTM	= TARO + 0x03b4,
525 	EATASGL0	= TARO + 0x03c0,
526 	EATASGL1	= TARO + 0x03c4,
527 	EATASGLR	= TARO + 0x03c8,
528 	EATASGR		= TARO + 0x03d0,
529 	EATASGRR	= TARO + 0x03d4,
530 	EATASHCC	= TARO + 0x03e0,
531 	EATASRIRM	= TARO + 0x03e4,
532 	EATASSM		= TARO + 0x03e8,
533 	EAUSMFSECN	= TARO + 0x0400,
534 	EATFECN		= TARO + 0x0404,
535 	EAFSECN		= TARO + 0x0408,
536 	EADQOECN	= TARO + 0x040c,
537 	EADQSECN	= TARO + 0x0410,
538 	EACKSECN	= TARO + 0x0414,
539 	EAEIS0		= TARO + 0x0500,
540 	EAEIE0		= TARO + 0x0504,
541 	EAEID0		= TARO + 0x0508,
542 	EAEIS1		= TARO + 0x0510,
543 	EAEIE1		= TARO + 0x0514,
544 	EAEID1		= TARO + 0x0518,
545 	EAEIS2		= TARO + 0x0520,
546 	EAEIE2		= TARO + 0x0524,
547 	EAEID2		= TARO + 0x0528,
548 	EASCR		= TARO + 0x0580,
549 
550 	MPSM		= RMRO + 0x0000,
551 	MPIC		= RMRO + 0x0004,
552 	MPIM		= RMRO + 0x0008,
553 	MIOC		= RMRO + 0x0010,
554 	MIOM		= RMRO + 0x0014,
555 	MXMS		= RMRO + 0x0018,
556 	MTFFC		= RMRO + 0x0020,
557 	MTPFC		= RMRO + 0x0024,
558 	MTPFC2		= RMRO + 0x0028,
559 	MTPFC30		= RMRO + 0x0030,
560 	MTATC0		= RMRO + 0x0050,
561 	MTIM		= RMRO + 0x0060,
562 	MRGC		= RMRO + 0x0080,
563 	MRMAC0		= RMRO + 0x0084,
564 	MRMAC1		= RMRO + 0x0088,
565 	MRAFC		= RMRO + 0x008c,
566 	MRSCE		= RMRO + 0x0090,
567 	MRSCP		= RMRO + 0x0094,
568 	MRSCC		= RMRO + 0x0098,
569 	MRFSCE		= RMRO + 0x009c,
570 	MRFSCP		= RMRO + 0x00a0,
571 	MTRC		= RMRO + 0x00a4,
572 	MRIM		= RMRO + 0x00a8,
573 	MRPFM		= RMRO + 0x00ac,
574 	MPFC0		= RMRO + 0x0100,
575 	MLVC		= RMRO + 0x0180,
576 	MEEEC		= RMRO + 0x0184,
577 	MLBC		= RMRO + 0x0188,
578 	MXGMIIC		= RMRO + 0x0190,
579 	MPCH		= RMRO + 0x0194,
580 	MANC		= RMRO + 0x0198,
581 	MANM		= RMRO + 0x019c,
582 	MPLCA1		= RMRO + 0x01a0,
583 	MPLCA2		= RMRO + 0x01a4,
584 	MPLCA3		= RMRO + 0x01a8,
585 	MPLCA4		= RMRO + 0x01ac,
586 	MPLCAM		= RMRO + 0x01b0,
587 	MHDC1		= RMRO + 0x01c0,
588 	MHDC2		= RMRO + 0x01c4,
589 	MEIS		= RMRO + 0x0200,
590 	MEIE		= RMRO + 0x0204,
591 	MEID		= RMRO + 0x0208,
592 	MMIS0		= RMRO + 0x0210,
593 	MMIE0		= RMRO + 0x0214,
594 	MMID0		= RMRO + 0x0218,
595 	MMIS1		= RMRO + 0x0220,
596 	MMIE1		= RMRO + 0x0224,
597 	MMID1		= RMRO + 0x0228,
598 	MMIS2		= RMRO + 0x0230,
599 	MMIE2		= RMRO + 0x0234,
600 	MMID2		= RMRO + 0x0238,
601 	MMPFTCT		= RMRO + 0x0300,
602 	MAPFTCT		= RMRO + 0x0304,
603 	MPFRCT		= RMRO + 0x0308,
604 	MFCICT		= RMRO + 0x030c,
605 	MEEECT		= RMRO + 0x0310,
606 	MMPCFTCT0	= RMRO + 0x0320,
607 	MAPCFTCT0	= RMRO + 0x0330,
608 	MPCFRCT0	= RMRO + 0x0340,
609 	MHDCC		= RMRO + 0x0350,
610 	MROVFC		= RMRO + 0x0354,
611 	MRHCRCEC	= RMRO + 0x0358,
612 	MRXBCE		= RMRO + 0x0400,
613 	MRXBCP		= RMRO + 0x0404,
614 	MRGFCE		= RMRO + 0x0408,
615 	MRGFCP		= RMRO + 0x040c,
616 	MRBFC		= RMRO + 0x0410,
617 	MRMFC		= RMRO + 0x0414,
618 	MRUFC		= RMRO + 0x0418,
619 	MRPEFC		= RMRO + 0x041c,
620 	MRNEFC		= RMRO + 0x0420,
621 	MRFMEFC		= RMRO + 0x0424,
622 	MRFFMEFC	= RMRO + 0x0428,
623 	MRCFCEFC	= RMRO + 0x042c,
624 	MRFCEFC		= RMRO + 0x0430,
625 	MRRCFEFC	= RMRO + 0x0434,
626 	MRUEFC		= RMRO + 0x043c,
627 	MROEFC		= RMRO + 0x0440,
628 	MRBOEC		= RMRO + 0x0444,
629 	MTXBCE		= RMRO + 0x0500,
630 	MTXBCP		= RMRO + 0x0504,
631 	MTGFCE		= RMRO + 0x0508,
632 	MTGFCP		= RMRO + 0x050c,
633 	MTBFC		= RMRO + 0x0510,
634 	MTMFC		= RMRO + 0x0514,
635 	MTUFC		= RMRO + 0x0518,
636 	MTEFC		= RMRO + 0x051c,
637 
638 	GWMC		= GWRO + 0x0000,
639 	GWMS		= GWRO + 0x0004,
640 	GWIRC		= GWRO + 0x0010,
641 	GWRDQSC		= GWRO + 0x0014,
642 	GWRDQC		= GWRO + 0x0018,
643 	GWRDQAC		= GWRO + 0x001c,
644 	GWRGC		= GWRO + 0x0020,
645 	GWRMFSC0	= GWRO + 0x0040,
646 	GWRDQDC0	= GWRO + 0x0060,
647 	GWRDQM0		= GWRO + 0x0080,
648 	GWRDQMLM0	= GWRO + 0x00a0,
649 	GWMTIRM		= GWRO + 0x0100,
650 	GWMSTLS		= GWRO + 0x0104,
651 	GWMSTLR		= GWRO + 0x0108,
652 	GWMSTSS		= GWRO + 0x010c,
653 	GWMSTSR		= GWRO + 0x0110,
654 	GWMAC0		= GWRO + 0x0120,
655 	GWMAC1		= GWRO + 0x0124,
656 	GWVCC		= GWRO + 0x0130,
657 	GWVTC		= GWRO + 0x0134,
658 	GWTTFC		= GWRO + 0x0138,
659 	GWTDCAC00	= GWRO + 0x0140,
660 	GWTDCAC10	= GWRO + 0x0144,
661 	GWTSDCC0	= GWRO + 0x0160,
662 	GWTNM		= GWRO + 0x0180,
663 	GWTMNM		= GWRO + 0x0184,
664 	GWAC		= GWRO + 0x0190,
665 	GWDCBAC0	= GWRO + 0x0194,
666 	GWDCBAC1	= GWRO + 0x0198,
667 	GWIICBSC	= GWRO + 0x019c,
668 	GWMDNC		= GWRO + 0x01a0,
669 	GWTRC0		= GWRO + 0x0200,
670 	GWTPC0		= GWRO + 0x0300,
671 	GWARIRM		= GWRO + 0x0380,
672 	GWDCC0		= GWRO + 0x0400,
673 	GWAARSS		= GWRO + 0x0800,
674 	GWAARSR0	= GWRO + 0x0804,
675 	GWAARSR1	= GWRO + 0x0808,
676 	GWIDAUAS0	= GWRO + 0x0840,
677 	GWIDASM0	= GWRO + 0x0880,
678 	GWIDASAM00	= GWRO + 0x0900,
679 	GWIDASAM10	= GWRO + 0x0904,
680 	GWIDACAM00	= GWRO + 0x0980,
681 	GWIDACAM10	= GWRO + 0x0984,
682 	GWGRLC		= GWRO + 0x0a00,
683 	GWGRLULC	= GWRO + 0x0a04,
684 	GWRLIVC0	= GWRO + 0x0a80,
685 	GWRLULC0	= GWRO + 0x0a84,
686 	GWIDPC		= GWRO + 0x0b00,
687 	GWIDC0		= GWRO + 0x0c00,
688 	GWDIS0		= GWRO + 0x1100,
689 	GWDIE0		= GWRO + 0x1104,
690 	GWDID0		= GWRO + 0x1108,
691 	GWTSDIS		= GWRO + 0x1180,
692 	GWTSDIE		= GWRO + 0x1184,
693 	GWTSDID		= GWRO + 0x1188,
694 	GWEIS0		= GWRO + 0x1190,
695 	GWEIE0		= GWRO + 0x1194,
696 	GWEID0		= GWRO + 0x1198,
697 	GWEIS1		= GWRO + 0x11a0,
698 	GWEIE1		= GWRO + 0x11a4,
699 	GWEID1		= GWRO + 0x11a8,
700 	GWEIS20		= GWRO + 0x1200,
701 	GWEIE20		= GWRO + 0x1204,
702 	GWEID20		= GWRO + 0x1208,
703 	GWEIS3		= GWRO + 0x1280,
704 	GWEIE3		= GWRO + 0x1284,
705 	GWEID3		= GWRO + 0x1288,
706 	GWEIS4		= GWRO + 0x1290,
707 	GWEIE4		= GWRO + 0x1294,
708 	GWEID4		= GWRO + 0x1298,
709 	GWEIS5		= GWRO + 0x12a0,
710 	GWEIE5		= GWRO + 0x12a4,
711 	GWEID5		= GWRO + 0x12a8,
712 	GWSCR0		= GWRO + 0x1800,
713 	GWSCR1		= GWRO + 0x1900,
714 };
715 
716 /* ETHA/RMAC */
717 enum rswitch_etha_mode {
718 	EAMC_OPC_RESET,
719 	EAMC_OPC_DISABLE,
720 	EAMC_OPC_CONFIG,
721 	EAMC_OPC_OPERATION,
722 };
723 
724 #define EAMS_OPS_MASK		EAMC_OPC_OPERATION
725 
726 #define EAVCC_VEM_SC_TAG	(0x3 << 16)
727 
728 #define MPIC_PIS		GENMASK(2, 0)
729 #define MPIC_PIS_GMII		2
730 #define MPIC_PIS_XGMII		4
731 #define MPIC_LSC		GENMASK(5, 3)
732 #define MPIC_LSC_100M		1
733 #define MPIC_LSC_1G		2
734 #define MPIC_LSC_2_5G		3
735 #define MPIC_PSMCS		GENMASK(22, 16)
736 #define MPIC_PSMHT		GENMASK(26, 24)
737 
738 #define MPSM_PSME		BIT(0)
739 #define MPSM_MFF		BIT(2)
740 #define MPSM_MMF_C22		0
741 #define MPSM_MMF_C45		1
742 #define MPSM_PDA		GENMASK(7, 3)
743 #define MPSM_PRA		GENMASK(12, 8)
744 #define MPSM_POP		GENMASK(14, 13)
745 #define MPSM_POP_ADDRESS	0
746 #define MPSM_POP_WRITE		1
747 #define MPSM_POP_READ_C22	2
748 #define MPSM_POP_READ_C45	3
749 #define MPSM_PRD		GENMASK(31, 16)
750 
751 #define MLVC_PLV		BIT(16)
752 
753 /* GWCA */
754 enum rswitch_gwca_mode {
755 	GWMC_OPC_RESET,
756 	GWMC_OPC_DISABLE,
757 	GWMC_OPC_CONFIG,
758 	GWMC_OPC_OPERATION,
759 };
760 
761 #define GWMS_OPS_MASK		GWMC_OPC_OPERATION
762 
763 #define GWMTIRM_MTIOG		BIT(0)
764 #define GWMTIRM_MTR		BIT(1)
765 
766 #define GWVCC_VEM_SC_TAG	(0x3 << 16)
767 
768 #define GWARIRM_ARIOG		BIT(0)
769 #define GWARIRM_ARR		BIT(1)
770 
771 #define GWMDNC_TSDMN(num)	(((num) << 16) & GENMASK(17, 16))
772 #define GWMDNC_TXDMN(num)	(((num) << 8) & GENMASK(12, 8))
773 #define GWMDNC_RXDMN(num)	((num) & GENMASK(4, 0))
774 
775 #define GWDCC_BALR		BIT(24)
776 #define GWDCC_DCP_MASK		GENMASK(18, 16)
777 #define GWDCC_DCP(prio)		FIELD_PREP(GWDCC_DCP_MASK, (prio))
778 #define GWDCC_DQT		BIT(11)
779 #define GWDCC_ETS		BIT(9)
780 #define GWDCC_EDE		BIT(8)
781 
782 #define GWTRC(queue)		(GWTRC0 + (queue) / 32 * 4)
783 #define GWTPC_PPPL(ipv)		BIT(ipv)
784 #define GWDCC_OFFS(queue)	(GWDCC0 + (queue) * 4)
785 
786 #define GWDIS(i)		(GWDIS0 + (i) * 0x10)
787 #define GWDIE(i)		(GWDIE0 + (i) * 0x10)
788 #define GWDID(i)		(GWDID0 + (i) * 0x10)
789 
790 /* COMA */
791 #define RRC_RR			BIT(0)
792 #define RRC_RR_CLR		0
793 #define	RCEC_ACE_DEFAULT	(BIT(0) | BIT(AGENT_INDEX_GWCA))
794 #define RCEC_RCE		BIT(16)
795 #define RCDC_RCD		BIT(16)
796 
797 #define CABPIRM_BPIOG		BIT(0)
798 #define CABPIRM_BPR		BIT(1)
799 
800 #define CABPPFLC_INIT_VALUE	0x00800080
801 
802 /* MFWD */
803 #define FWPC0(i)		(FWPC00 + (i) * 0x10)
804 #define FWPC0_LTHTA		BIT(0)
805 #define FWPC0_IP4UE		BIT(3)
806 #define FWPC0_IP4TE		BIT(4)
807 #define FWPC0_IP4OE		BIT(5)
808 #define FWPC0_L2SE		BIT(9)
809 #define FWPC0_IP4EA		BIT(10)
810 #define FWPC0_IPDSA		BIT(12)
811 #define FWPC0_IPHLA		BIT(18)
812 #define FWPC0_MACSDA		BIT(20)
813 #define FWPC0_MACHLA		BIT(26)
814 #define FWPC0_MACHMA		BIT(27)
815 #define FWPC0_VLANSA		BIT(28)
816 
817 #define FWPC1(i)		(FWPC10 + (i) * 0x10)
818 #define FWCP1_LTHFW		GENMASK(16 + (RSWITCH_NUM_AGENTS - 1), 16)
819 #define FWPC1_DDE		BIT(0)
820 
821 #define FWPC2(i)		(FWPC20 + (i) * 0x10)
822 #define FWCP2_LTWFW		GENMASK(16 + (RSWITCH_NUM_AGENTS - 1), 16)
823 
824 #define FWPBFC(i)		(FWPBFC0 + (i) * 0x10)
825 #define FWPBFC_PBDV		GENMASK(RSWITCH_NUM_AGENTS - 1, 0)
826 
827 #define FWPBFCSDC(j, i)         (FWPBFCSDC00 + (i) * 0x10 + (j) * 0x04)
828 
829 /* TOP */
830 #define TPEMIMC7(queue)		(TPEMIMC70 + (queue) * 4)
831 
832 /* Descriptors */
833 enum RX_DS_CC_BIT {
834 	RX_DS	= 0x0fff, /* Data size */
835 	RX_TR	= 0x1000, /* Truncation indication */
836 	RX_EI	= 0x2000, /* Error indication */
837 	RX_PS	= 0xc000, /* Padding selection */
838 };
839 
840 enum TX_DS_TAGL_BIT {
841 	TX_DS	= 0x0fff, /* Data size */
842 	TX_TAGL	= 0xf000, /* Frame tag LSBs */
843 };
844 
845 enum DIE_DT {
846 	/* Frame data */
847 	DT_FSINGLE	= 0x80,
848 	DT_FSTART	= 0x90,
849 	DT_FMID		= 0xa0,
850 	DT_FEND		= 0xb0,
851 
852 	/* Chain control */
853 	DT_LEMPTY	= 0xc0,
854 	DT_EEMPTY	= 0xd0,
855 	DT_LINKFIX	= 0x00,
856 	DT_LINK		= 0xe0,
857 	DT_EOS		= 0xf0,
858 	/* HW/SW arbitration */
859 	DT_FEMPTY	= 0x40,
860 	DT_FEMPTY_IS	= 0x10,
861 	DT_FEMPTY_IC	= 0x20,
862 	DT_FEMPTY_ND	= 0x30,
863 	DT_FEMPTY_START	= 0x50,
864 	DT_FEMPTY_MID	= 0x60,
865 	DT_FEMPTY_END	= 0x70,
866 
867 	DT_MASK		= 0xf0,
868 	DIE		= 0x08,	/* Descriptor Interrupt Enable */
869 };
870 
871 /* Both transmission and reception */
872 #define INFO1_FMT		BIT(2)
873 #define INFO1_TXC		BIT(3)
874 
875 /* For transmission */
876 #define INFO1_TSUN(val)		((u64)(val) << 8ULL)
877 #define INFO1_IPV(prio)		((u64)(prio) << 28ULL)
878 #define INFO1_CSD0(index)	((u64)(index) << 32ULL)
879 #define INFO1_CSD1(index)	((u64)(index) << 40ULL)
880 #define INFO1_DV(port_vector)	((u64)(port_vector) << 48ULL)
881 
882 /* For reception */
883 #define INFO1_SPN(port)		((u64)(port) << 36ULL)
884 
885 /* For timestamp descriptor in dptrl (Byte 4 to 7) */
886 #define TS_DESC_TSUN(dptrl)	((dptrl) & GENMASK(7, 0))
887 #define TS_DESC_SPN(dptrl)	(((dptrl) & GENMASK(10, 8)) >> 8)
888 #define TS_DESC_DPN(dptrl)	(((dptrl) & GENMASK(17, 16)) >> 16)
889 #define TS_DESC_TN(dptrl)	((dptrl) & BIT(24))
890 
891 struct rswitch_desc {
892 	__le16 info_ds;	/* Descriptor size */
893 	u8 die_dt;	/* Descriptor interrupt enable and type */
894 	__u8  dptrh;	/* Descriptor pointer MSB */
895 	__le32 dptrl;	/* Descriptor pointer LSW */
896 } __packed;
897 
898 struct rswitch_ts_desc {
899 	struct rswitch_desc desc;
900 	__le32 ts_nsec;
901 	__le32 ts_sec;
902 } __packed;
903 
904 struct rswitch_ext_desc {
905 	struct rswitch_desc desc;
906 	__le64 info1;
907 } __packed;
908 
909 struct rswitch_ext_ts_desc {
910 	struct rswitch_desc desc;
911 	__le64 info1;
912 	__le32 ts_nsec;
913 	__le32 ts_sec;
914 } __packed;
915 
916 struct rswitch_etha {
917 	unsigned int index;
918 	void __iomem *addr;
919 	void __iomem *coma_addr;
920 	bool external_phy;
921 	struct mii_bus *mii;
922 	phy_interface_t phy_interface;
923 	u32 psmcs;
924 	u8 mac_addr[MAX_ADDR_LEN];
925 	int link;
926 	int speed;
927 
928 	/* This hardware could not be initialized twice so that marked
929 	 * this flag to avoid multiple initialization.
930 	 */
931 	bool operated;
932 };
933 
934 /* The datasheet said descriptor "chain" and/or "queue". For consistency of
935  * name, this driver calls "queue".
936  */
937 struct rswitch_gwca_queue {
938 	union {
939 		struct rswitch_ext_desc *tx_ring;
940 		struct rswitch_ext_ts_desc *rx_ring;
941 		struct rswitch_ts_desc *ts_ring;
942 	};
943 
944 	/* Common */
945 	dma_addr_t ring_dma;
946 	unsigned int ring_size;
947 	unsigned int cur;
948 	unsigned int dirty;
949 
950 	/* For [rt]x_ring */
951 	unsigned int index;
952 	bool dir_tx;
953 	struct net_device *ndev;	/* queue to ndev for irq */
954 
955 	union {
956 		/* For TX */
957 		struct {
958 			struct sk_buff **skbs;
959 			dma_addr_t *unmap_addrs;
960 		};
961 		/* For RX */
962 		struct {
963 			void **rx_bufs;
964 			struct sk_buff *skb_fstart;
965 			u16 pkt_len;
966 		};
967 	};
968 };
969 
970 #define RSWITCH_NUM_IRQ_REGS	(RSWITCH_MAX_NUM_QUEUES / BITS_PER_TYPE(u32))
971 struct rswitch_gwca {
972 	unsigned int index;
973 	struct rswitch_desc *linkfix_table;
974 	dma_addr_t linkfix_table_dma;
975 	u32 linkfix_table_size;
976 	struct rswitch_gwca_queue *queues;
977 	int num_queues;
978 	struct rswitch_gwca_queue ts_queue;
979 	DECLARE_BITMAP(used, RSWITCH_MAX_NUM_QUEUES);
980 	u32 tx_irq_bits[RSWITCH_NUM_IRQ_REGS];
981 	u32 rx_irq_bits[RSWITCH_NUM_IRQ_REGS];
982 };
983 
984 #define NUM_QUEUES_PER_NDEV	2
985 #define TS_TAGS_PER_PORT	256
986 struct rswitch_device {
987 	struct rswitch_private *priv;
988 	struct net_device *ndev;
989 	struct napi_struct napi;
990 	void __iomem *addr;
991 	struct rswitch_gwca_queue *tx_queue;
992 	struct rswitch_gwca_queue *rx_queue;
993 	struct sk_buff *ts_skb[TS_TAGS_PER_PORT];
994 	DECLARE_BITMAP(ts_skb_used, TS_TAGS_PER_PORT);
995 	bool disabled;
996 
997 	int port;
998 	struct rswitch_etha *etha;
999 	struct device_node *np_port;
1000 	struct phy *serdes;
1001 };
1002 
1003 struct rswitch_mfwd_mac_table_entry {
1004 	int queue_index;
1005 	unsigned char addr[MAX_ADDR_LEN];
1006 };
1007 
1008 struct rswitch_mfwd {
1009 	struct rswitch_mac_table_entry *mac_table_entries;
1010 	int num_mac_table_entries;
1011 };
1012 
1013 struct rswitch_private {
1014 	struct platform_device *pdev;
1015 	void __iomem *addr;
1016 	struct rcar_gen4_ptp_private *ptp_priv;
1017 
1018 	struct rswitch_device *rdev[RSWITCH_NUM_PORTS];
1019 	DECLARE_BITMAP(opened_ports, RSWITCH_NUM_PORTS);
1020 
1021 	struct rswitch_gwca gwca;
1022 	struct rswitch_etha etha[RSWITCH_NUM_PORTS];
1023 	struct rswitch_mfwd mfwd;
1024 
1025 	spinlock_t lock;	/* lock interrupt registers' control */
1026 	struct clk *clk;
1027 
1028 	bool etha_no_runtime_change;
1029 	bool gwca_halt;
1030 };
1031 
1032 #endif	/* #ifndef __RSWITCH_H__ */
1033