1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #ifndef __RTW89_MAC_H__
6 #define __RTW89_MAC_H__
7
8 #include "core.h"
9 #include "fw.h"
10 #include "reg.h"
11
12 #define MAC_MEM_DUMP_PAGE_SIZE_AX 0x40000
13 #define MAC_MEM_DUMP_PAGE_SIZE_BE 0x80000
14
15 #define ADDR_CAM_ENT_SIZE 0x40
16 #define ADDR_CAM_ENT_SHORT_SIZE 0x20
17 #define BSSID_CAM_ENT_SIZE 0x08
18 #define HFC_PAGE_UNIT 64
19 #define RPWM_TRY_CNT 3
20
21 enum rtw89_mac_hwmod_sel {
22 RTW89_DMAC_SEL = 0,
23 RTW89_CMAC_SEL = 1,
24
25 RTW89_MAC_INVALID,
26 };
27
28 enum rtw89_mac_fwd_target {
29 RTW89_FWD_DONT_CARE = 0,
30 RTW89_FWD_TO_HOST = 1,
31 RTW89_FWD_TO_WLAN_CPU = 2
32 };
33
34 enum rtw89_mac_wd_dma_intvl {
35 RTW89_MAC_WD_DMA_INTVL_0S,
36 RTW89_MAC_WD_DMA_INTVL_256NS,
37 RTW89_MAC_WD_DMA_INTVL_512NS,
38 RTW89_MAC_WD_DMA_INTVL_768NS,
39 RTW89_MAC_WD_DMA_INTVL_1US,
40 RTW89_MAC_WD_DMA_INTVL_1_5US,
41 RTW89_MAC_WD_DMA_INTVL_2US,
42 RTW89_MAC_WD_DMA_INTVL_4US,
43 RTW89_MAC_WD_DMA_INTVL_8US,
44 RTW89_MAC_WD_DMA_INTVL_16US,
45 RTW89_MAC_WD_DMA_INTVL_DEF = 0xFE
46 };
47
48 enum rtw89_mac_multi_tag_num {
49 RTW89_MAC_TAG_NUM_1,
50 RTW89_MAC_TAG_NUM_2,
51 RTW89_MAC_TAG_NUM_3,
52 RTW89_MAC_TAG_NUM_4,
53 RTW89_MAC_TAG_NUM_5,
54 RTW89_MAC_TAG_NUM_6,
55 RTW89_MAC_TAG_NUM_7,
56 RTW89_MAC_TAG_NUM_8,
57 RTW89_MAC_TAG_NUM_DEF = 0xFE
58 };
59
60 enum rtw89_mac_lbc_tmr {
61 RTW89_MAC_LBC_TMR_8US = 0,
62 RTW89_MAC_LBC_TMR_16US,
63 RTW89_MAC_LBC_TMR_32US,
64 RTW89_MAC_LBC_TMR_64US,
65 RTW89_MAC_LBC_TMR_128US,
66 RTW89_MAC_LBC_TMR_256US,
67 RTW89_MAC_LBC_TMR_512US,
68 RTW89_MAC_LBC_TMR_1MS,
69 RTW89_MAC_LBC_TMR_2MS,
70 RTW89_MAC_LBC_TMR_4MS,
71 RTW89_MAC_LBC_TMR_8MS,
72 RTW89_MAC_LBC_TMR_DEF = 0xFE
73 };
74
75 enum rtw89_mac_cpuio_op_cmd_type {
76 CPUIO_OP_CMD_GET_1ST_PID = 0,
77 CPUIO_OP_CMD_GET_NEXT_PID = 1,
78 CPUIO_OP_CMD_ENQ_TO_TAIL = 4,
79 CPUIO_OP_CMD_ENQ_TO_HEAD = 5,
80 CPUIO_OP_CMD_DEQ = 8,
81 CPUIO_OP_CMD_DEQ_ENQ_ALL = 9,
82 CPUIO_OP_CMD_DEQ_ENQ_TO_TAIL = 12
83 };
84
85 enum rtw89_mac_wde_dle_port_id {
86 WDE_DLE_PORT_ID_DISPATCH = 0,
87 WDE_DLE_PORT_ID_PKTIN = 1,
88 WDE_DLE_PORT_ID_CMAC0 = 3,
89 WDE_DLE_PORT_ID_CMAC1 = 4,
90 WDE_DLE_PORT_ID_CPU_IO = 6,
91 WDE_DLE_PORT_ID_WDRLS = 7,
92 WDE_DLE_PORT_ID_END = 8
93 };
94
95 enum rtw89_mac_wde_dle_queid_wdrls {
96 WDE_DLE_QUEID_TXOK = 0,
97 WDE_DLE_QUEID_DROP_RETRY_LIMIT = 1,
98 WDE_DLE_QUEID_DROP_LIFETIME_TO = 2,
99 WDE_DLE_QUEID_DROP_MACID_DROP = 3,
100 WDE_DLE_QUEID_NO_REPORT = 4
101 };
102
103 enum rtw89_mac_ple_dle_port_id {
104 PLE_DLE_PORT_ID_DISPATCH = 0,
105 PLE_DLE_PORT_ID_MPDU = 1,
106 PLE_DLE_PORT_ID_SEC = 2,
107 PLE_DLE_PORT_ID_CMAC0 = 3,
108 PLE_DLE_PORT_ID_CMAC1 = 4,
109 PLE_DLE_PORT_ID_WDRLS = 5,
110 PLE_DLE_PORT_ID_CPU_IO = 6,
111 PLE_DLE_PORT_ID_PLRLS = 7,
112 PLE_DLE_PORT_ID_END = 8
113 };
114
115 enum rtw89_mac_ple_dle_queid_plrls {
116 PLE_DLE_QUEID_NO_REPORT = 0x0
117 };
118
119 enum rtw89_machdr_frame_type {
120 RTW89_MGNT = 0,
121 RTW89_CTRL = 1,
122 RTW89_DATA = 2,
123 };
124
125 enum rtw89_mac_dle_dfi_type {
126 DLE_DFI_TYPE_FREEPG = 0,
127 DLE_DFI_TYPE_QUOTA = 1,
128 DLE_DFI_TYPE_PAGELLT = 2,
129 DLE_DFI_TYPE_PKTINFO = 3,
130 DLE_DFI_TYPE_PREPKTLLT = 4,
131 DLE_DFI_TYPE_NXTPKTLLT = 5,
132 DLE_DFI_TYPE_QLNKTBL = 6,
133 DLE_DFI_TYPE_QEMPTY = 7,
134 };
135
136 enum rtw89_mac_dle_wde_quota_id {
137 WDE_QTAID_HOST_IF = 0,
138 WDE_QTAID_WLAN_CPU = 1,
139 WDE_QTAID_DATA_CPU = 2,
140 WDE_QTAID_PKTIN = 3,
141 WDE_QTAID_CPUIO = 4,
142 };
143
144 enum rtw89_mac_dle_ple_quota_id {
145 PLE_QTAID_B0_TXPL = 0,
146 PLE_QTAID_B1_TXPL = 1,
147 PLE_QTAID_C2H = 2,
148 PLE_QTAID_H2C = 3,
149 PLE_QTAID_WLAN_CPU = 4,
150 PLE_QTAID_MPDU = 5,
151 PLE_QTAID_CMAC0_RX = 6,
152 PLE_QTAID_CMAC1_RX = 7,
153 PLE_QTAID_CMAC1_BBRPT = 8,
154 PLE_QTAID_WDRLS = 9,
155 PLE_QTAID_CPUIO = 10,
156 };
157
158 enum rtw89_mac_dle_ctrl_type {
159 DLE_CTRL_TYPE_WDE = 0,
160 DLE_CTRL_TYPE_PLE = 1,
161 DLE_CTRL_TYPE_NUM = 2,
162 };
163
164 enum rtw89_mac_ax_l0_to_l1_event {
165 MAC_AX_L0_TO_L1_CHIF_IDLE = 0,
166 MAC_AX_L0_TO_L1_CMAC_DMA_IDLE = 1,
167 MAC_AX_L0_TO_L1_RLS_PKID = 2,
168 MAC_AX_L0_TO_L1_PTCL_IDLE = 3,
169 MAC_AX_L0_TO_L1_RX_QTA_LOST = 4,
170 MAC_AX_L0_TO_L1_DLE_STAT_HANG = 5,
171 MAC_AX_L0_TO_L1_PCIE_STUCK = 6,
172 MAC_AX_L0_TO_L1_EVENT_MAX = 15,
173 };
174
175 enum rtw89_mac_phy_rpt_size {
176 MAC_AX_PHY_RPT_SIZE_0 = 0,
177 MAC_AX_PHY_RPT_SIZE_8 = 1,
178 MAC_AX_PHY_RPT_SIZE_16 = 2,
179 MAC_AX_PHY_RPT_SIZE_24 = 3,
180 };
181
182 enum rtw89_mac_hdr_cnv_size {
183 MAC_AX_HDR_CNV_SIZE_0 = 0,
184 MAC_AX_HDR_CNV_SIZE_32 = 1,
185 MAC_AX_HDR_CNV_SIZE_64 = 2,
186 MAC_AX_HDR_CNV_SIZE_96 = 3,
187 };
188
189 enum rtw89_mac_wow_fw_status {
190 WOWLAN_NOT_READY = 0x00,
191 WOWLAN_SLEEP_READY = 0x01,
192 WOWLAN_RESUME_READY = 0x02,
193 };
194
195 #define RTW89_PORT_OFFSET_TU_TO_32US(shift_tu) ((shift_tu) * 1024 / 32)
196
197 enum rtw89_mac_dbg_port_sel {
198 /* CMAC 0 related */
199 RTW89_DBG_PORT_SEL_PTCL_C0 = 0,
200 RTW89_DBG_PORT_SEL_SCH_C0,
201 RTW89_DBG_PORT_SEL_TMAC_C0,
202 RTW89_DBG_PORT_SEL_RMAC_C0,
203 RTW89_DBG_PORT_SEL_RMACST_C0,
204 RTW89_DBG_PORT_SEL_RMAC_PLCP_C0,
205 RTW89_DBG_PORT_SEL_TRXPTCL_C0,
206 RTW89_DBG_PORT_SEL_TX_INFOL_C0,
207 RTW89_DBG_PORT_SEL_TX_INFOH_C0,
208 RTW89_DBG_PORT_SEL_TXTF_INFOL_C0,
209 RTW89_DBG_PORT_SEL_TXTF_INFOH_C0,
210 /* CMAC 1 related */
211 RTW89_DBG_PORT_SEL_PTCL_C1,
212 RTW89_DBG_PORT_SEL_SCH_C1,
213 RTW89_DBG_PORT_SEL_TMAC_C1,
214 RTW89_DBG_PORT_SEL_RMAC_C1,
215 RTW89_DBG_PORT_SEL_RMACST_C1,
216 RTW89_DBG_PORT_SEL_RMAC_PLCP_C1,
217 RTW89_DBG_PORT_SEL_TRXPTCL_C1,
218 RTW89_DBG_PORT_SEL_TX_INFOL_C1,
219 RTW89_DBG_PORT_SEL_TX_INFOH_C1,
220 RTW89_DBG_PORT_SEL_TXTF_INFOL_C1,
221 RTW89_DBG_PORT_SEL_TXTF_INFOH_C1,
222 /* DLE related */
223 RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG,
224 RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA,
225 RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT,
226 RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO,
227 RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT,
228 RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT,
229 RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL,
230 RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY,
231 RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG,
232 RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA,
233 RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT,
234 RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO,
235 RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT,
236 RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT,
237 RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL,
238 RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY,
239 RTW89_DBG_PORT_SEL_PKTINFO,
240 /* DISPATCHER related */
241 RTW89_DBG_PORT_SEL_DSPT_HDT_TX0,
242 RTW89_DBG_PORT_SEL_DSPT_HDT_TX1,
243 RTW89_DBG_PORT_SEL_DSPT_HDT_TX2,
244 RTW89_DBG_PORT_SEL_DSPT_HDT_TX3,
245 RTW89_DBG_PORT_SEL_DSPT_HDT_TX4,
246 RTW89_DBG_PORT_SEL_DSPT_HDT_TX5,
247 RTW89_DBG_PORT_SEL_DSPT_HDT_TX6,
248 RTW89_DBG_PORT_SEL_DSPT_HDT_TX7,
249 RTW89_DBG_PORT_SEL_DSPT_HDT_TX8,
250 RTW89_DBG_PORT_SEL_DSPT_HDT_TX9,
251 RTW89_DBG_PORT_SEL_DSPT_HDT_TXA,
252 RTW89_DBG_PORT_SEL_DSPT_HDT_TXB,
253 RTW89_DBG_PORT_SEL_DSPT_HDT_TXC,
254 RTW89_DBG_PORT_SEL_DSPT_HDT_TXD,
255 RTW89_DBG_PORT_SEL_DSPT_HDT_TXE,
256 RTW89_DBG_PORT_SEL_DSPT_HDT_TXF,
257 RTW89_DBG_PORT_SEL_DSPT_CDT_TX0,
258 RTW89_DBG_PORT_SEL_DSPT_CDT_TX1,
259 RTW89_DBG_PORT_SEL_DSPT_CDT_TX3,
260 RTW89_DBG_PORT_SEL_DSPT_CDT_TX4,
261 RTW89_DBG_PORT_SEL_DSPT_CDT_TX5,
262 RTW89_DBG_PORT_SEL_DSPT_CDT_TX6,
263 RTW89_DBG_PORT_SEL_DSPT_CDT_TX7,
264 RTW89_DBG_PORT_SEL_DSPT_CDT_TX8,
265 RTW89_DBG_PORT_SEL_DSPT_CDT_TX9,
266 RTW89_DBG_PORT_SEL_DSPT_CDT_TXA,
267 RTW89_DBG_PORT_SEL_DSPT_CDT_TXB,
268 RTW89_DBG_PORT_SEL_DSPT_CDT_TXC,
269 RTW89_DBG_PORT_SEL_DSPT_HDT_RX0,
270 RTW89_DBG_PORT_SEL_DSPT_HDT_RX1,
271 RTW89_DBG_PORT_SEL_DSPT_HDT_RX2,
272 RTW89_DBG_PORT_SEL_DSPT_HDT_RX3,
273 RTW89_DBG_PORT_SEL_DSPT_HDT_RX4,
274 RTW89_DBG_PORT_SEL_DSPT_HDT_RX5,
275 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0,
276 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_0,
277 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_1,
278 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_2,
279 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P1,
280 RTW89_DBG_PORT_SEL_DSPT_STF_CTRL,
281 RTW89_DBG_PORT_SEL_DSPT_ADDR_CTRL,
282 RTW89_DBG_PORT_SEL_DSPT_WDE_INTF,
283 RTW89_DBG_PORT_SEL_DSPT_PLE_INTF,
284 RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL,
285 /* PCIE related */
286 RTW89_DBG_PORT_SEL_PCIE_TXDMA,
287 RTW89_DBG_PORT_SEL_PCIE_RXDMA,
288 RTW89_DBG_PORT_SEL_PCIE_CVT,
289 RTW89_DBG_PORT_SEL_PCIE_CXPL,
290 RTW89_DBG_PORT_SEL_PCIE_IO,
291 RTW89_DBG_PORT_SEL_PCIE_MISC,
292 RTW89_DBG_PORT_SEL_PCIE_MISC2,
293
294 /* keep last */
295 RTW89_DBG_PORT_SEL_LAST,
296 RTW89_DBG_PORT_SEL_MAX = RTW89_DBG_PORT_SEL_LAST,
297 RTW89_DBG_PORT_SEL_INVALID = RTW89_DBG_PORT_SEL_LAST,
298 };
299
300 /* SRAM mem dump */
301 #define R_AX_INDIR_ACCESS_ENTRY 0x40000
302 #define R_BE_INDIR_ACCESS_ENTRY 0x80000
303
304 #define AXIDMA_BASE_ADDR 0x18006000
305 #define STA_SCHED_BASE_ADDR 0x18808000
306 #define RXPLD_FLTR_CAM_BASE_ADDR 0x18813000
307 #define SECURITY_CAM_BASE_ADDR 0x18814000
308 #define WOW_CAM_BASE_ADDR 0x18815000
309 #define CMAC_TBL_BASE_ADDR 0x18840000
310 #define ADDR_CAM_BASE_ADDR 0x18850000
311 #define BSSID_CAM_BASE_ADDR 0x18853000
312 #define BA_CAM_BASE_ADDR 0x18854000
313 #define BCN_IE_CAM0_BASE_ADDR 0x18855000
314 #define SHARED_BUF_BASE_ADDR 0x18700000
315 #define DMAC_TBL_BASE_ADDR 0x18800000
316 #define SHCUT_MACHDR_BASE_ADDR 0x18800800
317 #define BCN_IE_CAM1_BASE_ADDR 0x188A0000
318 #define TXD_FIFO_0_BASE_ADDR 0x18856200
319 #define TXD_FIFO_1_BASE_ADDR 0x188A1080
320 #define TXD_FIFO_0_BASE_ADDR_V1 0x18856400 /* for 8852C */
321 #define TXD_FIFO_1_BASE_ADDR_V1 0x188A1080 /* for 8852C */
322 #define TXDATA_FIFO_0_BASE_ADDR 0x18856000
323 #define TXDATA_FIFO_1_BASE_ADDR 0x188A1000
324 #define CPU_LOCAL_BASE_ADDR 0x18003000
325
326 #define WD_PAGE_BASE_ADDR_BE 0x0
327 #define CPU_LOCAL_BASE_ADDR_BE 0x18003000
328 #define AXIDMA_BASE_ADDR_BE 0x18006000
329 #define SHARED_BUF_BASE_ADDR_BE 0x18700000
330 #define DMAC_TBL_BASE_ADDR_BE 0x18800000
331 #define SHCUT_MACHDR_BASE_ADDR_BE 0x18800800
332 #define STA_SCHED_BASE_ADDR_BE 0x18818000
333 #define NAT25_CAM_BASE_ADDR_BE 0x18820000
334 #define RXPLD_FLTR_CAM_BASE_ADDR_BE 0x18823000
335 #define SEC_CAM_BASE_ADDR_BE 0x18824000
336 #define WOW_CAM_BASE_ADDR_BE 0x18828000
337 #define MLD_TBL_BASE_ADDR_BE 0x18829000
338 #define RX_CLSF_CAM_BASE_ADDR_BE 0x1882A000
339 #define CMAC_TBL_BASE_ADDR_BE 0x18840000
340 #define ADDR_CAM_BASE_ADDR_BE 0x18850000
341 #define BSSID_CAM_BASE_ADDR_BE 0x18858000
342 #define BA_CAM_BASE_ADDR_BE 0x18859000
343 #define BCN_IE_CAM0_BASE_ADDR_BE 0x18860000
344 #define TXDATA_FIFO_0_BASE_ADDR_BE 0x18861000
345 #define TXD_FIFO_0_BASE_ADDR_BE 0x18862000
346 #define BCN_IE_CAM1_BASE_ADDR_BE 0x18880000
347 #define TXDATA_FIFO_1_BASE_ADDR_BE 0x18881000
348 #define TXD_FIFO_1_BASE_ADDR_BE 0x18881800
349 #define DCPU_LOCAL_BASE_ADDR_BE 0x19C02000
350
351 #define CCTL_INFO_SIZE 32
352
353 enum rtw89_mac_mem_sel {
354 RTW89_MAC_MEM_AXIDMA,
355 RTW89_MAC_MEM_SHARED_BUF,
356 RTW89_MAC_MEM_DMAC_TBL,
357 RTW89_MAC_MEM_SHCUT_MACHDR,
358 RTW89_MAC_MEM_STA_SCHED,
359 RTW89_MAC_MEM_RXPLD_FLTR_CAM,
360 RTW89_MAC_MEM_SECURITY_CAM,
361 RTW89_MAC_MEM_WOW_CAM,
362 RTW89_MAC_MEM_CMAC_TBL,
363 RTW89_MAC_MEM_ADDR_CAM,
364 RTW89_MAC_MEM_BA_CAM,
365 RTW89_MAC_MEM_BCN_IE_CAM0,
366 RTW89_MAC_MEM_BCN_IE_CAM1,
367 RTW89_MAC_MEM_TXD_FIFO_0,
368 RTW89_MAC_MEM_TXD_FIFO_1,
369 RTW89_MAC_MEM_TXDATA_FIFO_0,
370 RTW89_MAC_MEM_TXDATA_FIFO_1,
371 RTW89_MAC_MEM_CPU_LOCAL,
372 RTW89_MAC_MEM_BSSID_CAM,
373 RTW89_MAC_MEM_TXD_FIFO_0_V1,
374 RTW89_MAC_MEM_TXD_FIFO_1_V1,
375 RTW89_MAC_MEM_WD_PAGE,
376 RTW89_MAC_MEM_MLD_TBL,
377
378 /* keep last */
379 RTW89_MAC_MEM_NUM,
380 };
381
382 enum rtw89_rpwm_req_pwr_state {
383 RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE = 0,
384 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFON = 1,
385 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFON = 2,
386 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF = 3,
387 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFOFF = 4,
388 RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED = 5,
389 RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED = 6,
390 RTW89_MAC_RPWM_REQ_PWR_STATE_HIOE_PWR_GATED = 7,
391 RTW89_MAC_RPWM_REQ_PWR_STATE_MAX,
392 };
393
394 struct rtw89_pwr_cfg {
395 u16 addr;
396 u8 cv_msk;
397 u8 intf_msk;
398 u8 base:4;
399 u8 cmd:4;
400 u8 msk;
401 u8 val;
402 };
403
404 enum rtw89_mac_c2h_ofld_func {
405 RTW89_MAC_C2H_FUNC_EFUSE_DUMP,
406 RTW89_MAC_C2H_FUNC_READ_RSP,
407 RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP,
408 RTW89_MAC_C2H_FUNC_BCN_RESEND,
409 RTW89_MAC_C2H_FUNC_MACID_PAUSE,
410 RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT = 0x6,
411 RTW89_MAC_C2H_FUNC_SCANOFLD_RSP = 0x9,
412 RTW89_MAC_C2H_FUNC_TX_DUTY_RPT = 0xa,
413 RTW89_MAC_C2H_FUNC_BCNFLTR_RPT = 0xd,
414 RTW89_MAC_C2H_FUNC_OFLD_MAX,
415 };
416
417 enum rtw89_mac_c2h_info_func {
418 RTW89_MAC_C2H_FUNC_REC_ACK,
419 RTW89_MAC_C2H_FUNC_DONE_ACK,
420 RTW89_MAC_C2H_FUNC_C2H_LOG,
421 RTW89_MAC_C2H_FUNC_BCN_CNT,
422 RTW89_MAC_C2H_FUNC_INFO_MAX,
423 };
424
425 enum rtw89_mac_c2h_mcc_func {
426 RTW89_MAC_C2H_FUNC_MCC_RCV_ACK = 0,
427 RTW89_MAC_C2H_FUNC_MCC_REQ_ACK = 1,
428 RTW89_MAC_C2H_FUNC_MCC_TSF_RPT = 2,
429 RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT = 3,
430
431 NUM_OF_RTW89_MAC_C2H_FUNC_MCC,
432 };
433
434 enum rtw89_mac_c2h_mlo_func {
435 RTW89_MAC_C2H_FUNC_MLO_GET_TBL = 0x0,
436 RTW89_MAC_C2H_FUNC_MLO_EMLSR_TRANS_DONE = 0x1,
437 RTW89_MAC_C2H_FUNC_MLO_EMLSR_STA_CFG_DONE = 0x2,
438 RTW89_MAC_C2H_FUNC_MCMLO_RELINK_RPT = 0x3,
439 RTW89_MAC_C2H_FUNC_MCMLO_SN_SYNC_RPT = 0x4,
440 RTW89_MAC_C2H_FUNC_MLO_LINK_CFG_STAT = 0x5,
441 RTW89_MAC_C2H_FUNC_MLO_DM_DBG_DUMP = 0x6,
442
443 NUM_OF_RTW89_MAC_C2H_FUNC_MLO,
444 };
445
446 enum rtw89_mac_c2h_mrc_func {
447 RTW89_MAC_C2H_FUNC_MRC_TSF_RPT = 0,
448 RTW89_MAC_C2H_FUNC_MRC_STATUS_RPT = 1,
449
450 NUM_OF_RTW89_MAC_C2H_FUNC_MRC,
451 };
452
453 enum rtw89_mac_c2h_wow_func {
454 RTW89_MAC_C2H_FUNC_AOAC_REPORT,
455
456 NUM_OF_RTW89_MAC_C2H_FUNC_WOW,
457 };
458
459 enum rtw89_mac_c2h_ap_func {
460 RTW89_MAC_C2H_FUNC_PWR_INT_NOTIFY = 0,
461
462 NUM_OF_RTW89_MAC_C2H_FUNC_AP,
463 };
464
465 enum rtw89_mac_c2h_class {
466 RTW89_MAC_C2H_CLASS_INFO = 0x0,
467 RTW89_MAC_C2H_CLASS_OFLD = 0x1,
468 RTW89_MAC_C2H_CLASS_TWT = 0x2,
469 RTW89_MAC_C2H_CLASS_WOW = 0x3,
470 RTW89_MAC_C2H_CLASS_MCC = 0x4,
471 RTW89_MAC_C2H_CLASS_FWDBG = 0x5,
472 RTW89_MAC_C2H_CLASS_MLO = 0xc,
473 RTW89_MAC_C2H_CLASS_MRC = 0xe,
474 RTW89_MAC_C2H_CLASS_AP = 0x18,
475 RTW89_MAC_C2H_CLASS_ROLE = 0x1b,
476 RTW89_MAC_C2H_CLASS_MAX,
477 };
478
479 enum rtw89_mac_mcc_status {
480 RTW89_MAC_MCC_ADD_ROLE_OK = 0,
481 RTW89_MAC_MCC_START_GROUP_OK = 1,
482 RTW89_MAC_MCC_STOP_GROUP_OK = 2,
483 RTW89_MAC_MCC_DEL_GROUP_OK = 3,
484 RTW89_MAC_MCC_RESET_GROUP_OK = 4,
485 RTW89_MAC_MCC_SWITCH_CH_OK = 5,
486 RTW89_MAC_MCC_TXNULL0_OK = 6,
487 RTW89_MAC_MCC_TXNULL1_OK = 7,
488
489 RTW89_MAC_MCC_SWITCH_EARLY = 10,
490 RTW89_MAC_MCC_TBTT = 11,
491 RTW89_MAC_MCC_DURATION_START = 12,
492 RTW89_MAC_MCC_DURATION_END = 13,
493
494 RTW89_MAC_MCC_ADD_ROLE_FAIL = 20,
495 RTW89_MAC_MCC_START_GROUP_FAIL = 21,
496 RTW89_MAC_MCC_STOP_GROUP_FAIL = 22,
497 RTW89_MAC_MCC_DEL_GROUP_FAIL = 23,
498 RTW89_MAC_MCC_RESET_GROUP_FAIL = 24,
499 RTW89_MAC_MCC_SWITCH_CH_FAIL = 25,
500 RTW89_MAC_MCC_TXNULL0_FAIL = 26,
501 RTW89_MAC_MCC_TXNULL1_FAIL = 27,
502 };
503
504 enum rtw89_mac_mrc_status {
505 RTW89_MAC_MRC_START_SCH_OK = 0,
506 RTW89_MAC_MRC_STOP_SCH_OK = 1,
507 RTW89_MAC_MRC_DEL_SCH_OK = 2,
508 RTW89_MAC_MRC_EMPTY_SCH_FAIL = 16,
509 RTW89_MAC_MRC_ROLE_NOT_EXIST_FAIL = 17,
510 RTW89_MAC_MRC_DATA_NOT_FOUND_FAIL = 18,
511 RTW89_MAC_MRC_GET_NEXT_SLOT_FAIL = 19,
512 RTW89_MAC_MRC_ALT_ROLE_FAIL = 20,
513 RTW89_MAC_MRC_ADD_PSTIMER_FAIL = 21,
514 RTW89_MAC_MRC_MALLOC_FAIL = 22,
515 RTW89_MAC_MRC_SWITCH_CH_FAIL = 23,
516 RTW89_MAC_MRC_TXNULL0_FAIL = 24,
517 RTW89_MAC_MRC_PORT_FUNC_EN_FAIL = 25,
518 };
519
520 struct rtw89_mac_ax_coex {
521 #define RTW89_MAC_AX_COEX_RTK_MODE 0
522 #define RTW89_MAC_AX_COEX_CSR_MODE 1
523 u8 pta_mode;
524 #define RTW89_MAC_AX_COEX_INNER 0
525 #define RTW89_MAC_AX_COEX_OUTPUT 1
526 #define RTW89_MAC_AX_COEX_INPUT 2
527 u8 direction;
528 };
529
530 struct rtw89_mac_ax_plt {
531 #define RTW89_MAC_AX_PLT_LTE_RX BIT(0)
532 #define RTW89_MAC_AX_PLT_GNT_BT_TX BIT(1)
533 #define RTW89_MAC_AX_PLT_GNT_BT_RX BIT(2)
534 #define RTW89_MAC_AX_PLT_GNT_WL BIT(3)
535 u8 band;
536 u8 tx;
537 u8 rx;
538 };
539
540 enum rtw89_mac_bf_rrsc_rate {
541 RTW89_MAC_BF_RRSC_6M = 0,
542 RTW89_MAC_BF_RRSC_9M = 1,
543 RTW89_MAC_BF_RRSC_12M,
544 RTW89_MAC_BF_RRSC_18M,
545 RTW89_MAC_BF_RRSC_24M,
546 RTW89_MAC_BF_RRSC_36M,
547 RTW89_MAC_BF_RRSC_48M,
548 RTW89_MAC_BF_RRSC_54M,
549 RTW89_MAC_BF_RRSC_HT_MSC0,
550 RTW89_MAC_BF_RRSC_HT_MSC1,
551 RTW89_MAC_BF_RRSC_HT_MSC2,
552 RTW89_MAC_BF_RRSC_HT_MSC3,
553 RTW89_MAC_BF_RRSC_HT_MSC4,
554 RTW89_MAC_BF_RRSC_HT_MSC5,
555 RTW89_MAC_BF_RRSC_HT_MSC6,
556 RTW89_MAC_BF_RRSC_HT_MSC7,
557 RTW89_MAC_BF_RRSC_VHT_MSC0,
558 RTW89_MAC_BF_RRSC_VHT_MSC1,
559 RTW89_MAC_BF_RRSC_VHT_MSC2,
560 RTW89_MAC_BF_RRSC_VHT_MSC3,
561 RTW89_MAC_BF_RRSC_VHT_MSC4,
562 RTW89_MAC_BF_RRSC_VHT_MSC5,
563 RTW89_MAC_BF_RRSC_VHT_MSC6,
564 RTW89_MAC_BF_RRSC_VHT_MSC7,
565 RTW89_MAC_BF_RRSC_HE_MSC0,
566 RTW89_MAC_BF_RRSC_HE_MSC1,
567 RTW89_MAC_BF_RRSC_HE_MSC2,
568 RTW89_MAC_BF_RRSC_HE_MSC3,
569 RTW89_MAC_BF_RRSC_HE_MSC4,
570 RTW89_MAC_BF_RRSC_HE_MSC5,
571 RTW89_MAC_BF_RRSC_HE_MSC6,
572 RTW89_MAC_BF_RRSC_HE_MSC7 = 31,
573 RTW89_MAC_BF_RRSC_MAX = 32
574 };
575
576 #define RTW89_R32_EA 0xEAEAEAEA
577 #define RTW89_R32_DEAD 0xDEADBEEF
578 #define MAC_REG_POOL_COUNT 10
579 #define ACCESS_CMAC(_addr) \
580 ({typeof(_addr) __addr = (_addr); \
581 __addr >= R_AX_CMAC_REG_START && __addr <= R_AX_CMAC_REG_END; })
582 #define RTW89_MAC_AX_BAND_REG_OFFSET 0x2000
583 #define RTW89_MAC_BE_BAND_REG_OFFSET 0x4000
584
585 #define PTCL_IDLE_POLL_CNT 10000
586 #define SW_CVR_DUR_US 8
587 #define SW_CVR_CNT 8
588
589 #define DLE_BOUND_UNIT (8 * 1024)
590 #define DLE_WAIT_CNT 2000
591 #define TRXCFG_WAIT_CNT 2000
592
593 #define RTW89_WDE_PG_64 64
594 #define RTW89_WDE_PG_128 128
595 #define RTW89_WDE_PG_256 256
596
597 #define S_AX_WDE_PAGE_SEL_64 0
598 #define S_AX_WDE_PAGE_SEL_128 1
599 #define S_AX_WDE_PAGE_SEL_256 2
600
601 #define RTW89_PLE_PG_64 64
602 #define RTW89_PLE_PG_128 128
603 #define RTW89_PLE_PG_256 256
604
605 #define S_AX_PLE_PAGE_SEL_64 0
606 #define S_AX_PLE_PAGE_SEL_128 1
607 #define S_AX_PLE_PAGE_SEL_256 2
608
609 #define B_CMAC0_MGQ_NORMAL BIT(2)
610 #define B_CMAC0_MGQ_NO_PWRSAV BIT(3)
611 #define B_CMAC0_CPUMGQ BIT(4)
612 #define B_CMAC1_MGQ_NORMAL BIT(10)
613 #define B_CMAC1_MGQ_NO_PWRSAV BIT(11)
614 #define B_CMAC1_CPUMGQ BIT(12)
615
616 #define B_CMAC0_MGQ_NORMAL_BE BIT(2)
617 #define B_CMAC1_MGQ_NORMAL_BE BIT(30)
618
619 #define QEMP_ACQ_GRP_MACID_NUM 8
620 #define QEMP_ACQ_GRP_QSEL_SH 4
621 #define QEMP_ACQ_GRP_QSEL_MASK 0xF
622
623 #define SDIO_LOCAL_BASE_ADDR 0x80000000
624
625 #define PWR_CMD_WRITE 0
626 #define PWR_CMD_POLL 1
627 #define PWR_CMD_DELAY 2
628 #define PWR_CMD_END 3
629
630 #define PWR_INTF_MSK_SDIO BIT(0)
631 #define PWR_INTF_MSK_USB BIT(1)
632 #define PWR_INTF_MSK_PCIE BIT(2)
633 #define PWR_INTF_MSK_ALL 0x7
634
635 #define PWR_BASE_MAC 0
636 #define PWR_BASE_USB 1
637 #define PWR_BASE_PCIE 2
638 #define PWR_BASE_SDIO 3
639
640 #define PWR_CV_MSK_A BIT(0)
641 #define PWR_CV_MSK_B BIT(1)
642 #define PWR_CV_MSK_C BIT(2)
643 #define PWR_CV_MSK_D BIT(3)
644 #define PWR_CV_MSK_E BIT(4)
645 #define PWR_CV_MSK_F BIT(5)
646 #define PWR_CV_MSK_G BIT(6)
647 #define PWR_CV_MSK_TEST BIT(7)
648 #define PWR_CV_MSK_ALL 0xFF
649
650 #define PWR_DELAY_US 0
651 #define PWR_DELAY_MS 1
652
653 /* STA scheduler */
654 #define SS_MACID_SH 8
655 #define SS_TX_LEN_MSK 0x1FFFFF
656 #define SS_CTRL1_R_TX_LEN 5
657 #define SS_CTRL1_R_NEXT_LINK 20
658 #define SS_LINK_SIZE 256
659
660 /* MAC debug port */
661 #define TMAC_DBG_SEL_C0 0xA5
662 #define RMAC_DBG_SEL_C0 0xA6
663 #define TRXPTCL_DBG_SEL_C0 0xA7
664 #define TMAC_DBG_SEL_C1 0xB5
665 #define RMAC_DBG_SEL_C1 0xB6
666 #define TRXPTCL_DBG_SEL_C1 0xB7
667 #define FW_PROG_CNTR_DBG_SEL 0xF2
668 #define PCIE_TXDMA_DBG_SEL 0x30
669 #define PCIE_RXDMA_DBG_SEL 0x31
670 #define PCIE_CVT_DBG_SEL 0x32
671 #define PCIE_CXPL_DBG_SEL 0x33
672 #define PCIE_IO_DBG_SEL 0x37
673 #define PCIE_MISC_DBG_SEL 0x38
674 #define PCIE_MISC2_DBG_SEL 0x00
675 #define MAC_DBG_SEL 1
676 #define RMAC_CMAC_DBG_SEL 1
677
678 /* TRXPTCL dbg port sel */
679 #define TRXPTRL_DBG_SEL_TMAC 0
680 #define TRXPTRL_DBG_SEL_RMAC 1
681
682 struct rtw89_cpuio_ctrl {
683 u16 pkt_num;
684 u16 start_pktid;
685 u16 end_pktid;
686 u8 cmd_type;
687 u8 macid;
688 u8 src_pid;
689 u8 src_qid;
690 u8 dst_pid;
691 u8 dst_qid;
692 u16 pktid;
693 };
694
695 struct rtw89_mac_dbg_port_info {
696 u32 sel_addr;
697 u8 sel_byte;
698 u32 sel_msk;
699 u32 srt;
700 u32 end;
701 u32 rd_addr;
702 u8 rd_byte;
703 u32 rd_msk;
704 };
705
706 #define QLNKTBL_ADDR_INFO_SEL BIT(0)
707 #define QLNKTBL_ADDR_INFO_SEL_0 0
708 #define QLNKTBL_ADDR_INFO_SEL_1 1
709 #define QLNKTBL_ADDR_TBL_IDX_MASK GENMASK(10, 1)
710 #define QLNKTBL_DATA_SEL1_PKT_CNT_MASK GENMASK(11, 0)
711
712 struct rtw89_mac_dle_dfi_ctrl {
713 enum rtw89_mac_dle_ctrl_type type;
714 u32 target;
715 u32 addr;
716 u32 out_data;
717 };
718
719 struct rtw89_mac_dle_dfi_quota {
720 enum rtw89_mac_dle_ctrl_type dle_type;
721 u32 qtaid;
722 u16 rsv_pgnum;
723 u16 use_pgnum;
724 };
725
726 struct rtw89_mac_dle_dfi_qempty {
727 enum rtw89_mac_dle_ctrl_type dle_type;
728 u32 grpsel;
729 u32 qempty;
730 };
731
732 enum rtw89_mac_dle_rsvd_qt_type {
733 DLE_RSVD_QT_MPDU_INFO,
734 DLE_RSVD_QT_B0_CSI,
735 DLE_RSVD_QT_B1_CSI,
736 DLE_RSVD_QT_B0_LMR,
737 DLE_RSVD_QT_B1_LMR,
738 DLE_RSVD_QT_B0_FTM,
739 DLE_RSVD_QT_B1_FTM,
740 };
741
742 struct rtw89_mac_dle_rsvd_qt_cfg {
743 u16 pktid;
744 u16 pg_num;
745 u32 size;
746 };
747
748 enum rtw89_mac_error_scenario {
749 RTW89_RXI300_ERROR = 1,
750 RTW89_WCPU_CPU_EXCEPTION = 2,
751 RTW89_WCPU_ASSERTION = 3,
752 };
753
754 #define RTW89_ERROR_SCENARIO(__err) ((__err) >> 28)
755
756 /* Define DBG and recovery enum */
757 enum mac_ax_err_info {
758 /* Get error info */
759
760 /* L0 */
761 MAC_AX_ERR_L0_ERR_CMAC0 = 0x0001,
762 MAC_AX_ERR_L0_ERR_CMAC1 = 0x0002,
763 MAC_AX_ERR_L0_RESET_DONE = 0x0003,
764 MAC_AX_ERR_L0_PROMOTE_TO_L1 = 0x0010,
765
766 /* L1 */
767 MAC_AX_ERR_L1_PREERR_DMAC = 0x999,
768 MAC_AX_ERR_L1_ERR_DMAC = 0x1000,
769 MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE = 0x1001,
770 MAC_AX_ERR_L1_RESET_RECOVERY_DONE = 0x1002,
771 MAC_AX_ERR_L1_PROMOTE_TO_L2 = 0x1010,
772 MAC_AX_ERR_L1_RCVY_STOP_DONE = 0x1011,
773
774 /* L2 */
775 /* address hole (master) */
776 MAC_AX_ERR_L2_ERR_AH_DMA = 0x2000,
777 MAC_AX_ERR_L2_ERR_AH_HCI = 0x2010,
778 MAC_AX_ERR_L2_ERR_AH_RLX4081 = 0x2020,
779 MAC_AX_ERR_L2_ERR_AH_IDDMA = 0x2030,
780 MAC_AX_ERR_L2_ERR_AH_HIOE = 0x2040,
781 MAC_AX_ERR_L2_ERR_AH_IPSEC = 0x2050,
782 MAC_AX_ERR_L2_ERR_AH_RX4281 = 0x2060,
783 MAC_AX_ERR_L2_ERR_AH_OTHERS = 0x2070,
784
785 /* AHB bridge timeout (master) */
786 MAC_AX_ERR_L2_ERR_AHB_TO_DMA = 0x2100,
787 MAC_AX_ERR_L2_ERR_AHB_TO_HCI = 0x2110,
788 MAC_AX_ERR_L2_ERR_AHB_TO_RLX4081 = 0x2120,
789 MAC_AX_ERR_L2_ERR_AHB_TO_IDDMA = 0x2130,
790 MAC_AX_ERR_L2_ERR_AHB_TO_HIOE = 0x2140,
791 MAC_AX_ERR_L2_ERR_AHB_TO_IPSEC = 0x2150,
792 MAC_AX_ERR_L2_ERR_AHB_TO_RX4281 = 0x2160,
793 MAC_AX_ERR_L2_ERR_AHB_TO_OTHERS = 0x2170,
794
795 /* APB_SA bridge timeout (master + slave) */
796 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WVA = 0x2200,
797 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_UART = 0x2201,
798 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_CPULOCAL = 0x2202,
799 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_AXIDMA = 0x2203,
800 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_HIOE = 0x2204,
801 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IDDMA = 0x2205,
802 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IPSEC = 0x2206,
803 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WON = 0x2207,
804 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WDMAC = 0x2208,
805 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WCMAC = 0x2209,
806 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_OTHERS = 0x220A,
807 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WVA = 0x2210,
808 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_UART = 0x2211,
809 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_CPULOCAL = 0x2212,
810 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_AXIDMA = 0x2213,
811 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_HIOE = 0x2214,
812 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IDDMA = 0x2215,
813 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IPSEC = 0x2216,
814 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WDMAC = 0x2218,
815 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WCMAC = 0x2219,
816 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_OTHERS = 0x221A,
817 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WVA = 0x2220,
818 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_UART = 0x2221,
819 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_CPULOCAL = 0x2222,
820 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_AXIDMA = 0x2223,
821 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_HIOE = 0x2224,
822 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IDDMA = 0x2225,
823 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IPSEC = 0x2226,
824 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WON = 0x2227,
825 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WDMAC = 0x2228,
826 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WCMAC = 0x2229,
827 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_OTHERS = 0x222A,
828 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WVA = 0x2230,
829 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_UART = 0x2231,
830 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_CPULOCAL = 0x2232,
831 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_AXIDMA = 0x2233,
832 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_HIOE = 0x2234,
833 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IDDMA = 0x2235,
834 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IPSEC = 0x2236,
835 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WON = 0x2237,
836 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WDMAC = 0x2238,
837 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WCMAC = 0x2239,
838 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_OTHERS = 0x223A,
839 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WVA = 0x2240,
840 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_UART = 0x2241,
841 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_CPULOCAL = 0x2242,
842 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_AXIDMA = 0x2243,
843 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_HIOE = 0x2244,
844 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IDDMA = 0x2245,
845 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IPSEC = 0x2246,
846 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WON = 0x2247,
847 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WDMAC = 0x2248,
848 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WCMAC = 0x2249,
849 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_OTHERS = 0x224A,
850 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WVA = 0x2250,
851 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_UART = 0x2251,
852 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_CPULOCAL = 0x2252,
853 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_AXIDMA = 0x2253,
854 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_HIOE = 0x2254,
855 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IDDMA = 0x2255,
856 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IPSEC = 0x2256,
857 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WON = 0x2257,
858 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WDMAC = 0x2258,
859 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WCMAC = 0x2259,
860 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_OTHERS = 0x225A,
861 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WVA = 0x2260,
862 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_UART = 0x2261,
863 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_CPULOCAL = 0x2262,
864 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_AXIDMA = 0x2263,
865 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_HIOE = 0x2264,
866 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IDDMA = 0x2265,
867 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IPSEC = 0x2266,
868 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WON = 0x2267,
869 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WDMAC = 0x2268,
870 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WCMAC = 0x2269,
871 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_OTHERS = 0x226A,
872 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WVA = 0x2270,
873 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_UART = 0x2271,
874 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_CPULOCAL = 0x2272,
875 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_AXIDMA = 0x2273,
876 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_HIOE = 0x2274,
877 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IDDMA = 0x2275,
878 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IPSEC = 0x2276,
879 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WON = 0x2277,
880 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WDMAC = 0x2278,
881 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WCMAC = 0x2279,
882 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_OTHERS = 0x227A,
883
884 /* APB_BBRF bridge timeout (master) */
885 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_DMA = 0x2300,
886 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HCI = 0x2310,
887 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RLX4081 = 0x2320,
888 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IDDMA = 0x2330,
889 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HIOE = 0x2340,
890 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IPSEC = 0x2350,
891 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RX4281 = 0x2360,
892 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_OTHERS = 0x2370,
893 MAC_AX_ERR_L2_RESET_DONE = 0x2400,
894 MAC_AX_ERR_L2_ERR_WDT_TIMEOUT_INT = 0x2599,
895 MAC_AX_ERR_CPU_EXCEPTION = 0x3000,
896 MAC_AX_ERR_ASSERTION = 0x4000,
897 MAC_AX_ERR_RXI300 = 0x5000,
898 MAC_AX_GET_ERR_MAX,
899 MAC_AX_DUMP_SHAREBUFF_INDICATOR = 0x80000000,
900
901 /* set error info */
902 MAC_AX_ERR_L1_DISABLE_EN = 0x0001,
903 MAC_AX_ERR_L1_RCVY_EN = 0x0002,
904 MAC_AX_ERR_L1_RCVY_STOP_REQ = 0x0003,
905 MAC_AX_ERR_L1_RCVY_START_REQ = 0x0004,
906 MAC_AX_ERR_L1_RESET_START_DMAC = 0x000A,
907 MAC_AX_ERR_L0_CFG_NOTIFY = 0x0010,
908 MAC_AX_ERR_L0_CFG_DIS_NOTIFY = 0x0011,
909 MAC_AX_ERR_L0_CFG_HANDSHAKE = 0x0012,
910 MAC_AX_ERR_L0_RCVY_EN = 0x0013,
911 MAC_AX_SET_ERR_MAX,
912 };
913
914 struct rtw89_mac_size_set {
915 const struct rtw89_hfc_prec_cfg hfc_preccfg_pcie;
916 const struct rtw89_hfc_prec_cfg hfc_prec_cfg_c0;
917 const struct rtw89_hfc_prec_cfg hfc_prec_cfg_c2;
918 const struct rtw89_dle_size wde_size0;
919 const struct rtw89_dle_size wde_size0_v1;
920 const struct rtw89_dle_size wde_size4;
921 const struct rtw89_dle_size wde_size4_v1;
922 const struct rtw89_dle_size wde_size6;
923 const struct rtw89_dle_size wde_size7;
924 const struct rtw89_dle_size wde_size9;
925 const struct rtw89_dle_size wde_size18;
926 const struct rtw89_dle_size wde_size19;
927 const struct rtw89_dle_size wde_size23;
928 const struct rtw89_dle_size wde_size25;
929 const struct rtw89_dle_size ple_size0;
930 const struct rtw89_dle_size ple_size0_v1;
931 const struct rtw89_dle_size ple_size3_v1;
932 const struct rtw89_dle_size ple_size4;
933 const struct rtw89_dle_size ple_size6;
934 const struct rtw89_dle_size ple_size8;
935 const struct rtw89_dle_size ple_size9;
936 const struct rtw89_dle_size ple_size18;
937 const struct rtw89_dle_size ple_size19;
938 const struct rtw89_dle_size ple_size32;
939 const struct rtw89_dle_size ple_size33;
940 const struct rtw89_wde_quota wde_qt0;
941 const struct rtw89_wde_quota wde_qt0_v1;
942 const struct rtw89_wde_quota wde_qt4;
943 const struct rtw89_wde_quota wde_qt6;
944 const struct rtw89_wde_quota wde_qt7;
945 const struct rtw89_wde_quota wde_qt17;
946 const struct rtw89_wde_quota wde_qt18;
947 const struct rtw89_wde_quota wde_qt23;
948 const struct rtw89_wde_quota wde_qt25;
949 const struct rtw89_ple_quota ple_qt0;
950 const struct rtw89_ple_quota ple_qt1;
951 const struct rtw89_ple_quota ple_qt4;
952 const struct rtw89_ple_quota ple_qt5;
953 const struct rtw89_ple_quota ple_qt9;
954 const struct rtw89_ple_quota ple_qt13;
955 const struct rtw89_ple_quota ple_qt18;
956 const struct rtw89_ple_quota ple_qt44;
957 const struct rtw89_ple_quota ple_qt45;
958 const struct rtw89_ple_quota ple_qt46;
959 const struct rtw89_ple_quota ple_qt47;
960 const struct rtw89_ple_quota ple_qt57;
961 const struct rtw89_ple_quota ple_qt58;
962 const struct rtw89_ple_quota ple_qt59;
963 const struct rtw89_ple_quota ple_qt72;
964 const struct rtw89_ple_quota ple_qt73;
965 const struct rtw89_ple_quota ple_qt74;
966 const struct rtw89_ple_quota ple_qt75;
967 const struct rtw89_ple_quota ple_qt_52a_wow;
968 const struct rtw89_ple_quota ple_qt_52b_wow;
969 const struct rtw89_ple_quota ple_qt_52bt_wow;
970 const struct rtw89_ple_quota ple_qt_51b_wow;
971 const struct rtw89_rsvd_quota ple_rsvd_qt0;
972 const struct rtw89_rsvd_quota ple_rsvd_qt1;
973 const struct rtw89_dle_rsvd_size rsvd0_size0;
974 const struct rtw89_dle_rsvd_size rsvd1_size0;
975 };
976
977 extern const struct rtw89_mac_size_set rtw89_mac_size;
978
979 struct rtw89_mac_gen_def {
980 u32 band1_offset;
981 u32 filter_model_addr;
982 u32 indir_access_addr;
983 const u32 *mem_base_addrs;
984 u32 mem_page_size;
985 u32 rx_fltr;
986 const struct rtw89_port_reg *port_base;
987 u32 agg_len_ht;
988 u32 ps_status;
989
990 struct rtw89_reg_def muedca_ctrl;
991 struct rtw89_reg_def bfee_ctrl;
992 struct rtw89_reg_def narrow_bw_ru_dis;
993 struct rtw89_reg_def wow_ctrl;
994 struct rtw89_reg_def agg_limit;
995 struct rtw89_reg_def txcnt_limit;
996
997 int (*check_mac_en)(struct rtw89_dev *rtwdev, u8 band,
998 enum rtw89_mac_hwmod_sel sel);
999 int (*sys_init)(struct rtw89_dev *rtwdev);
1000 int (*trx_init)(struct rtw89_dev *rtwdev);
1001 void (*hci_func_en)(struct rtw89_dev *rtwdev);
1002 void (*dmac_func_pre_en)(struct rtw89_dev *rtwdev);
1003 void (*dle_func_en)(struct rtw89_dev *rtwdev, bool enable);
1004 void (*dle_clk_en)(struct rtw89_dev *rtwdev, bool enable);
1005 void (*bf_assoc)(struct rtw89_dev *rtwdev,
1006 struct rtw89_vif_link *rtwvif_link,
1007 struct rtw89_sta_link *rtwsta_link);
1008
1009 int (*typ_fltr_opt)(struct rtw89_dev *rtwdev,
1010 enum rtw89_machdr_frame_type type,
1011 enum rtw89_mac_fwd_target fwd_target,
1012 u8 mac_idx);
1013 int (*cfg_ppdu_status)(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable);
1014 void (*cfg_phy_rpt)(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable);
1015
1016 int (*dle_mix_cfg)(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg);
1017 int (*chk_dle_rdy)(struct rtw89_dev *rtwdev, bool wde_or_ple);
1018 int (*dle_buf_req)(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id);
1019 void (*hfc_func_en)(struct rtw89_dev *rtwdev, bool en, bool h2c_en);
1020 void (*hfc_h2c_cfg)(struct rtw89_dev *rtwdev);
1021 void (*hfc_mix_cfg)(struct rtw89_dev *rtwdev);
1022 void (*hfc_get_mix_info)(struct rtw89_dev *rtwdev);
1023 void (*wde_quota_cfg)(struct rtw89_dev *rtwdev,
1024 const struct rtw89_wde_quota *min_cfg,
1025 const struct rtw89_wde_quota *max_cfg,
1026 u16 ext_wde_min_qt_wcpu);
1027 void (*ple_quota_cfg)(struct rtw89_dev *rtwdev,
1028 const struct rtw89_ple_quota *min_cfg,
1029 const struct rtw89_ple_quota *max_cfg);
1030 int (*set_cpuio)(struct rtw89_dev *rtwdev,
1031 struct rtw89_cpuio_ctrl *ctrl_para, bool wd);
1032 int (*dle_quota_change)(struct rtw89_dev *rtwdev, bool band1_en);
1033
1034 void (*disable_cpu)(struct rtw89_dev *rtwdev);
1035 int (*fwdl_enable_wcpu)(struct rtw89_dev *rtwdev, u8 boot_reason,
1036 bool dlfw, bool include_bb);
1037 u8 (*fwdl_get_status)(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type);
1038 int (*fwdl_check_path_ready)(struct rtw89_dev *rtwdev, bool h2c_or_fwdl);
1039 void (*fwdl_secure_idmem_share_mode)(struct rtw89_dev *rtwdev, u8 mode);
1040 int (*parse_efuse_map)(struct rtw89_dev *rtwdev);
1041 int (*parse_phycap_map)(struct rtw89_dev *rtwdev);
1042 int (*cnv_efuse_state)(struct rtw89_dev *rtwdev, bool idle);
1043 int (*efuse_read_fw_secure)(struct rtw89_dev *rtwdev);
1044
1045 int (*cfg_plt)(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt);
1046 u16 (*get_plt_cnt)(struct rtw89_dev *rtwdev, u8 band);
1047
1048 bool (*get_txpwr_cr)(struct rtw89_dev *rtwdev,
1049 enum rtw89_phy_idx phy_idx,
1050 u32 reg_base, u32 *cr);
1051
1052 int (*write_xtal_si)(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask);
1053 int (*read_xtal_si)(struct rtw89_dev *rtwdev, u8 offset, u8 *val);
1054
1055 void (*dump_qta_lost)(struct rtw89_dev *rtwdev);
1056 void (*dump_err_status)(struct rtw89_dev *rtwdev,
1057 enum mac_ax_err_info err);
1058
1059 bool (*is_txq_empty)(struct rtw89_dev *rtwdev);
1060
1061 int (*prep_chan_list)(struct rtw89_dev *rtwdev,
1062 struct rtw89_vif_link *rtwvif_link);
1063 void (*free_chan_list)(struct rtw89_dev *rtwdev);
1064 int (*add_chan_list)(struct rtw89_dev *rtwdev,
1065 struct rtw89_vif_link *rtwvif_link);
1066 int (*add_chan_list_pno)(struct rtw89_dev *rtwdev,
1067 struct rtw89_vif_link *rtwvif_link);
1068 int (*scan_offload)(struct rtw89_dev *rtwdev,
1069 struct rtw89_scan_option *option,
1070 struct rtw89_vif_link *rtwvif_link,
1071 bool wowlan);
1072
1073 int (*wow_config_mac)(struct rtw89_dev *rtwdev, bool enable_wow);
1074 };
1075
1076 extern const struct rtw89_mac_gen_def rtw89_mac_gen_ax;
1077 extern const struct rtw89_mac_gen_def rtw89_mac_gen_be;
1078
1079 static inline
rtw89_mac_reg_by_idx(struct rtw89_dev * rtwdev,u32 reg_base,u8 band)1080 u32 rtw89_mac_reg_by_idx(struct rtw89_dev *rtwdev, u32 reg_base, u8 band)
1081 {
1082 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1083
1084 return band == 0 ? reg_base : (reg_base + mac->band1_offset);
1085 }
1086
1087 static inline
rtw89_mac_reg_by_port(struct rtw89_dev * rtwdev,u32 base,u8 port,u8 mac_idx)1088 u32 rtw89_mac_reg_by_port(struct rtw89_dev *rtwdev, u32 base, u8 port, u8 mac_idx)
1089 {
1090 return rtw89_mac_reg_by_idx(rtwdev, base + port * 0x40, mac_idx);
1091 }
1092
1093 static inline u32
rtw89_read32_port(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,u32 base)1094 rtw89_read32_port(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, u32 base)
1095 {
1096 u32 reg;
1097
1098 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port,
1099 rtwvif_link->mac_idx);
1100 return rtw89_read32(rtwdev, reg);
1101 }
1102
1103 static inline u32
rtw89_read32_port_mask(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,u32 base,u32 mask)1104 rtw89_read32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
1105 u32 base, u32 mask)
1106 {
1107 u32 reg;
1108
1109 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port,
1110 rtwvif_link->mac_idx);
1111 return rtw89_read32_mask(rtwdev, reg, mask);
1112 }
1113
1114 static inline void
rtw89_write32_port(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,u32 base,u32 data)1115 rtw89_write32_port(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, u32 base,
1116 u32 data)
1117 {
1118 u32 reg;
1119
1120 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port,
1121 rtwvif_link->mac_idx);
1122 rtw89_write32(rtwdev, reg, data);
1123 }
1124
1125 static inline void
rtw89_write32_port_mask(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,u32 base,u32 mask,u32 data)1126 rtw89_write32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
1127 u32 base, u32 mask, u32 data)
1128 {
1129 u32 reg;
1130
1131 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port,
1132 rtwvif_link->mac_idx);
1133 rtw89_write32_mask(rtwdev, reg, mask, data);
1134 }
1135
1136 static inline void
rtw89_write16_port_mask(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,u32 base,u32 mask,u16 data)1137 rtw89_write16_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
1138 u32 base, u32 mask, u16 data)
1139 {
1140 u32 reg;
1141
1142 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port,
1143 rtwvif_link->mac_idx);
1144 rtw89_write16_mask(rtwdev, reg, mask, data);
1145 }
1146
1147 static inline void
rtw89_write32_port_clr(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,u32 base,u32 bit)1148 rtw89_write32_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
1149 u32 base, u32 bit)
1150 {
1151 u32 reg;
1152
1153 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port,
1154 rtwvif_link->mac_idx);
1155 rtw89_write32_clr(rtwdev, reg, bit);
1156 }
1157
1158 static inline void
rtw89_write16_port_clr(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,u32 base,u16 bit)1159 rtw89_write16_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
1160 u32 base, u16 bit)
1161 {
1162 u32 reg;
1163
1164 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port,
1165 rtwvif_link->mac_idx);
1166 rtw89_write16_clr(rtwdev, reg, bit);
1167 }
1168
1169 static inline void
rtw89_write32_port_set(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,u32 base,u32 bit)1170 rtw89_write32_port_set(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
1171 u32 base, u32 bit)
1172 {
1173 u32 reg;
1174
1175 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port,
1176 rtwvif_link->mac_idx);
1177 rtw89_write32_set(rtwdev, reg, bit);
1178 }
1179
1180 int rtw89_mac_pwr_on(struct rtw89_dev *rtwdev);
1181 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev);
1182 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev, bool include_bb);
1183 int rtw89_mac_init(struct rtw89_dev *rtwdev);
1184 int rtw89_mac_dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode,
1185 enum rtw89_qta_mode ext_mode);
1186 int rtw89_mac_hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en);
1187 int rtw89_mac_preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx,
1188 enum rtw89_qta_mode mode);
1189 bool rtw89_mac_is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode);
1190 static inline
rtw89_mac_check_mac_en(struct rtw89_dev * rtwdev,u8 band,enum rtw89_mac_hwmod_sel sel)1191 int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 band,
1192 enum rtw89_mac_hwmod_sel sel)
1193 {
1194 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1195
1196 return mac->check_mac_en(rtwdev, band, sel);
1197 }
1198
1199 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val);
1200 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val);
1201 int rtw89_mac_dle_dfi_cfg(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl);
1202 int rtw89_mac_dle_dfi_quota_cfg(struct rtw89_dev *rtwdev,
1203 struct rtw89_mac_dle_dfi_quota *quota);
1204 void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev);
1205 int rtw89_mac_dle_dfi_qempty_cfg(struct rtw89_dev *rtwdev,
1206 struct rtw89_mac_dle_dfi_qempty *qempty);
1207 void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev,
1208 enum mac_ax_err_info err);
1209 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif_link *vif);
1210 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link);
1211 void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev,
1212 struct rtw89_vif_link *rtwvif_link,
1213 struct rtw89_vif_link *rtwvif_src,
1214 u16 offset_tu);
1215 int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
1216 u64 *tsf);
1217 void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev,
1218 struct rtw89_vif_link *rtwvif_link, bool en);
1219 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev,
1220 struct rtw89_vif_link *rtwvif_link);
1221 void rtw89_mac_set_he_tb(struct rtw89_dev *rtwdev,
1222 struct rtw89_vif_link *rtwvif_link);
1223 void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link);
1224 void rtw89_mac_enable_beacon_for_ap_vifs(struct rtw89_dev *rtwdev, bool en);
1225 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif_link *vif);
1226 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev);
1227 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev);
1228
rtw89_chip_enable_bb_rf(struct rtw89_dev * rtwdev)1229 static inline int rtw89_chip_enable_bb_rf(struct rtw89_dev *rtwdev)
1230 {
1231 const struct rtw89_chip_info *chip = rtwdev->chip;
1232
1233 return chip->ops->enable_bb_rf(rtwdev);
1234 }
1235
rtw89_chip_disable_bb_rf(struct rtw89_dev * rtwdev)1236 static inline int rtw89_chip_disable_bb_rf(struct rtw89_dev *rtwdev)
1237 {
1238 const struct rtw89_chip_info *chip = rtwdev->chip;
1239
1240 return chip->ops->disable_bb_rf(rtwdev);
1241 }
1242
rtw89_chip_reset_bb_rf(struct rtw89_dev * rtwdev)1243 static inline int rtw89_chip_reset_bb_rf(struct rtw89_dev *rtwdev)
1244 {
1245 int ret;
1246
1247 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX)
1248 return 0;
1249
1250 ret = rtw89_chip_disable_bb_rf(rtwdev);
1251 if (ret)
1252 return ret;
1253 ret = rtw89_chip_enable_bb_rf(rtwdev);
1254 if (ret)
1255 return ret;
1256
1257 return 0;
1258 }
1259
1260 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev);
1261 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err);
1262 bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, struct sk_buff *c2h,
1263 u8 class, u8 func);
1264 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
1265 u32 len, u8 class, u8 func);
1266 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev);
1267 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx,
1268 u32 *tx_en, enum rtw89_sch_tx_sel sel);
1269 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx,
1270 u32 *tx_en, enum rtw89_sch_tx_sel sel);
1271 int rtw89_mac_stop_sch_tx_v2(struct rtw89_dev *rtwdev, u8 mac_idx,
1272 u32 *tx_en, enum rtw89_sch_tx_sel sel);
1273 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
1274 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
1275 int rtw89_mac_resume_sch_tx_v2(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
1276 void rtw89_mac_cfg_phy_rpt_be(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable);
1277
1278 static inline
rtw89_mac_cfg_phy_rpt(struct rtw89_dev * rtwdev,u8 mac_idx,bool enable)1279 void rtw89_mac_cfg_phy_rpt(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable)
1280 {
1281 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1282
1283 if (mac->cfg_phy_rpt)
1284 mac->cfg_phy_rpt(rtwdev, mac_idx, enable);
1285 }
1286
1287 static inline
rtw89_mac_cfg_phy_rpt_bands(struct rtw89_dev * rtwdev,bool enable)1288 void rtw89_mac_cfg_phy_rpt_bands(struct rtw89_dev *rtwdev, bool enable)
1289 {
1290 rtw89_mac_cfg_phy_rpt(rtwdev, RTW89_MAC_0, enable);
1291
1292 if (!rtwdev->dbcc_en)
1293 return;
1294
1295 rtw89_mac_cfg_phy_rpt(rtwdev, RTW89_MAC_1, enable);
1296 }
1297
1298 static inline
rtw89_mac_cfg_ppdu_status(struct rtw89_dev * rtwdev,u8 mac_idx,bool enable)1299 int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable)
1300 {
1301 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1302
1303 return mac->cfg_ppdu_status(rtwdev, mac_idx, enable);
1304 }
1305
1306 static inline
rtw89_mac_cfg_ppdu_status_bands(struct rtw89_dev * rtwdev,bool enable)1307 int rtw89_mac_cfg_ppdu_status_bands(struct rtw89_dev *rtwdev, bool enable)
1308 {
1309 int ret;
1310
1311 ret = rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, enable);
1312 if (ret)
1313 return ret;
1314
1315 if (!rtwdev->dbcc_en)
1316 return 0;
1317
1318 return rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_1, enable);
1319 }
1320
1321 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev);
1322 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop);
1323 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex);
1324 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev,
1325 const struct rtw89_mac_ax_coex *coex);
1326 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev,
1327 const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
1328 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev,
1329 const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
1330 int rtw89_mac_cfg_gnt_v2(struct rtw89_dev *rtwdev,
1331 const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
1332
1333 static inline
rtw89_mac_cfg_plt(struct rtw89_dev * rtwdev,struct rtw89_mac_ax_plt * plt)1334 int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt)
1335 {
1336 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1337
1338 return mac->cfg_plt(rtwdev, plt);
1339 }
1340
1341 static inline
rtw89_mac_get_plt_cnt(struct rtw89_dev * rtwdev,u8 band)1342 u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band)
1343 {
1344 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1345
1346 return mac->get_plt_cnt(rtwdev, band);
1347 }
1348
1349 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val);
1350 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev);
1351 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev);
1352 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl);
1353 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl);
1354 int rtw89_mac_cfg_ctrl_path_v2(struct rtw89_dev *rtwdev, bool wl);
1355 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter);
1356 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev);
1357
1358 static inline
rtw89_mac_bf_assoc(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)1359 void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev,
1360 struct rtw89_vif_link *rtwvif_link,
1361 struct rtw89_sta_link *rtwsta_link)
1362 {
1363 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1364
1365 if (mac->bf_assoc)
1366 mac->bf_assoc(rtwdev, rtwvif_link, rtwsta_link);
1367 }
1368
1369 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev,
1370 struct rtw89_vif_link *rtwvif_link,
1371 struct rtw89_sta_link *rtwsta_link);
1372 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
1373 struct ieee80211_bss_conf *conf);
1374 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev,
1375 struct rtw89_sta_link *rtwsta_link,
1376 bool disconnect);
1377 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev);
1378 void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en);
1379 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link);
1380 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link);
1381 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev,
1382 struct rtw89_vif_link *rtwvif_link, bool en);
1383 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause);
1384
rtw89_mac_bf_monitor_track(struct rtw89_dev * rtwdev)1385 static inline void rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev)
1386 {
1387 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX)
1388 return;
1389
1390 if (!test_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags))
1391 return;
1392
1393 _rtw89_mac_bf_monitor_track(rtwdev);
1394 }
1395
rtw89_mac_txpwr_read32(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u32 reg_base,u32 * val)1396 static inline int rtw89_mac_txpwr_read32(struct rtw89_dev *rtwdev,
1397 enum rtw89_phy_idx phy_idx,
1398 u32 reg_base, u32 *val)
1399 {
1400 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1401 u32 cr;
1402
1403 if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))
1404 return -EINVAL;
1405
1406 *val = rtw89_read32(rtwdev, cr);
1407 return 0;
1408 }
1409
rtw89_mac_txpwr_write32(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u32 reg_base,u32 val)1410 static inline int rtw89_mac_txpwr_write32(struct rtw89_dev *rtwdev,
1411 enum rtw89_phy_idx phy_idx,
1412 u32 reg_base, u32 val)
1413 {
1414 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1415 u32 cr;
1416
1417 if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))
1418 return -EINVAL;
1419
1420 rtw89_write32(rtwdev, cr, val);
1421 return 0;
1422 }
1423
rtw89_mac_txpwr_write32_mask(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u32 reg_base,u32 mask,u32 val)1424 static inline int rtw89_mac_txpwr_write32_mask(struct rtw89_dev *rtwdev,
1425 enum rtw89_phy_idx phy_idx,
1426 u32 reg_base, u32 mask, u32 val)
1427 {
1428 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1429 u32 cr;
1430
1431 if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))
1432 return -EINVAL;
1433
1434 rtw89_write32_mask(rtwdev, cr, mask, val);
1435 return 0;
1436 }
1437
rtw89_mac_ctrl_hci_dma_tx(struct rtw89_dev * rtwdev,bool enable)1438 static inline void rtw89_mac_ctrl_hci_dma_tx(struct rtw89_dev *rtwdev,
1439 bool enable)
1440 {
1441 const struct rtw89_chip_info *chip = rtwdev->chip;
1442
1443 if (enable)
1444 rtw89_write32_set(rtwdev, chip->hci_func_en_addr,
1445 B_AX_HCI_TXDMA_EN);
1446 else
1447 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr,
1448 B_AX_HCI_TXDMA_EN);
1449 }
1450
rtw89_mac_ctrl_hci_dma_rx(struct rtw89_dev * rtwdev,bool enable)1451 static inline void rtw89_mac_ctrl_hci_dma_rx(struct rtw89_dev *rtwdev,
1452 bool enable)
1453 {
1454 const struct rtw89_chip_info *chip = rtwdev->chip;
1455
1456 if (enable)
1457 rtw89_write32_set(rtwdev, chip->hci_func_en_addr,
1458 B_AX_HCI_RXDMA_EN);
1459 else
1460 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr,
1461 B_AX_HCI_RXDMA_EN);
1462 }
1463
rtw89_mac_ctrl_hci_dma_trx(struct rtw89_dev * rtwdev,bool enable)1464 static inline void rtw89_mac_ctrl_hci_dma_trx(struct rtw89_dev *rtwdev,
1465 bool enable)
1466 {
1467 const struct rtw89_chip_info *chip = rtwdev->chip;
1468
1469 if (enable)
1470 rtw89_write32_set(rtwdev, chip->hci_func_en_addr,
1471 B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN);
1472 else
1473 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr,
1474 B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN);
1475 }
1476
rtw89_mac_get_power_state(struct rtw89_dev * rtwdev)1477 static inline bool rtw89_mac_get_power_state(struct rtw89_dev *rtwdev)
1478 {
1479 u32 val;
1480
1481 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE,
1482 B_AX_WLMAC_PWR_STE_MASK);
1483
1484 return !!val;
1485 }
1486
1487 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link,
1488 bool resume, u32 tx_time);
1489 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link,
1490 u32 *tx_time);
1491 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev,
1492 struct rtw89_sta_link *rtwsta_link,
1493 bool resume, u8 tx_retry);
1494 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev,
1495 struct rtw89_sta_link *rtwsta_link, u8 *tx_retry);
1496
1497 enum rtw89_mac_xtal_si_offset {
1498 XTAL0 = 0x0,
1499 XTAL3 = 0x3,
1500 XTAL_SI_XTAL_SC_XI = 0x04,
1501 #define XTAL_SC_XI_MASK GENMASK(7, 0)
1502 XTAL_SI_XTAL_SC_XO = 0x05,
1503 #define XTAL_SC_XO_MASK GENMASK(7, 0)
1504 XTAL_SI_XREF_MODE = 0x0B,
1505 XTAL_SI_PWR_CUT = 0x10,
1506 #define XTAL_SI_SMALL_PWR_CUT BIT(0)
1507 #define XTAL_SI_BIG_PWR_CUT BIT(1)
1508 XTAL_SI_XTAL_DRV = 0x15,
1509 #define XTAL_SI_DRV_LATCH BIT(4)
1510 XTAL_SI_XTAL_PLL = 0x16,
1511 XTAL_SI_XTAL_XMD_2 = 0x24,
1512 #define XTAL_SI_LDO_LPS GENMASK(6, 4)
1513 XTAL_SI_XTAL_XMD_4 = 0x26,
1514 #define XTAL_SI_LPS_CAP GENMASK(3, 0)
1515 XTAL_SI_XREF_RF1 = 0x2D,
1516 XTAL_SI_XREF_RF2 = 0x2E,
1517 XTAL_SI_CV = 0x41,
1518 #define XTAL_SI_ACV_MASK GENMASK(3, 0)
1519 XTAL_SI_LOW_ADDR = 0x62,
1520 #define XTAL_SI_LOW_ADDR_MASK GENMASK(7, 0)
1521 XTAL_SI_CTRL = 0x63,
1522 #define XTAL_SI_MODE_SEL_MASK GENMASK(7, 6)
1523 #define XTAL_SI_RDY BIT(5)
1524 #define XTAL_SI_HIGH_ADDR_MASK GENMASK(2, 0)
1525 XTAL_SI_READ_VAL = 0x7A,
1526 XTAL_SI_WL_RFC_S0 = 0x80,
1527 #define XTAL_SI_RF00S_EN GENMASK(2, 0)
1528 #define XTAL_SI_RF00 BIT(0)
1529 XTAL_SI_WL_RFC_S1 = 0x81,
1530 #define XTAL_SI_RF10S_EN GENMASK(2, 0)
1531 #define XTAL_SI_RF10 BIT(0)
1532 XTAL_SI_ANAPAR_WL = 0x90,
1533 #define XTAL_SI_SRAM2RFC BIT(7)
1534 #define XTAL_SI_GND_SHDN_WL BIT(6)
1535 #define XTAL_SI_SHDN_WL BIT(5)
1536 #define XTAL_SI_RFC2RF BIT(4)
1537 #define XTAL_SI_OFF_EI BIT(3)
1538 #define XTAL_SI_OFF_WEI BIT(2)
1539 #define XTAL_SI_PON_EI BIT(1)
1540 #define XTAL_SI_PON_WEI BIT(0)
1541 XTAL_SI_SRAM_CTRL = 0xA1,
1542 #define XTAL_SI_SRAM_DIS BIT(1)
1543 #define FULL_BIT_MASK GENMASK(7, 0)
1544 XTAL_SI_APBT = 0xD1,
1545 XTAL_SI_PLL = 0xE0,
1546 XTAL_SI_PLL_1 = 0xE1,
1547 };
1548
1549 static inline
rtw89_mac_write_xtal_si(struct rtw89_dev * rtwdev,u8 offset,u8 val,u8 mask)1550 int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask)
1551 {
1552 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1553
1554 return mac->write_xtal_si(rtwdev, offset, val, mask);
1555 }
1556
1557 static inline
rtw89_mac_read_xtal_si(struct rtw89_dev * rtwdev,u8 offset,u8 * val)1558 int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val)
1559 {
1560 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1561
1562 return mac->read_xtal_si(rtwdev, offset, val);
1563 }
1564
1565 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
1566 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow);
1567 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev,
1568 enum rtw89_mac_idx band);
1569 void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool wow);
1570 int rtw89_mac_dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode,
1571 bool band1_en);
1572 int rtw89_mac_get_dle_rsvd_qt_cfg(struct rtw89_dev *rtwdev,
1573 enum rtw89_mac_dle_rsvd_qt_type type,
1574 struct rtw89_mac_dle_rsvd_qt_cfg *cfg);
1575 int rtw89_mac_cpu_io_rx(struct rtw89_dev *rtwdev, bool wow_enable);
1576
1577 static inline
rtw89_fwdl_secure_idmem_share_mode(struct rtw89_dev * rtwdev,u8 mode)1578 void rtw89_fwdl_secure_idmem_share_mode(struct rtw89_dev *rtwdev, u8 mode)
1579 {
1580 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1581
1582 if (!mac->fwdl_secure_idmem_share_mode)
1583 return;
1584
1585 return mac->fwdl_secure_idmem_share_mode(rtwdev, mode);
1586 }
1587
1588 static inline
rtw89_mac_scan_offload(struct rtw89_dev * rtwdev,struct rtw89_scan_option * option,struct rtw89_vif_link * rtwvif_link,bool wowlan)1589 int rtw89_mac_scan_offload(struct rtw89_dev *rtwdev,
1590 struct rtw89_scan_option *option,
1591 struct rtw89_vif_link *rtwvif_link,
1592 bool wowlan)
1593 {
1594 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1595 int ret;
1596
1597 ret = mac->scan_offload(rtwdev, option, rtwvif_link, wowlan);
1598
1599 if (option->enable) {
1600 /*
1601 * At this point, new scan request is acknowledged by firmware,
1602 * so scan events of previous scan request become obsoleted.
1603 * Purge the queued scan events to prevent interference to
1604 * current new request.
1605 */
1606 rtw89_fw_c2h_purge_obsoleted_scan_events(rtwdev);
1607 }
1608
1609 return ret;
1610 }
1611 #endif
1612