1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2024 Nuvoton Technology Corp.
4 *
5 * Author: Shan-Chun Hung <schung@nuvoton.com>
6 * * Jacky Huang <ychuang3@nuvoton.com>
7 */
8
9 #include <linux/bitfield.h>
10 #include <linux/bitops.h>
11 #include <linux/cleanup.h>
12 #include <linux/clk.h>
13 #include <linux/gpio/driver.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/of.h>
16 #include <linux/platform_device.h>
17 #include <linux/property.h>
18 #include <linux/regmap.h>
19
20 #include <linux/pinctrl/pinconf.h>
21 #include <linux/pinctrl/pinctrl.h>
22 #include "../core.h"
23 #include "../pinconf.h"
24 #include "pinctrl-ma35.h"
25
26 #define MA35_MFP_REG_BASE 0x80
27 #define MA35_MFP_REG_SZ_PER_BANK 8
28 #define MA35_MFP_BITS_PER_PORT 4
29
30 #define MA35_GPIO_BANK_MAX 14
31 #define MA35_GPIO_PORT_MAX 16
32
33 /* GPIO control registers */
34 #define MA35_GP_REG_MODE 0x00
35 #define MA35_GP_REG_DINOFF 0x04
36 #define MA35_GP_REG_DOUT 0x08
37 #define MA35_GP_REG_DATMSK 0x0c
38 #define MA35_GP_REG_PIN 0x10
39 #define MA35_GP_REG_DBEN 0x14
40 #define MA35_GP_REG_INTTYPE 0x18
41 #define MA35_GP_REG_INTEN 0x1c
42 #define MA35_GP_REG_INTSRC 0x20
43 #define MA35_GP_REG_SMTEN 0x24
44 #define MA35_GP_REG_SLEWCTL 0x28
45 #define MA35_GP_REG_SPW 0x2c
46 #define MA35_GP_REG_PUSEL 0x30
47 #define MA35_GP_REG_DSL 0x38
48 #define MA35_GP_REG_DSH 0x3c
49
50 /* GPIO mode control */
51 #define MA35_GP_MODE_INPUT 0x0
52 #define MA35_GP_MODE_OUTPUT 0x1
53 #define MA35_GP_MODE_OPEN_DRAIN 0x2
54 #define MA35_GP_MODE_QUASI 0x3
55 #define MA35_GP_MODE_MASK(n) GENMASK(n * 2 + 1, n * 2)
56
57 #define MA35_GP_SLEWCTL_MASK(n) GENMASK(n * 2 + 1, n * 2)
58
59 /* GPIO pull-up and pull-down selection control */
60 #define MA35_GP_PUSEL_DISABLE 0x0
61 #define MA35_GP_PUSEL_PULL_UP 0x1
62 #define MA35_GP_PUSEL_PULL_DOWN 0x2
63 #define MA35_GP_PUSEL_MASK(n) GENMASK(n * 2 + 1, n * 2)
64
65 /*
66 * The MA35_GP_REG_INTEN bits 0 ~ 15 control low-level or falling edge trigger,
67 * while bits 16 ~ 31 control high-level or rising edge trigger.
68 */
69 #define MA35_GP_INTEN_L(n) BIT(n)
70 #define MA35_GP_INTEN_H(n) BIT(n + 16)
71 #define MA35_GP_INTEN_BOTH(n) (MA35_GP_INTEN_H(n) | MA35_GP_INTEN_L(n))
72
73 /*
74 * The MA35_GP_REG_DSL register controls ports 0 to 7, while the MA35_GP_REG_DSH
75 * register controls ports 8 to 15. Each port occupies a width of 4 bits, with 3
76 * bits being effective.
77 */
78 #define MA35_GP_DS_REG(n) (n < 8 ? MA35_GP_REG_DSL : MA35_GP_REG_DSH)
79 #define MA35_GP_DS_MASK(n) GENMASK((n % 8) * 4 + 3, (n % 8) * 4)
80
81 #define MVOLT_1800 0
82 #define MVOLT_3300 1
83
84 /* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */
85 #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
86 #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask))
87
88 static const char * const gpio_group_name[] = {
89 "gpioa", "gpiob", "gpioc", "gpiod", "gpioe", "gpiof", "gpiog",
90 "gpioh", "gpioi", "gpioj", "gpiok", "gpiol", "gpiom", "gpion",
91 };
92
93 static const u32 ds_1800mv_tbl[] = {
94 2900, 4400, 5800, 7300, 8600, 10100, 11500, 13000,
95 };
96
97 static const u32 ds_3300mv_tbl[] = {
98 17100, 25600, 34100, 42800, 48000, 56000, 77000, 82000,
99 };
100
101 struct ma35_pin_setting {
102 u32 offset;
103 u32 shift;
104 u32 muxval;
105 unsigned long *configs;
106 unsigned int nconfigs;
107 };
108
109 struct ma35_pin_bank {
110 void __iomem *reg_base;
111 struct clk *clk;
112 int irq;
113 u8 bank_num;
114 u8 nr_pins;
115 bool valid;
116 const char *name;
117 struct fwnode_handle *fwnode;
118 struct gpio_chip chip;
119 u32 irqtype;
120 u32 irqinten;
121 struct regmap *regmap;
122 struct device *dev;
123 };
124
125 struct ma35_pin_ctrl {
126 struct ma35_pin_bank *pin_banks;
127 u32 nr_banks;
128 u32 nr_pins;
129 };
130
131 struct ma35_pinctrl {
132 struct device *dev;
133 struct ma35_pin_ctrl *ctrl;
134 struct pinctrl_dev *pctl;
135 const struct ma35_pinctrl_soc_info *info;
136 struct regmap *regmap;
137 struct group_desc *groups;
138 unsigned int ngroups;
139 struct pinfunction *functions;
140 unsigned int nfunctions;
141 };
142
143 static DEFINE_RAW_SPINLOCK(ma35_lock);
144
ma35_get_groups_count(struct pinctrl_dev * pctldev)145 static int ma35_get_groups_count(struct pinctrl_dev *pctldev)
146 {
147 struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
148
149 return npctl->ngroups;
150 }
151
ma35_get_group_name(struct pinctrl_dev * pctldev,unsigned int selector)152 static const char *ma35_get_group_name(struct pinctrl_dev *pctldev, unsigned int selector)
153 {
154 struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
155
156 return npctl->groups[selector].grp.name;
157 }
158
ma35_get_group_pins(struct pinctrl_dev * pctldev,unsigned int selector,const unsigned int ** pins,unsigned int * npins)159 static int ma35_get_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
160 const unsigned int **pins, unsigned int *npins)
161 {
162 struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
163
164 if (selector >= npctl->ngroups)
165 return -EINVAL;
166
167 *pins = npctl->groups[selector].grp.pins;
168 *npins = npctl->groups[selector].grp.npins;
169
170 return 0;
171 }
172
173 static struct group_desc *
ma35_pinctrl_find_group_by_name(const struct ma35_pinctrl * npctl,const char * name)174 ma35_pinctrl_find_group_by_name(const struct ma35_pinctrl *npctl, const char *name)
175 {
176 int i;
177
178 for (i = 0; i < npctl->ngroups; i++) {
179 if (!strcmp(npctl->groups[i].grp.name, name))
180 return &npctl->groups[i];
181 }
182 return NULL;
183 }
184
ma35_pinctrl_dt_node_to_map_func(struct pinctrl_dev * pctldev,struct device_node * np,struct pinctrl_map ** map,unsigned int * num_maps)185 static int ma35_pinctrl_dt_node_to_map_func(struct pinctrl_dev *pctldev,
186 struct device_node *np,
187 struct pinctrl_map **map,
188 unsigned int *num_maps)
189 {
190 struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
191 struct ma35_pin_setting *setting;
192 struct pinctrl_map *new_map;
193 struct device_node *parent;
194 struct group_desc *grp;
195 int map_num = 1;
196 int i;
197
198 /*
199 * first find the group of this node and check if we need create
200 * config maps for pins
201 */
202 grp = ma35_pinctrl_find_group_by_name(npctl, np->name);
203 if (!grp) {
204 dev_err(npctl->dev, "unable to find group for node %s\n", np->name);
205 return -EINVAL;
206 }
207
208 map_num += grp->grp.npins;
209 new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL);
210 if (!new_map)
211 return -ENOMEM;
212
213 *map = new_map;
214 *num_maps = map_num;
215 /* create mux map */
216 parent = of_get_parent(np);
217 if (!parent)
218 return -EINVAL;
219
220 setting = grp->data;
221
222 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
223 new_map[0].data.mux.function = parent->name;
224 new_map[0].data.mux.group = np->name;
225 of_node_put(parent);
226
227 new_map++;
228 for (i = 0; i < grp->grp.npins; i++) {
229 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
230 new_map[i].data.configs.group_or_pin = pin_get_name(pctldev, grp->grp.pins[i]);
231 new_map[i].data.configs.configs = setting[i].configs;
232 new_map[i].data.configs.num_configs = setting[i].nconfigs;
233 }
234 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
235 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
236
237 return 0;
238 }
239
240 static const struct pinctrl_ops ma35_pctrl_ops = {
241 .get_groups_count = ma35_get_groups_count,
242 .get_group_name = ma35_get_group_name,
243 .get_group_pins = ma35_get_group_pins,
244 .dt_node_to_map = ma35_pinctrl_dt_node_to_map_func,
245 .dt_free_map = pinconf_generic_dt_free_map,
246 };
247
ma35_pinmux_get_func_count(struct pinctrl_dev * pctldev)248 static int ma35_pinmux_get_func_count(struct pinctrl_dev *pctldev)
249 {
250 struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
251
252 return npctl->nfunctions;
253 }
254
ma35_pinmux_get_func_name(struct pinctrl_dev * pctldev,unsigned int selector)255 static const char *ma35_pinmux_get_func_name(struct pinctrl_dev *pctldev,
256 unsigned int selector)
257 {
258 struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
259
260 return npctl->functions[selector].name;
261 }
262
ma35_pinmux_get_func_groups(struct pinctrl_dev * pctldev,unsigned int function,const char * const ** groups,unsigned int * const num_groups)263 static int ma35_pinmux_get_func_groups(struct pinctrl_dev *pctldev,
264 unsigned int function,
265 const char *const **groups,
266 unsigned int *const num_groups)
267 {
268 struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
269
270 *groups = npctl->functions[function].groups;
271 *num_groups = npctl->functions[function].ngroups;
272
273 return 0;
274 }
275
ma35_pinmux_set_mux(struct pinctrl_dev * pctldev,unsigned int selector,unsigned int group)276 static int ma35_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
277 unsigned int group)
278 {
279 struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
280 struct group_desc *grp = &npctl->groups[group];
281 struct ma35_pin_setting *setting = grp->data;
282 u32 i, regval;
283
284 dev_dbg(npctl->dev, "enable function %s group %s\n",
285 npctl->functions[selector].name, grp->grp.name);
286
287 for (i = 0; i < grp->grp.npins; i++) {
288 regmap_read(npctl->regmap, setting->offset, ®val);
289 regval &= ~GENMASK(setting->shift + MA35_MFP_BITS_PER_PORT - 1,
290 setting->shift);
291 regval |= setting->muxval << setting->shift;
292 regmap_write(npctl->regmap, setting->offset, regval);
293 setting++;
294 }
295 return 0;
296 }
297
298 static const struct pinmux_ops ma35_pmx_ops = {
299 .get_functions_count = ma35_pinmux_get_func_count,
300 .get_function_name = ma35_pinmux_get_func_name,
301 .get_function_groups = ma35_pinmux_get_func_groups,
302 .set_mux = ma35_pinmux_set_mux,
303 .strict = true,
304 };
305
ma35_gpio_set_mode(void __iomem * reg_mode,unsigned int gpio,u32 mode)306 static void ma35_gpio_set_mode(void __iomem *reg_mode, unsigned int gpio, u32 mode)
307 {
308 u32 regval = readl(reg_mode);
309
310 regval &= ~MA35_GP_MODE_MASK(gpio);
311 regval |= field_prep(MA35_GP_MODE_MASK(gpio), mode);
312
313 writel(regval, reg_mode);
314 }
315
ma35_gpio_get_mode(void __iomem * reg_mode,unsigned int gpio)316 static u32 ma35_gpio_get_mode(void __iomem *reg_mode, unsigned int gpio)
317 {
318 u32 regval = readl(reg_mode);
319
320 return field_get(MA35_GP_MODE_MASK(gpio), regval);
321 }
322
ma35_gpio_core_direction_in(struct gpio_chip * gc,unsigned int gpio)323 static int ma35_gpio_core_direction_in(struct gpio_chip *gc, unsigned int gpio)
324 {
325 struct ma35_pin_bank *bank = gpiochip_get_data(gc);
326 void __iomem *reg_mode = bank->reg_base + MA35_GP_REG_MODE;
327
328 guard(raw_spinlock_irqsave)(&ma35_lock);
329
330 ma35_gpio_set_mode(reg_mode, gpio, MA35_GP_MODE_INPUT);
331
332 return 0;
333 }
334
ma35_gpio_core_direction_out(struct gpio_chip * gc,unsigned int gpio,int val)335 static int ma35_gpio_core_direction_out(struct gpio_chip *gc, unsigned int gpio, int val)
336 {
337 struct ma35_pin_bank *bank = gpiochip_get_data(gc);
338 void __iomem *reg_dout = bank->reg_base + MA35_GP_REG_DOUT;
339 void __iomem *reg_mode = bank->reg_base + MA35_GP_REG_MODE;
340 unsigned int regval;
341
342 guard(raw_spinlock_irqsave)(&ma35_lock);
343
344 regval = readl(reg_dout);
345 if (val)
346 regval |= BIT(gpio);
347 else
348 regval &= ~BIT(gpio);
349 writel(regval, reg_dout);
350
351 ma35_gpio_set_mode(reg_mode, gpio, MA35_GP_MODE_OUTPUT);
352
353 return 0;
354 }
355
ma35_gpio_core_get(struct gpio_chip * gc,unsigned int gpio)356 static int ma35_gpio_core_get(struct gpio_chip *gc, unsigned int gpio)
357 {
358 struct ma35_pin_bank *bank = gpiochip_get_data(gc);
359 void __iomem *reg_pin = bank->reg_base + MA35_GP_REG_PIN;
360
361 return !!(readl(reg_pin) & BIT(gpio));
362 }
363
ma35_gpio_core_set(struct gpio_chip * gc,unsigned int gpio,int val)364 static void ma35_gpio_core_set(struct gpio_chip *gc, unsigned int gpio, int val)
365 {
366 struct ma35_pin_bank *bank = gpiochip_get_data(gc);
367 void __iomem *reg_dout = bank->reg_base + MA35_GP_REG_DOUT;
368 u32 regval;
369
370 if (val)
371 regval = readl(reg_dout) | BIT(gpio);
372 else
373 regval = readl(reg_dout) & ~BIT(gpio);
374
375 writel(regval, reg_dout);
376 }
377
ma35_gpio_core_to_request(struct gpio_chip * gc,unsigned int gpio)378 static int ma35_gpio_core_to_request(struct gpio_chip *gc, unsigned int gpio)
379 {
380 struct ma35_pin_bank *bank = gpiochip_get_data(gc);
381 u32 reg_offs, bit_offs, regval;
382
383 if (gpio < 8) {
384 /* The MFP low register controls port 0 ~ 7 */
385 reg_offs = bank->bank_num * MA35_MFP_REG_SZ_PER_BANK;
386 bit_offs = gpio * MA35_MFP_BITS_PER_PORT;
387 } else {
388 /* The MFP high register controls port 8 ~ 15 */
389 reg_offs = bank->bank_num * MA35_MFP_REG_SZ_PER_BANK + 4;
390 bit_offs = (gpio - 8) * MA35_MFP_BITS_PER_PORT;
391 }
392
393 regmap_read(bank->regmap, MA35_MFP_REG_BASE + reg_offs, ®val);
394 regval &= ~GENMASK(bit_offs + MA35_MFP_BITS_PER_PORT - 1, bit_offs);
395 regmap_write(bank->regmap, MA35_MFP_REG_BASE + reg_offs, regval);
396
397 return 0;
398 }
399
ma35_irq_gpio_ack(struct irq_data * d)400 static void ma35_irq_gpio_ack(struct irq_data *d)
401 {
402 struct ma35_pin_bank *bank = gpiochip_get_data(irq_data_get_irq_chip_data(d));
403 void __iomem *reg_intsrc = bank->reg_base + MA35_GP_REG_INTSRC;
404 irq_hw_number_t hwirq = irqd_to_hwirq(d);
405
406 writel(BIT(hwirq), reg_intsrc);
407 }
408
ma35_irq_gpio_mask(struct irq_data * d)409 static void ma35_irq_gpio_mask(struct irq_data *d)
410 {
411 struct ma35_pin_bank *bank = gpiochip_get_data(irq_data_get_irq_chip_data(d));
412 void __iomem *reg_ien = bank->reg_base + MA35_GP_REG_INTEN;
413 irq_hw_number_t hwirq = irqd_to_hwirq(d);
414 u32 regval;
415
416 regval = readl(reg_ien);
417
418 regval &= ~MA35_GP_INTEN_BOTH(hwirq);
419
420 writel(regval, reg_ien);
421 }
422
ma35_irq_gpio_unmask(struct irq_data * d)423 static void ma35_irq_gpio_unmask(struct irq_data *d)
424 {
425 struct ma35_pin_bank *bank = gpiochip_get_data(irq_data_get_irq_chip_data(d));
426 void __iomem *reg_itype = bank->reg_base + MA35_GP_REG_INTTYPE;
427 void __iomem *reg_ien = bank->reg_base + MA35_GP_REG_INTEN;
428 irq_hw_number_t hwirq = irqd_to_hwirq(d);
429 u32 bval, regval;
430
431 bval = bank->irqtype & BIT(hwirq);
432 regval = readl(reg_itype);
433 regval &= ~BIT(hwirq);
434 writel(regval | bval, reg_itype);
435
436 bval = bank->irqinten & MA35_GP_INTEN_BOTH(hwirq);
437 regval = readl(reg_ien);
438 regval &= ~MA35_GP_INTEN_BOTH(hwirq);
439 writel(regval | bval, reg_ien);
440 }
441
ma35_irq_irqtype(struct irq_data * d,unsigned int type)442 static int ma35_irq_irqtype(struct irq_data *d, unsigned int type)
443 {
444 struct ma35_pin_bank *bank = gpiochip_get_data(irq_data_get_irq_chip_data(d));
445 irq_hw_number_t hwirq = irqd_to_hwirq(d);
446
447 switch (type) {
448 case IRQ_TYPE_EDGE_BOTH:
449 irq_set_handler_locked(d, handle_edge_irq);
450 bank->irqtype &= ~BIT(hwirq);
451 bank->irqinten |= MA35_GP_INTEN_BOTH(hwirq);
452 break;
453 case IRQ_TYPE_EDGE_RISING:
454 case IRQ_TYPE_LEVEL_HIGH:
455 irq_set_handler_locked(d, handle_edge_irq);
456 bank->irqtype &= ~BIT(hwirq);
457 bank->irqinten |= MA35_GP_INTEN_H(hwirq);
458 bank->irqinten &= ~MA35_GP_INTEN_L(hwirq);
459 break;
460 case IRQ_TYPE_EDGE_FALLING:
461 case IRQ_TYPE_LEVEL_LOW:
462 irq_set_handler_locked(d, handle_edge_irq);
463 bank->irqtype &= ~BIT(hwirq);
464 bank->irqinten |= MA35_GP_INTEN_L(hwirq);
465 bank->irqinten &= ~MA35_GP_INTEN_H(hwirq);
466 break;
467 default:
468 return -EINVAL;
469 }
470
471 writel(bank->irqtype, bank->reg_base + MA35_GP_REG_INTTYPE);
472 writel(bank->irqinten, bank->reg_base + MA35_GP_REG_INTEN);
473
474 return 0;
475 }
476
477 static struct irq_chip ma35_gpio_irqchip = {
478 .name = "MA35-GPIO-IRQ",
479 .irq_disable = ma35_irq_gpio_mask,
480 .irq_enable = ma35_irq_gpio_unmask,
481 .irq_ack = ma35_irq_gpio_ack,
482 .irq_mask = ma35_irq_gpio_mask,
483 .irq_unmask = ma35_irq_gpio_unmask,
484 .irq_set_type = ma35_irq_irqtype,
485 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,
486 GPIOCHIP_IRQ_RESOURCE_HELPERS,
487 };
488
ma35_irq_demux_intgroup(struct irq_desc * desc)489 static void ma35_irq_demux_intgroup(struct irq_desc *desc)
490 {
491 struct ma35_pin_bank *bank = gpiochip_get_data(irq_desc_get_handler_data(desc));
492 struct irq_domain *irqdomain = bank->chip.irq.domain;
493 struct irq_chip *irqchip = irq_desc_get_chip(desc);
494 unsigned long isr;
495 int offset;
496
497 chained_irq_enter(irqchip, desc);
498
499 isr = readl(bank->reg_base + MA35_GP_REG_INTSRC);
500
501 for_each_set_bit(offset, &isr, bank->nr_pins)
502 generic_handle_irq(irq_find_mapping(irqdomain, offset));
503
504 chained_irq_exit(irqchip, desc);
505 }
506
ma35_gpiolib_register(struct platform_device * pdev,struct ma35_pinctrl * npctl)507 static int ma35_gpiolib_register(struct platform_device *pdev, struct ma35_pinctrl *npctl)
508 {
509 struct ma35_pin_ctrl *ctrl = npctl->ctrl;
510 struct ma35_pin_bank *bank = ctrl->pin_banks;
511 int ret;
512 int i;
513
514 for (i = 0; i < ctrl->nr_banks; i++, bank++) {
515 if (!bank->valid) {
516 dev_warn(&pdev->dev, "%pfw: bank is not valid\n", bank->fwnode);
517 continue;
518 }
519 bank->irqtype = 0;
520 bank->irqinten = 0;
521 bank->chip.label = bank->name;
522 bank->chip.parent = &pdev->dev;
523 bank->chip.request = ma35_gpio_core_to_request;
524 bank->chip.direction_input = ma35_gpio_core_direction_in;
525 bank->chip.direction_output = ma35_gpio_core_direction_out;
526 bank->chip.get = ma35_gpio_core_get;
527 bank->chip.set = ma35_gpio_core_set;
528 bank->chip.base = -1;
529 bank->chip.ngpio = bank->nr_pins;
530 bank->chip.can_sleep = false;
531
532 if (bank->irq > 0) {
533 struct gpio_irq_chip *girq;
534
535 girq = &bank->chip.irq;
536 gpio_irq_chip_set_chip(girq, &ma35_gpio_irqchip);
537 girq->parent_handler = ma35_irq_demux_intgroup;
538 girq->num_parents = 1;
539
540 girq->parents = devm_kcalloc(&pdev->dev, girq->num_parents,
541 sizeof(*girq->parents), GFP_KERNEL);
542 if (!girq->parents)
543 return -ENOMEM;
544
545 girq->parents[0] = bank->irq;
546 girq->default_type = IRQ_TYPE_NONE;
547 girq->handler = handle_bad_irq;
548 }
549
550 ret = devm_gpiochip_add_data(&pdev->dev, &bank->chip, bank);
551 if (ret) {
552 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
553 bank->chip.label, ret);
554 return ret;
555 }
556 }
557 return 0;
558 }
559
ma35_get_bank_data(struct ma35_pin_bank * bank)560 static int ma35_get_bank_data(struct ma35_pin_bank *bank)
561 {
562 bank->reg_base = fwnode_iomap(bank->fwnode, 0);
563 if (!bank->reg_base)
564 return -ENOMEM;
565
566 bank->irq = fwnode_irq_get(bank->fwnode, 0);
567
568 bank->nr_pins = MA35_GPIO_PORT_MAX;
569
570 bank->clk = of_clk_get(to_of_node(bank->fwnode), 0);
571 if (IS_ERR(bank->clk))
572 return PTR_ERR(bank->clk);
573
574 return clk_prepare_enable(bank->clk);
575 }
576
ma35_pinctrl_get_soc_data(struct ma35_pinctrl * pctl,struct platform_device * pdev)577 static int ma35_pinctrl_get_soc_data(struct ma35_pinctrl *pctl, struct platform_device *pdev)
578 {
579 struct fwnode_handle *child;
580 struct ma35_pin_ctrl *ctrl;
581 struct ma35_pin_bank *bank;
582 int i, id = 0;
583
584 ctrl = pctl->ctrl;
585 ctrl->nr_banks = MA35_GPIO_BANK_MAX;
586
587 ctrl->pin_banks = devm_kcalloc(&pdev->dev, ctrl->nr_banks,
588 sizeof(*ctrl->pin_banks), GFP_KERNEL);
589 if (!ctrl->pin_banks)
590 return -ENOMEM;
591
592 for (i = 0; i < ctrl->nr_banks; i++) {
593 ctrl->pin_banks[i].bank_num = i;
594 ctrl->pin_banks[i].name = gpio_group_name[i];
595 }
596
597 for_each_gpiochip_node(&pdev->dev, child) {
598 bank = &ctrl->pin_banks[id];
599 bank->fwnode = child;
600 bank->regmap = pctl->regmap;
601 bank->dev = &pdev->dev;
602 if (!ma35_get_bank_data(bank))
603 bank->valid = true;
604 id++;
605 }
606 return 0;
607 }
608
ma35_gpio_cla_port(unsigned int gpio_num,unsigned int * group,unsigned int * num)609 static void ma35_gpio_cla_port(unsigned int gpio_num, unsigned int *group,
610 unsigned int *num)
611 {
612 *group = gpio_num / MA35_GPIO_PORT_MAX;
613 *num = gpio_num % MA35_GPIO_PORT_MAX;
614 }
615
ma35_pinconf_set_pull(struct ma35_pinctrl * npctl,unsigned int pin,int pull_up)616 static int ma35_pinconf_set_pull(struct ma35_pinctrl *npctl, unsigned int pin,
617 int pull_up)
618 {
619 unsigned int port, group_num;
620 void __iomem *base;
621 u32 regval, pull_sel = MA35_GP_PUSEL_DISABLE;
622
623 ma35_gpio_cla_port(pin, &group_num, &port);
624 base = npctl->ctrl->pin_banks[group_num].reg_base;
625
626 regval = readl(base + MA35_GP_REG_PUSEL);
627 regval &= ~MA35_GP_PUSEL_MASK(port);
628
629 switch (pull_up) {
630 case PIN_CONFIG_BIAS_PULL_UP:
631 pull_sel = MA35_GP_PUSEL_PULL_UP;
632 break;
633
634 case PIN_CONFIG_BIAS_PULL_DOWN:
635 pull_sel = MA35_GP_PUSEL_PULL_DOWN;
636 break;
637
638 case PIN_CONFIG_BIAS_DISABLE:
639 pull_sel = MA35_GP_PUSEL_DISABLE;
640 break;
641 }
642
643 regval |= field_prep(MA35_GP_PUSEL_MASK(port), pull_sel);
644 writel(regval, base + MA35_GP_REG_PUSEL);
645
646 return 0;
647 }
648
ma35_pinconf_get_output(struct ma35_pinctrl * npctl,unsigned int pin)649 static int ma35_pinconf_get_output(struct ma35_pinctrl *npctl, unsigned int pin)
650 {
651 unsigned int port, group_num;
652 void __iomem *base;
653 u32 mode;
654
655 ma35_gpio_cla_port(pin, &group_num, &port);
656 base = npctl->ctrl->pin_banks[group_num].reg_base;
657
658 mode = ma35_gpio_get_mode(base + MA35_GP_REG_MODE, port);
659 if (mode == MA35_GP_MODE_OUTPUT)
660 return 1;
661
662 return 0;
663 }
664
ma35_pinconf_get_pull(struct ma35_pinctrl * npctl,unsigned int pin)665 static int ma35_pinconf_get_pull(struct ma35_pinctrl *npctl, unsigned int pin)
666 {
667 unsigned int port, group_num;
668 void __iomem *base;
669 u32 regval, pull_sel;
670
671 ma35_gpio_cla_port(pin, &group_num, &port);
672 base = npctl->ctrl->pin_banks[group_num].reg_base;
673
674 regval = readl(base + MA35_GP_REG_PUSEL);
675
676 pull_sel = field_get(MA35_GP_PUSEL_MASK(port), regval);
677
678 switch (pull_sel) {
679 case MA35_GP_PUSEL_PULL_UP:
680 return PIN_CONFIG_BIAS_PULL_UP;
681
682 case MA35_GP_PUSEL_PULL_DOWN:
683 return PIN_CONFIG_BIAS_PULL_DOWN;
684
685 case MA35_GP_PUSEL_DISABLE:
686 return PIN_CONFIG_BIAS_DISABLE;
687 }
688
689 return PIN_CONFIG_BIAS_DISABLE;
690 }
691
ma35_pinconf_set_output(struct ma35_pinctrl * npctl,unsigned int pin,bool out)692 static int ma35_pinconf_set_output(struct ma35_pinctrl *npctl, unsigned int pin, bool out)
693 {
694 unsigned int port, group_num;
695 void __iomem *base;
696
697 ma35_gpio_cla_port(pin, &group_num, &port);
698 base = npctl->ctrl->pin_banks[group_num].reg_base;
699
700 ma35_gpio_set_mode(base + MA35_GP_REG_MODE, port, MA35_GP_MODE_OUTPUT);
701
702 return 0;
703 }
704
ma35_pinconf_get_power_source(struct ma35_pinctrl * npctl,unsigned int pin)705 static int ma35_pinconf_get_power_source(struct ma35_pinctrl *npctl, unsigned int pin)
706 {
707 unsigned int port, group_num;
708 void __iomem *base;
709 u32 regval;
710
711 ma35_gpio_cla_port(pin, &group_num, &port);
712 base = npctl->ctrl->pin_banks[group_num].reg_base;
713
714 regval = readl(base + MA35_GP_REG_SPW);
715
716 if (regval & BIT(port))
717 return MVOLT_3300;
718 else
719 return MVOLT_1800;
720 }
721
ma35_pinconf_set_power_source(struct ma35_pinctrl * npctl,unsigned int pin,int arg)722 static int ma35_pinconf_set_power_source(struct ma35_pinctrl *npctl,
723 unsigned int pin, int arg)
724 {
725 unsigned int port, group_num;
726 void __iomem *base;
727 u32 regval;
728
729 if ((arg != MVOLT_1800) && (arg != MVOLT_3300))
730 return -EINVAL;
731
732 ma35_gpio_cla_port(pin, &group_num, &port);
733 base = npctl->ctrl->pin_banks[group_num].reg_base;
734
735 regval = readl(base + MA35_GP_REG_SPW);
736
737 if (arg == MVOLT_1800)
738 regval &= ~BIT(port);
739 else
740 regval |= BIT(port);
741
742 writel(regval, base + MA35_GP_REG_SPW);
743
744 return 0;
745 }
746
ma35_pinconf_get_drive_strength(struct ma35_pinctrl * npctl,unsigned int pin,u32 * strength)747 static int ma35_pinconf_get_drive_strength(struct ma35_pinctrl *npctl, unsigned int pin,
748 u32 *strength)
749 {
750 unsigned int port, group_num;
751 void __iomem *base;
752 u32 regval, ds_val;
753
754 ma35_gpio_cla_port(pin, &group_num, &port);
755 base = npctl->ctrl->pin_banks[group_num].reg_base;
756
757 regval = readl(base + MA35_GP_DS_REG(port));
758 ds_val = field_get(MA35_GP_DS_MASK(port), regval);
759
760 if (ma35_pinconf_get_power_source(npctl, pin) == MVOLT_1800)
761 *strength = ds_1800mv_tbl[ds_val];
762 else
763 *strength = ds_3300mv_tbl[ds_val];
764
765 return 0;
766 }
767
ma35_pinconf_set_drive_strength(struct ma35_pinctrl * npctl,unsigned int pin,int strength)768 static int ma35_pinconf_set_drive_strength(struct ma35_pinctrl *npctl, unsigned int pin,
769 int strength)
770 {
771 unsigned int port, group_num;
772 void __iomem *base;
773 int i, ds_val = -1;
774 u32 regval;
775
776 if (ma35_pinconf_get_power_source(npctl, pin) == MVOLT_1800) {
777 for (i = 0; i < ARRAY_SIZE(ds_1800mv_tbl); i++) {
778 if (ds_1800mv_tbl[i] == strength) {
779 ds_val = i;
780 break;
781 }
782 }
783 } else {
784 for (i = 0; i < ARRAY_SIZE(ds_3300mv_tbl); i++) {
785 if (ds_3300mv_tbl[i] == strength) {
786 ds_val = i;
787 break;
788 }
789 }
790 }
791 if (ds_val == -1)
792 return -EINVAL;
793
794 ma35_gpio_cla_port(pin, &group_num, &port);
795 base = npctl->ctrl->pin_banks[group_num].reg_base;
796
797 regval = readl(base + MA35_GP_DS_REG(port));
798 regval &= ~MA35_GP_DS_MASK(port);
799 regval |= field_prep(MA35_GP_DS_MASK(port), ds_val);
800
801 writel(regval, base + MA35_GP_DS_REG(port));
802
803 return 0;
804 }
805
ma35_pinconf_get_schmitt_enable(struct ma35_pinctrl * npctl,unsigned int pin)806 static int ma35_pinconf_get_schmitt_enable(struct ma35_pinctrl *npctl, unsigned int pin)
807 {
808 unsigned int port, group_num;
809 void __iomem *base;
810 u32 regval;
811
812 ma35_gpio_cla_port(pin, &group_num, &port);
813 base = npctl->ctrl->pin_banks[group_num].reg_base;
814
815 regval = readl(base + MA35_GP_REG_SMTEN);
816
817 return !!(regval & BIT(port));
818 }
819
ma35_pinconf_set_schmitt(struct ma35_pinctrl * npctl,unsigned int pin,int enable)820 static int ma35_pinconf_set_schmitt(struct ma35_pinctrl *npctl, unsigned int pin, int enable)
821 {
822 unsigned int port, group_num;
823 void __iomem *base;
824 u32 regval;
825
826 ma35_gpio_cla_port(pin, &group_num, &port);
827 base = npctl->ctrl->pin_banks[group_num].reg_base;
828
829 regval = readl(base + MA35_GP_REG_SMTEN);
830
831 if (enable)
832 regval |= BIT(port);
833 else
834 regval &= ~BIT(port);
835
836 writel(regval, base + MA35_GP_REG_SMTEN);
837
838 return 0;
839 }
840
ma35_pinconf_get_slew_rate(struct ma35_pinctrl * npctl,unsigned int pin)841 static int ma35_pinconf_get_slew_rate(struct ma35_pinctrl *npctl, unsigned int pin)
842 {
843 unsigned int port, group_num;
844 void __iomem *base;
845 u32 regval;
846
847 ma35_gpio_cla_port(pin, &group_num, &port);
848 base = npctl->ctrl->pin_banks[group_num].reg_base;
849
850 regval = readl(base + MA35_GP_REG_SLEWCTL);
851
852 return field_get(MA35_GP_SLEWCTL_MASK(port), regval);
853 }
854
ma35_pinconf_set_slew_rate(struct ma35_pinctrl * npctl,unsigned int pin,int rate)855 static int ma35_pinconf_set_slew_rate(struct ma35_pinctrl *npctl, unsigned int pin, int rate)
856 {
857 unsigned int port, group_num;
858 void __iomem *base;
859 u32 regval;
860
861 ma35_gpio_cla_port(pin, &group_num, &port);
862 base = npctl->ctrl->pin_banks[group_num].reg_base;
863
864 regval = readl(base + MA35_GP_REG_SLEWCTL);
865 regval &= ~MA35_GP_SLEWCTL_MASK(port);
866 regval |= field_prep(MA35_GP_SLEWCTL_MASK(port), rate);
867
868 writel(regval, base + MA35_GP_REG_SLEWCTL);
869
870 return 0;
871 }
872
ma35_pinconf_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)873 static int ma35_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *config)
874 {
875 struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
876 enum pin_config_param param = pinconf_to_config_param(*config);
877 u32 arg;
878 int ret;
879
880 switch (param) {
881 case PIN_CONFIG_BIAS_DISABLE:
882 case PIN_CONFIG_BIAS_PULL_DOWN:
883 case PIN_CONFIG_BIAS_PULL_UP:
884 if (ma35_pinconf_get_pull(npctl, pin) != param)
885 return -EINVAL;
886 arg = 1;
887 break;
888
889 case PIN_CONFIG_DRIVE_STRENGTH:
890 ret = ma35_pinconf_get_drive_strength(npctl, pin, &arg);
891 if (ret)
892 return ret;
893 break;
894
895 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
896 arg = ma35_pinconf_get_schmitt_enable(npctl, pin);
897 break;
898
899 case PIN_CONFIG_SLEW_RATE:
900 arg = ma35_pinconf_get_slew_rate(npctl, pin);
901 break;
902
903 case PIN_CONFIG_OUTPUT_ENABLE:
904 arg = ma35_pinconf_get_output(npctl, pin);
905 break;
906
907 case PIN_CONFIG_POWER_SOURCE:
908 arg = ma35_pinconf_get_power_source(npctl, pin);
909 break;
910
911 default:
912 return -EINVAL;
913 }
914 *config = pinconf_to_config_packed(param, arg);
915
916 return 0;
917 }
918
ma35_pinconf_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned int num_configs)919 static int ma35_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
920 unsigned long *configs, unsigned int num_configs)
921 {
922 struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
923 enum pin_config_param param;
924 unsigned int arg = 0;
925 int i, ret = 0;
926
927 for (i = 0; i < num_configs; i++) {
928 param = pinconf_to_config_param(configs[i]);
929 arg = pinconf_to_config_argument(configs[i]);
930
931 switch (param) {
932 case PIN_CONFIG_BIAS_DISABLE:
933 case PIN_CONFIG_BIAS_PULL_UP:
934 case PIN_CONFIG_BIAS_PULL_DOWN:
935 ret = ma35_pinconf_set_pull(npctl, pin, param);
936 break;
937
938 case PIN_CONFIG_DRIVE_STRENGTH:
939 ret = ma35_pinconf_set_drive_strength(npctl, pin, arg);
940 break;
941
942 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
943 ret = ma35_pinconf_set_schmitt(npctl, pin, 1);
944 break;
945
946 case PIN_CONFIG_INPUT_SCHMITT:
947 ret = ma35_pinconf_set_schmitt(npctl, pin, arg);
948 break;
949
950 case PIN_CONFIG_SLEW_RATE:
951 ret = ma35_pinconf_set_slew_rate(npctl, pin, arg);
952 break;
953
954 case PIN_CONFIG_OUTPUT_ENABLE:
955 ret = ma35_pinconf_set_output(npctl, pin, arg);
956 break;
957
958 case PIN_CONFIG_POWER_SOURCE:
959 ret = ma35_pinconf_set_power_source(npctl, pin, arg);
960 break;
961
962 default:
963 return -EINVAL;
964 }
965
966 if (ret)
967 break;
968 }
969 return ret;
970 }
971
972 static const struct pinconf_ops ma35_pinconf_ops = {
973 .pin_config_get = ma35_pinconf_get,
974 .pin_config_set = ma35_pinconf_set,
975 .is_generic = true,
976 };
977
ma35_pinctrl_parse_groups(struct fwnode_handle * fwnode,struct group_desc * grp,struct ma35_pinctrl * npctl,u32 index)978 static int ma35_pinctrl_parse_groups(struct fwnode_handle *fwnode, struct group_desc *grp,
979 struct ma35_pinctrl *npctl, u32 index)
980 {
981 struct device_node *np = to_of_node(fwnode);
982 struct ma35_pin_setting *pin;
983 unsigned long *configs;
984 unsigned int nconfigs;
985 unsigned int *pins;
986 int i, j, count, ret;
987 u32 *elems;
988
989 ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &nconfigs);
990 if (ret)
991 return ret;
992
993 count = fwnode_property_count_u32(fwnode, "nuvoton,pins");
994 if (!count || count % 3)
995 return -EINVAL;
996
997 elems = devm_kmalloc_array(npctl->dev, count, sizeof(u32), GFP_KERNEL);
998 if (!elems)
999 return -ENOMEM;
1000
1001 grp->grp.name = np->name;
1002
1003 ret = fwnode_property_read_u32_array(fwnode, "nuvoton,pins", elems, count);
1004 if (ret)
1005 return -EINVAL;
1006 grp->grp.npins = count / 3;
1007
1008 pins = devm_kcalloc(npctl->dev, grp->grp.npins, sizeof(*pins), GFP_KERNEL);
1009 if (!pins)
1010 return -ENOMEM;
1011 grp->grp.pins = pins;
1012
1013 pin = devm_kcalloc(npctl->dev, grp->grp.npins, sizeof(*pin), GFP_KERNEL);
1014 if (!pin)
1015 return -ENOMEM;
1016 grp->data = pin;
1017
1018 for (i = 0, j = 0; i < count; i += 3, j++) {
1019 pin->offset = elems[i] * MA35_MFP_REG_SZ_PER_BANK + MA35_MFP_REG_BASE;
1020 pin->shift = (elems[i + 1] * MA35_MFP_BITS_PER_PORT) % 32;
1021 pin->muxval = elems[i + 2];
1022 pin->configs = configs;
1023 pin->nconfigs = nconfigs;
1024 pins[j] = npctl->info->get_pin_num(pin->offset, pin->shift);
1025 pin++;
1026 }
1027 return 0;
1028 }
1029
ma35_pinctrl_parse_functions(struct fwnode_handle * fwnode,struct ma35_pinctrl * npctl,u32 index)1030 static int ma35_pinctrl_parse_functions(struct fwnode_handle *fwnode, struct ma35_pinctrl *npctl,
1031 u32 index)
1032 {
1033 struct device_node *np = to_of_node(fwnode);
1034 struct fwnode_handle *child;
1035 struct pinfunction *func;
1036 struct group_desc *grp;
1037 static u32 grp_index;
1038 const char **groups;
1039 u32 ret, i = 0;
1040
1041 dev_dbg(npctl->dev, "parse function(%d): %s\n", index, np->name);
1042
1043 func = &npctl->functions[index];
1044 func->name = np->name;
1045 func->ngroups = of_get_child_count(np);
1046
1047 if (func->ngroups <= 0)
1048 return 0;
1049
1050 groups = devm_kcalloc(npctl->dev, func->ngroups, sizeof(*groups), GFP_KERNEL);
1051 if (!groups)
1052 return -ENOMEM;
1053
1054 fwnode_for_each_child_node(fwnode, child) {
1055 struct device_node *node = to_of_node(child);
1056
1057 groups[i] = node->name;
1058 grp = &npctl->groups[grp_index++];
1059 ret = ma35_pinctrl_parse_groups(child, grp, npctl, i++);
1060 if (ret) {
1061 fwnode_handle_put(child);
1062 return ret;
1063 }
1064 }
1065
1066 func->groups = groups;
1067 return 0;
1068 }
1069
ma35_pinctrl_probe_dt(struct platform_device * pdev,struct ma35_pinctrl * npctl)1070 static int ma35_pinctrl_probe_dt(struct platform_device *pdev, struct ma35_pinctrl *npctl)
1071 {
1072 struct device *dev = &pdev->dev;
1073 struct fwnode_handle *child;
1074 u32 idx = 0;
1075 int ret;
1076
1077 device_for_each_child_node(dev, child) {
1078 if (fwnode_property_present(child, "gpio-controller"))
1079 continue;
1080
1081 npctl->nfunctions++;
1082 npctl->ngroups += of_get_child_count(to_of_node(child));
1083 }
1084
1085 if (!npctl->nfunctions)
1086 return -EINVAL;
1087
1088 npctl->functions = devm_kcalloc(&pdev->dev, npctl->nfunctions,
1089 sizeof(*npctl->functions), GFP_KERNEL);
1090 if (!npctl->functions)
1091 return -ENOMEM;
1092
1093 npctl->groups = devm_kcalloc(&pdev->dev, npctl->ngroups,
1094 sizeof(*npctl->groups), GFP_KERNEL);
1095 if (!npctl->groups)
1096 return -ENOMEM;
1097
1098 device_for_each_child_node(dev, child) {
1099 if (fwnode_property_present(child, "gpio-controller"))
1100 continue;
1101
1102 ret = ma35_pinctrl_parse_functions(child, npctl, idx++);
1103 if (ret) {
1104 fwnode_handle_put(child);
1105 dev_err(&pdev->dev, "failed to parse function\n");
1106 return ret;
1107 }
1108 }
1109 return 0;
1110 }
1111
ma35_pinctrl_probe(struct platform_device * pdev,const struct ma35_pinctrl_soc_info * info)1112 int ma35_pinctrl_probe(struct platform_device *pdev, const struct ma35_pinctrl_soc_info *info)
1113 {
1114 struct pinctrl_desc *ma35_pinctrl_desc;
1115 struct device *dev = &pdev->dev;
1116 struct ma35_pinctrl *npctl;
1117 int ret;
1118
1119 if (!info || !info->pins || !info->npins) {
1120 dev_err(&pdev->dev, "wrong pinctrl info\n");
1121 return -EINVAL;
1122 }
1123
1124 npctl = devm_kzalloc(&pdev->dev, sizeof(*npctl), GFP_KERNEL);
1125 if (!npctl)
1126 return -ENOMEM;
1127
1128 ma35_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*ma35_pinctrl_desc), GFP_KERNEL);
1129 if (!ma35_pinctrl_desc)
1130 return -ENOMEM;
1131
1132 npctl->ctrl = devm_kzalloc(&pdev->dev, sizeof(*npctl->ctrl), GFP_KERNEL);
1133 if (!npctl->ctrl)
1134 return -ENOMEM;
1135
1136 ma35_pinctrl_desc->name = dev_name(&pdev->dev);
1137 ma35_pinctrl_desc->pins = info->pins;
1138 ma35_pinctrl_desc->npins = info->npins;
1139 ma35_pinctrl_desc->pctlops = &ma35_pctrl_ops;
1140 ma35_pinctrl_desc->pmxops = &ma35_pmx_ops;
1141 ma35_pinctrl_desc->confops = &ma35_pinconf_ops;
1142 ma35_pinctrl_desc->owner = THIS_MODULE;
1143
1144 npctl->info = info;
1145 npctl->dev = &pdev->dev;
1146
1147 npctl->regmap = syscon_regmap_lookup_by_phandle(dev_of_node(dev), "nuvoton,sys");
1148 if (IS_ERR(npctl->regmap))
1149 return dev_err_probe(&pdev->dev, PTR_ERR(npctl->regmap),
1150 "No syscfg phandle specified\n");
1151
1152 ret = ma35_pinctrl_get_soc_data(npctl, pdev);
1153 if (ret)
1154 return dev_err_probe(&pdev->dev, ret, "fail to get soc data\n");
1155
1156 platform_set_drvdata(pdev, npctl);
1157
1158 ret = ma35_pinctrl_probe_dt(pdev, npctl);
1159 if (ret)
1160 return dev_err_probe(&pdev->dev, ret, "fail to probe MA35 pinctrl dt\n");
1161
1162 ret = devm_pinctrl_register_and_init(dev, ma35_pinctrl_desc, npctl, &npctl->pctl);
1163 if (ret)
1164 return dev_err_probe(&pdev->dev, ret, "fail to register MA35 pinctrl\n");
1165
1166 ret = pinctrl_enable(npctl->pctl);
1167 if (ret)
1168 return dev_err_probe(&pdev->dev, ret, "fail to enable MA35 pinctrl\n");
1169
1170 return ma35_gpiolib_register(pdev, npctl);
1171 }
1172
ma35_pinctrl_suspend(struct device * dev)1173 int ma35_pinctrl_suspend(struct device *dev)
1174 {
1175 struct ma35_pinctrl *npctl = dev_get_drvdata(dev);
1176
1177 return pinctrl_force_sleep(npctl->pctl);
1178 }
1179
ma35_pinctrl_resume(struct device * dev)1180 int ma35_pinctrl_resume(struct device *dev)
1181 {
1182 struct ma35_pinctrl *npctl = dev_get_drvdata(dev);
1183
1184 return pinctrl_force_default(npctl->pctl);
1185 }
1186