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Searched defs:LogicOp (Results 1 – 8 of 8) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp1033 struct LogicOp { struct
1035 LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize) in LogicOp() argument
1038 explicit operator bool() const { return RegSize; } in operator bool()
1040 unsigned RegSize = 0;
1041 unsigned ImmLSB = 0;
1042 unsigned ImmSize = 0;
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp3078 SDValue IntegerCompareEliminator::computeLogicOpInGPR(SDValue LogicOp) { in computeLogicOpInGPR()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h4330 const SDNode *LogicOp, const SDNode *SETCC0, const SDNode *SETCC1) const { in isDesirableToCombineLogicOpOfSETCC()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp8756 Instruction *LogicOp; in splitBranchCondition() local
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp6151 static SDValue foldAndOrOfSETCC(SDNode *LogicOp, SelectionDAG &DAG) { in foldAndOrOfSETCC()
6860 static SDValue foldLogicOfShifts(SDNode *N, SDValue LogicOp, SDValue ShiftOp, in foldLogicOfShifts()
9621 SDValue LogicOp = Shift->getOperand(0); in combineShiftOfShiftedLogic() local
H A DTargetLowering.cpp4523 unsigned LogicOp = Cond == ISD::SETEQ ? ISD::OR : ISD::AND; in SimplifySetCC() local
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp21876 unsigned LogicOp = IsFABS ? X86ISD::FAND : in LowerFABSorFNEG() local
22475 ISD::NodeType LogicOp = CmpNull ? ISD::OR : ISD::AND; in MatchVectorAllEqualTest() local
58021 const SDNode *LogicOp, const SDNode *SETCC0, const SDNode *SETCC1) const { in isDesirableToCombineLogicOpOfSETCC() argument
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp10294 unsigned LogicOp = (Cond == ISD::SETEQ) ? ISD::AND : ISD::OR; in performOrXorChainCombine() local