1/*- 2 * Copyright (c) 2012-2014 Andrew Turner 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include "assym.inc" 28#include "opt_kstack_pages.h" 29#include <sys/elf_common.h> 30#include <sys/syscall.h> 31#include <machine/asm.h> 32#include <machine/armreg.h> 33#include <machine/cpu.h> 34#include <machine/hypervisor.h> 35#include <machine/param.h> 36#include <machine/pte.h> 37#include <machine/vm.h> 38#include <machine/vmparam.h> 39 40#define VIRT_BITS 48 41 42#if PAGE_SIZE == PAGE_SIZE_16K 43/* 44 * The number of level 3 tables to create. 32 will allow for 1G of address 45 * space, the same as a single level 2 page with 4k pages. 46 */ 47#define L3_PAGE_COUNT 32 48#endif 49 50/* 51 * The size of our bootstrap stack. 52 */ 53#define BOOT_STACK_SIZE (KSTACK_PAGES * PAGE_SIZE) 54 55 .globl kernbase 56 .set kernbase, KERNBASE 57 58/* 59 * We assume: 60 * MMU on with an identity map, or off 61 * D-Cache: off 62 * I-Cache: on or off 63 * We are loaded at a 2MiB aligned address 64 */ 65 66ENTRY(_start) 67 /* Enter the kernel exception level */ 68 bl enter_kernel_el 69 70 /* Set the context id */ 71 msr contextidr_el1, xzr 72 73 /* Get the virt -> phys offset */ 74 bl get_load_phys_addr 75 76 /* 77 * At this point: 78 * x28 = Our physical load address 79 */ 80 81 /* Create the page tables */ 82 bl create_pagetables 83 84 /* 85 * At this point: 86 * x27 = TTBR0 table 87 * x26 = Kernel L1 table 88 * x24 = TTBR1 table 89 * x22 = PTE shareability attributes 90 */ 91 92 /* Enable the mmu */ 93 bl start_mmu 94 95 /* Load the new ttbr0 pagetable */ 96 adrp x27, pagetable_l0_ttbr0 97 add x27, x27, :lo12:pagetable_l0_ttbr0 98 99 /* Jump to the virtual address space */ 100 ldr x15, .Lvirtdone 101 br x15 102 103virtdone: 104 BTI_J 105 106 /* Set up the stack */ 107 adrp x25, initstack_end 108 add x25, x25, :lo12:initstack_end 109 sub sp, x25, #PCB_SIZE 110 111 /* Zero the BSS */ 112 ldr x15, .Lbss 113 ldr x14, .Lend 1141: 115 stp xzr, xzr, [x15], #16 116 cmp x15, x14 117 b.lo 1b 118 119#if defined(PERTHREAD_SSP) 120 /* Set sp_el0 to the boot canary for early per-thread SSP to work */ 121 adrp x15, boot_canary 122 add x15, x15, :lo12:boot_canary 123 msr sp_el0, x15 124#endif 125 126 /* Backup the module pointer */ 127 mov x1, x0 128 129 sub sp, sp, #BOOTPARAMS_SIZE 130 mov x0, sp 131 132 str x1, [x0, #BP_MODULEP] 133 adrp x25, initstack 134 add x25, x25, :lo12:initstack 135 str x25, [x0, #BP_KERN_STACK] 136 str x27, [x0, #BP_KERN_TTBR0] 137 str x23, [x0, #BP_BOOT_EL] 138 139 /* Set this before it's used in kasan_init_early */ 140 adrp x1, pmap_sh_attr 141 str x22, [x1, :lo12:pmap_sh_attr] 142 143#ifdef KASAN 144 /* Save bootparams */ 145 mov x19, x0 146 147 /* Bootstrap an early shadow map for the boot stack. */ 148 ldr x0, [x0, #BP_KERN_STACK] 149 ldr x1, =BOOT_STACK_SIZE 150 bl kasan_init_early 151 152 /* Restore bootparams */ 153 mov x0, x19 154#endif 155 156 /* trace back starts here */ 157 mov fp, #0 158 /* Branch to C code */ 159 bl initarm 160 /* We are done with the boot params */ 161 add sp, sp, #BOOTPARAMS_SIZE 162 163 /* 164 * Enable pointer authentication in the kernel. We set the keys for 165 * thread0 in initarm so have to wait until it returns to enable it. 166 * If we were to enable it in initarm then any authentication when 167 * returning would fail as it was called with pointer authentication 168 * disabled. 169 */ 170 bl ptrauth_start 171 172 bl mi_startup 173 174 /* We should not get here */ 175 brk 0 176 177 .align 3 178.Lvirtdone: 179 .quad virtdone 180.Lbss: 181 .quad __bss_start 182.Lend: 183 .quad __bss_end 184END(_start) 185 186#ifdef SMP 187/* 188 * void 189 * mpentry_psci(unsigned long) 190 * 191 * Called by a core when it is being brought online with psci. 192 * The data in x0 is passed straight to init_secondary. 193 */ 194ENTRY(mpentry_psci) 195 mov x26, xzr 196 b mpentry_common 197END(mpentry_psci) 198 199/* 200 * void 201 * mpentry_spintable(void) 202 * 203 * Called by a core when it is being brought online with a spin-table. 204 * Reads the new CPU ID and passes this to init_secondary. 205 */ 206ENTRY(mpentry_spintable) 207 ldr x26, =spintable_wait 208 b mpentry_common 209END(mpentry_spintable) 210 211/* Wait for the current CPU to be released */ 212LENTRY(spintable_wait) 213 /* Read the affinity bits from mpidr_el1 */ 214 mrs x1, mpidr_el1 215 ldr x2, =CPU_AFF_MASK 216 and x1, x1, x2 217 218 adrp x2, ap_cpuid 2191: 220 ldr x0, [x2, :lo12:ap_cpuid] 221 cmp x0, x1 222 b.ne 1b 223 224 str xzr, [x2, :lo12:ap_cpuid] 225 dsb sy 226 sev 227 228 ret 229LEND(mpentry_spintable) 230 231LENTRY(mpentry_common) 232 /* Disable interrupts */ 233 msr daifset, #DAIF_INTR 234 235 /* Enter the kernel exception level */ 236 bl enter_kernel_el 237 238 /* Set the context id */ 239 msr contextidr_el1, xzr 240 241 /* Load the kernel page table */ 242 adrp x24, pagetable_l0_ttbr1 243 add x24, x24, :lo12:pagetable_l0_ttbr1 244 /* Load the identity page table */ 245 adrp x27, pagetable_l0_ttbr0_bootstrap 246 add x27, x27, :lo12:pagetable_l0_ttbr0_bootstrap 247 248 /* Enable the mmu */ 249 bl start_mmu 250 251 /* Load the new ttbr0 pagetable */ 252 adrp x27, pagetable_l0_ttbr0 253 add x27, x27, :lo12:pagetable_l0_ttbr0 254 255 /* Jump to the virtual address space */ 256 ldr x15, =mp_virtdone 257 br x15 258 259mp_virtdone: 260 BTI_J 261 262 /* 263 * Allow this CPU to wait until the kernel is ready for it, 264 * e.g. with spin-table but each CPU uses the same release address 265 */ 266 cbz x26, 1f 267 blr x26 2681: 269 270 /* Start using the AP boot stack */ 271 adrp x4, bootstack 272 ldr x4, [x4, :lo12:bootstack] 273 mov sp, x4 274 275#if defined(PERTHREAD_SSP) 276 /* Set sp_el0 to the boot canary for early per-thread SSP to work */ 277 adrp x15, boot_canary 278 add x15, x15, :lo12:boot_canary 279 msr sp_el0, x15 280#endif 281 282 /* Load the kernel ttbr0 pagetable */ 283 msr ttbr0_el1, x27 284 isb 285 286 /* Invalidate the TLB */ 287 tlbi vmalle1 288 dsb sy 289 isb 290 291 /* 292 * Initialize the per-CPU pointer before calling into C code, for the 293 * benefit of kernel sanitizers. 294 */ 295 adrp x18, bootpcpu 296 ldr x18, [x18, :lo12:bootpcpu] 297 msr tpidr_el1, x18 298 299 b init_secondary 300LEND(mpentry_common) 301#endif 302 303/* 304 * Enter the exception level the kernel will use: 305 * 306 * - If in EL1 continue in EL1 307 * - If the CPU supports FEAT_VHE then set HCR_E2H and HCR_TGE and continue 308 * in EL2 309 * - Configure EL2 to support running the kernel at EL1 and exit to that 310 */ 311LENTRY(enter_kernel_el) 312#define INIT_SCTLR_EL1 (SCTLR_LSMAOE | SCTLR_nTLSMD | SCTLR_EIS | \ 313 SCTLR_TSCXT | SCTLR_EOS) 314 mrs x23, CurrentEL 315 and x23, x23, #(CURRENTEL_EL_MASK) 316 cmp x23, #(CURRENTEL_EL_EL2) 317 b.eq 1f 318 319 ldr x2, =INIT_SCTLR_EL1 320 msr sctlr_el1, x2 321 /* SCTLR_EOS is set so eret is a context synchronizing event so we 322 * need an isb here to ensure it's observed by later instructions, 323 * but don't need it in the eret below. 324 */ 325 isb 326 327 /* Ensure SPSR_EL1 and pstate are in sync. The only wat to set the 328 * latter is to set the former and return from an exception with eret. 329 */ 330 mov x2, #(PSR_DAIF | PSR_M_EL1h) 331 msr spsr_el1, x2 332 msr elr_el1, lr 333 eret 334 3351: 336 dsb sy 337 /* 338 * Set just the reserved bits in sctlr_el2. This will disable the 339 * MMU which may have broken the kernel if we enter the kernel in 340 * EL2, e.g. when using VHE. 341 */ 342 ldr x2, =(SCTLR_EL2_RES1 | SCTLR_EL2_EIS | SCTLR_EL2_EOS) 343 msr sctlr_el2, x2 344 isb 345 346 /* Configure the Hypervisor */ 347 ldr x2, =(HCR_RW | HCR_APK | HCR_API | HCR_E2H) 348 msr hcr_el2, x2 349 350 /* Stash value of HCR_EL2 for later */ 351 isb 352 mrs x4, hcr_el2 353 354 355 /* Load the Virtualization Process ID Register */ 356 mrs x2, midr_el1 357 msr vpidr_el2, x2 358 359 /* Load the Virtualization Multiprocess ID Register */ 360 mrs x2, mpidr_el1 361 msr vmpidr_el2, x2 362 363 /* Set the initial sctlr_el1 */ 364 ldr x2, =INIT_SCTLR_EL1 365 msr sctlr_el1, x2 366 367 /* Check if the E2H flag is set */ 368 tst x4, #HCR_E2H 369 b.eq .Lno_vhe 370 371 /* 372 * The kernel will be running in EL2, route exceptions here rather 373 * than EL1. 374 */ 375 orr x4, x4, #(HCR_TGE) 376 msr hcr_el2, x4 377 isb 378 379 msr SCTLR_EL12_REG, x2 380 mov x2, xzr /* CPTR_EL2 is managed by vfp.c */ 381 ldr x3, =(CNTHCTL_E2H_EL1PCTEN | CNTHCTL_E2H_EL1PTEN) 382 ldr x5, =(PSR_DAIF | PSR_M_EL2h) 383 b .Ldone_vhe 384 385.Lno_vhe: 386 /* Hypervisor trap functions */ 387 adrp x2, hyp_stub_vectors 388 add x2, x2, :lo12:hyp_stub_vectors 389 msr vbar_el2, x2 390 391 ldr x2, =(CPTR_RES1) 392 ldr x3, =(CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN) 393 ldr x5, =(PSR_DAIF | PSR_M_EL1h) 394 395.Ldone_vhe: 396 397 msr cptr_el2, x2 398 /* Enable access to the physical timers at EL1 */ 399 msr cnthctl_el2, x3 400 /* Set the return PSTATE */ 401 msr spsr_el2, x5 402 403 /* Don't trap to EL2 for CP15 traps */ 404 msr hstr_el2, xzr 405 406 /* Set the counter offset to a known value */ 407 msr cntvoff_el2, xzr 408 409 /* Zero vttbr_el2 so a hypervisor can tell the host and guest apart */ 410 msr vttbr_el2, xzr 411 412 /* Configure GICv3 CPU interface */ 413 mrs x2, id_aa64pfr0_el1 414 /* Extract GIC bits from the register */ 415 ubfx x2, x2, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_BITS 416 /* GIC[3:0] != 0000 - GIC CPU interface via special regs. supported */ 417 cbz x2, 2f 418 419 mrs x2, icc_sre_el2 420 orr x2, x2, #ICC_SRE_EL2_EN /* Enable access from insecure EL1 */ 421 orr x2, x2, #ICC_SRE_EL2_SRE /* Enable system registers */ 422 msr icc_sre_el2, x2 4232: 424 425 /* Set the address to return to our return address */ 426 msr elr_el2, x30 427 isb 428 429 eret 430#undef INIT_SCTLR_EL1 431LEND(enter_kernel_el) 432 433/* 434 * Get the physical address the kernel was loaded at. 435 */ 436LENTRY(get_load_phys_addr) 437 /* Load the offset of get_load_phys_addr from KERNBASE */ 438 ldr x28, =(get_load_phys_addr - KERNBASE) 439 /* Load the physical address of get_load_phys_addr */ 440 adr x29, get_load_phys_addr 441 /* Find the physical address of KERNBASE, i.e. our load address */ 442 sub x28, x29, x28 443 ret 444LEND(get_load_phys_addr) 445 446/* 447 * This builds the page tables containing the identity map, and the kernel 448 * virtual map. 449 * 450 * It relys on: 451 * We were loaded to an address that is on a 2MiB boundary 452 * All the memory must not cross a 1GiB boundaty 453 * x28 contains the physical address we were loaded from 454 * 455 * There are 7 or 8 pages before that address for the page tables 456 * The pages used are: 457 * - The Kernel L3 tables (only for 16k kernel) 458 * - The Kernel L2 table 459 * - The Kernel L1 table 460 * - The Kernel L0 table (TTBR1) 461 * - The identity (PA = VA) L2 table 462 * - The identity (PA = VA) L1 table 463 * - The identity (PA = VA) L0 table (Early TTBR0) 464 * - The Kernel empty L0 table (Late TTBR0) 465 */ 466LENTRY(create_pagetables) 467 /* Save the Link register */ 468 mov x5, x30 469 470 /* Clean the page table */ 471 adrp x6, pagetable 472 add x6, x6, :lo12:pagetable 473 mov x26, x6 474 adrp x27, pagetable_end 475 add x27, x27, :lo12:pagetable_end 4761: 477 stp xzr, xzr, [x6], #16 478 stp xzr, xzr, [x6], #16 479 stp xzr, xzr, [x6], #16 480 stp xzr, xzr, [x6], #16 481 cmp x6, x27 482 b.lo 1b 483 484 /* 485 * Find the shareability attribute we should use. If FEAT_LPA2 is 486 * enabled then the shareability field is moved from the page table 487 * to tcr_el1 and the bits in the page table are reused by the 488 * address field. 489 */ 490#if PAGE_SIZE == PAGE_SIZE_4K 491#define LPA2_MASK ID_AA64MMFR0_TGran4_MASK 492#define LPA2_VAL ID_AA64MMFR0_TGran4_LPA2 493#elif PAGE_SIZE == PAGE_SIZE_16K 494#define LPA2_MASK ID_AA64MMFR0_TGran16_MASK 495#define LPA2_VAL ID_AA64MMFR0_TGran16_LPA2 496#else 497#error Unsupported page size 498#endif 499 mrs x6, id_aa64mmfr0_el1 500 mov x7, LPA2_VAL 501 and x6, x6, LPA2_MASK 502 cmp x6, x7 503 ldr x22, =(ATTR_SH(ATTR_SH_IS)) 504 csel x22, xzr, x22, eq 505#undef LPA2_MASK 506#undef LPA2_VAL 507 508 /* 509 * Build the TTBR1 maps. 510 */ 511 512 /* Find the size of the kernel */ 513 mov x6, #(KERNBASE) 514 515#if defined(LINUX_BOOT_ABI) 516 /* X19 is used as 'map FDT data' flag */ 517 mov x19, xzr 518 519 /* No modules or FDT pointer ? */ 520 cbz x0, booti_no_fdt 521 522 /* 523 * Test if x0 points to modules descriptor(virtual address) or 524 * to FDT (physical address) 525 */ 526 cmp x0, x6 /* x6 is #(KERNBASE) */ 527 b.lo booti_fdt 528#endif 529 530 /* Booted with modules pointer */ 531 /* Find modulep - begin */ 532 sub x8, x0, x6 533 /* 534 * Add space for the module data. When PAGE_SIZE is 4k this will 535 * add at least 2 level 2 blocks (2 * 2MiB). When PAGE_SIZE is 536 * larger it will be at least as large as we use smaller level 3 537 * pages. 538 */ 539 ldr x7, =((6 * 1024 * 1024) - 1) 540 add x8, x8, x7 541 b common 542 543#if defined(LINUX_BOOT_ABI) 544booti_fdt: 545 /* Booted by U-Boot booti with FDT data */ 546 /* Set 'map FDT data' flag */ 547 mov x19, #1 548 549booti_no_fdt: 550 /* Booted by U-Boot booti without FTD data */ 551 /* Find the end - begin */ 552 ldr x7, .Lend 553 sub x8, x7, x6 554 555 /* 556 * Add one 2MiB page for copy of FDT data (maximum FDT size), 557 * one for metadata and round up 558 */ 559 ldr x7, =(3 * L2_SIZE - 1) 560 add x8, x8, x7 561#endif 562 563common: 564#if PAGE_SIZE != PAGE_SIZE_4K 565 /* 566 * Create L3 and L3C pages. The kernel will be loaded at a 2M aligned 567 * address, enabling the creation of L3C pages. However, when the page 568 * size is larger than 4k, L2 blocks are too large to map the kernel 569 * with 2M alignment. 570 */ 571#define PTE_SHIFT L3_SHIFT 572#define BUILD_PTE_FUNC build_l3_page_pagetable 573#else 574#define PTE_SHIFT L2_SHIFT 575#define BUILD_PTE_FUNC build_l2_block_pagetable 576#endif 577 578 /* Get the number of blocks/pages to allocate, rounded down */ 579 lsr x10, x8, #(PTE_SHIFT) 580 581 /* Create the kernel space PTE table */ 582 mov x6, x26 583 mov x7, #(ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK)) 584 mov x8, #(KERNBASE) 585 mov x9, x28 586 bl BUILD_PTE_FUNC 587 588#undef PTE_SHIFT 589#undef BUILD_PTE_FUNC 590 591#if PAGE_SIZE != PAGE_SIZE_4K 592 /* Move to the l2 table */ 593 ldr x9, =(PAGE_SIZE * L3_PAGE_COUNT) 594 add x26, x26, x9 595 596 /* Link the l2 -> l3 table */ 597 mov x9, x6 598 mov x6, x26 599 bl link_l2_pagetable 600#endif 601 602 /* Move to the l1 table */ 603 add x26, x26, #PAGE_SIZE 604 605 /* Link the l1 -> l2 table */ 606 mov x9, x6 607 mov x6, x26 608 bl link_l1_pagetable 609 610 /* Move to the l0 table */ 611 add x24, x26, #PAGE_SIZE 612 613 /* Link the l0 -> l1 table */ 614 mov x9, x6 615 mov x6, x24 616 mov x10, #1 617 bl link_l0_pagetable 618 619 /* 620 * Build the TTBR0 maps. As TTBR0 maps, they must specify ATTR_S1_nG. 621 * They are only needed early on, so the VA = PA map is uncached. 622 */ 623 add x27, x24, #PAGE_SIZE 624 625 mov x6, x27 /* The initial page table */ 626 627 /* Create the VA = PA map */ 628 mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK)) 629 adrp x16, _start 630 and x16, x16, #(~L2_OFFSET) 631 mov x9, x16 /* PA start */ 632 mov x8, x16 /* VA start (== PA start) */ 633 mov x10, #1 634 bl build_l2_block_pagetable 635 636#if defined(SOCDEV_PA) 637 /* Create a table for the UART */ 638 mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_DEVICE)) 639 ldr x9, =(L2_SIZE) 640 add x16, x16, x9 /* VA start */ 641 mov x8, x16 642 643 /* Store the socdev virtual address */ 644 add x17, x8, #(SOCDEV_PA & L2_OFFSET) 645 adrp x9, socdev_va 646 str x17, [x9, :lo12:socdev_va] 647 648 mov x9, #(SOCDEV_PA & ~L2_OFFSET) /* PA start */ 649 mov x10, #1 650 bl build_l2_block_pagetable 651#endif 652 653#if defined(LINUX_BOOT_ABI) 654 /* Map FDT data ? */ 655 cbz x19, 1f 656 657 /* Create the mapping for FDT data (2 MiB max) */ 658 mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK)) 659 ldr x9, =(L2_SIZE) 660 add x16, x16, x9 /* VA start */ 661 mov x8, x16 662 mov x9, x0 /* PA start */ 663 /* Update the module pointer to point at the allocated memory */ 664 and x0, x0, #(L2_OFFSET) /* Keep the lower bits */ 665 add x0, x0, x8 /* Add the aligned virtual address */ 666 667 mov x10, #1 668 bl build_l2_block_pagetable 669 6701: 671#endif 672 673 /* Move to the l1 table */ 674 add x27, x27, #PAGE_SIZE 675 676 /* Link the l1 -> l2 table */ 677 mov x9, x6 678 mov x6, x27 679 bl link_l1_pagetable 680 681 /* Move to the l0 table */ 682 add x27, x27, #PAGE_SIZE 683 684 /* Link the l0 -> l1 table */ 685 mov x9, x6 686 mov x6, x27 687 mov x10, #1 688 bl link_l0_pagetable 689 690 /* Restore the Link register */ 691 mov x30, x5 692 ret 693LEND(create_pagetables) 694 695/* 696 * Builds an L0 -> L1 table descriptor 697 * 698 * x6 = L0 table 699 * x8 = Virtual Address 700 * x9 = L1 PA (trashed) 701 * x10 = Entry count (trashed) 702 * x11, x12 and x13 are trashed 703 */ 704LENTRY(link_l0_pagetable) 705 /* 706 * Link an L0 -> L1 table entry. 707 */ 708 /* Find the table index */ 709 lsr x11, x8, #L0_SHIFT 710 and x11, x11, #L0_ADDR_MASK 711 712 /* Build the L0 block entry */ 713 mov x12, #L0_TABLE 714 orr x12, x12, #(TATTR_UXN_TABLE | TATTR_AP_TABLE_NO_EL0) 715 716 /* Only use the output address bits */ 717 lsr x9, x9, #PAGE_SHIFT 7181: orr x13, x12, x9, lsl #PAGE_SHIFT 719 720 /* Store the entry */ 721 str x13, [x6, x11, lsl #3] 722 723 sub x10, x10, #1 724 add x11, x11, #1 725 add x9, x9, #1 726 cbnz x10, 1b 727 728 ret 729LEND(link_l0_pagetable) 730 731/* 732 * Builds an L1 -> L2 table descriptor 733 * 734 * x6 = L1 table 735 * x8 = Virtual Address 736 * x9 = L2 PA (trashed) 737 * x11, x12 and x13 are trashed 738 */ 739LENTRY(link_l1_pagetable) 740 /* 741 * Link an L1 -> L2 table entry. 742 */ 743 /* Find the table index */ 744 lsr x11, x8, #L1_SHIFT 745 and x11, x11, #Ln_ADDR_MASK 746 747 /* Build the L1 block entry */ 748 mov x12, #L1_TABLE 749 750 /* Only use the output address bits */ 751 lsr x9, x9, #PAGE_SHIFT 752 orr x13, x12, x9, lsl #PAGE_SHIFT 753 754 /* Store the entry */ 755 str x13, [x6, x11, lsl #3] 756 757 ret 758LEND(link_l1_pagetable) 759 760/* 761 * Builds count 2 MiB page table entry 762 * x6 = L2 table 763 * x7 = Block attributes 764 * x8 = VA start 765 * x9 = PA start (trashed) 766 * x10 = Entry count (trashed) 767 * x11, x12 and x13 are trashed 768 */ 769LENTRY(build_l2_block_pagetable) 770 /* 771 * Build the L2 table entry. 772 */ 773 /* Find the table index */ 774 lsr x11, x8, #L2_SHIFT 775 and x11, x11, #Ln_ADDR_MASK 776 777 /* Build the L2 block entry */ 778 orr x12, x7, #L2_BLOCK 779 orr x12, x12, #(ATTR_AF) 780 orr x12, x12, #(ATTR_S1_UXN) 781#ifdef __ARM_FEATURE_BTI_DEFAULT 782 orr x12, x12, #(ATTR_S1_GP) 783#endif 784 /* Set the shareability attribute */ 785 orr x12, x12, x22 786 787 /* Only use the output address bits */ 788 lsr x9, x9, #L2_SHIFT 789 790 /* Set the physical address for this virtual address */ 7911: orr x13, x12, x9, lsl #L2_SHIFT 792 793 /* Store the entry */ 794 str x13, [x6, x11, lsl #3] 795 796 sub x10, x10, #1 797 add x11, x11, #1 798 add x9, x9, #1 799 cbnz x10, 1b 800 801 ret 802LEND(build_l2_block_pagetable) 803 804#if PAGE_SIZE != PAGE_SIZE_4K 805/* 806 * Builds an L2 -> L3 table descriptor 807 * 808 * x6 = L2 table 809 * x8 = Virtual Address 810 * x9 = L3 PA (trashed) 811 * x11, x12 and x13 are trashed 812 */ 813LENTRY(link_l2_pagetable) 814 /* 815 * Link an L2 -> L3 table entry. 816 */ 817 /* Find the table index */ 818 lsr x11, x8, #L2_SHIFT 819 and x11, x11, #Ln_ADDR_MASK 820 821 /* Build the L1 block entry */ 822 mov x12, #L2_TABLE 823 824 /* Only use the output address bits */ 825 lsr x9, x9, #PAGE_SHIFT 826 orr x13, x12, x9, lsl #PAGE_SHIFT 827 828 /* Store the entry */ 829 str x13, [x6, x11, lsl #3] 830 831 ret 832LEND(link_l2_pagetable) 833 834/* 835 * Builds count level 3 page table entries. Uses ATTR_CONTIGUOUS to create 836 * large page (L3C) mappings when the current VA and remaining count allow 837 * it. 838 * x6 = L3 table 839 * x7 = Block attributes 840 * x8 = VA start 841 * x9 = PA start (trashed) 842 * x10 = Entry count (trashed) 843 * x11, x12 and x13 are trashed 844 * 845 * VA start (x8) modulo L3C_SIZE must equal PA start (x9) modulo L3C_SIZE. 846 */ 847LENTRY(build_l3_page_pagetable) 848 /* 849 * Build the L3 table entry. 850 */ 851 /* Find the table index */ 852 lsr x11, x8, #L3_SHIFT 853 and x11, x11, #Ln_ADDR_MASK 854 855 /* Build the L3 page entry */ 856 orr x12, x7, #L3_PAGE 857 orr x12, x12, #(ATTR_AF) 858 orr x12, x12, #(ATTR_S1_UXN) 859#ifdef __ARM_FEATURE_BTI_DEFAULT 860 orr x12, x12, #(ATTR_S1_GP) 861#endif 862 /* Set the shareability attribute */ 863 orr x12, x12, x22 864 865 /* Only use the output address bits */ 866 lsr x9, x9, #L3_SHIFT 867 868 /* Check if an ATTR_CONTIGUOUS mapping is possible */ 8691: tst x11, #(L3C_ENTRIES - 1) 870 b.ne 2f 871 cmp x10, #L3C_ENTRIES 872 b.lo 3f 873 orr x12, x12, #(ATTR_CONTIGUOUS) 874 b 2f 8753: and x12, x12, #(~ATTR_CONTIGUOUS) 876 877 /* Set the physical address for this virtual address */ 8782: orr x13, x12, x9, lsl #L3_SHIFT 879 880 /* Store the entry */ 881 str x13, [x6, x11, lsl #3] 882 883 sub x10, x10, #1 884 add x11, x11, #1 885 add x9, x9, #1 886 cbnz x10, 1b 887 888 ret 889LEND(build_l3_page_pagetable) 890#endif 891 892LENTRY(start_mmu) 893 dsb sy 894 895 /* Load the exception vectors */ 896 ldr x2, =exception_vectors 897 msr vbar_el1, x2 898 899 /* Load ttbr0 and ttbr1 */ 900 msr ttbr0_el1, x27 901 msr ttbr1_el1, x24 902 isb 903 904 /* Clear the Monitor Debug System control register */ 905 msr mdscr_el1, xzr 906 907 /* Invalidate the TLB */ 908 tlbi vmalle1is 909 dsb ish 910 isb 911 912 ldr x2, mair 913 msr mair_el1, x2 914 915 /* 916 * Setup TCR according to the PARange and ASIDBits fields 917 * from ID_AA64MMFR0_EL1 and the HAFDBS field from the 918 * ID_AA64MMFR1_EL1. More precisely, set TCR_EL1.AS 919 * to 1 only if the ASIDBits field equals 0b0010. 920 */ 921 ldr x2, tcr 922 923 /* If x22 contains a non-zero value then LPA2 is not implemented */ 924 cbnz x22, .Lno_lpa2 925 ldr x3, =(TCR_DS) 926 orr x2, x2, x3 927.Lno_lpa2: 928 929 mrs x3, id_aa64mmfr0_el1 930 931 /* Copy the bottom 3 bits from id_aa64mmfr0_el1 into TCR.IPS */ 932 bfi x2, x3, #(TCR_IPS_SHIFT), #(TCR_IPS_WIDTH) 933 and x3, x3, #(ID_AA64MMFR0_ASIDBits_MASK) 934 935 /* Check if the HW supports 16 bit ASIDS */ 936 cmp x3, #(ID_AA64MMFR0_ASIDBits_16) 937 /* If so x3 == 1, else x3 == 0 */ 938 cset x3, eq 939 /* Set TCR.AS with x3 */ 940 bfi x2, x3, #(TCR_ASID_SHIFT), #(TCR_ASID_WIDTH) 941 942 /* 943 * Check if the HW supports access flag updates, and set 944 * TCR_EL1.HA accordingly. The TCR_EL1.HD flag to enable 945 * HW management of dirty state is set in C code as it may 946 * need to be disabled because of CPU errata. 947 */ 948 mrs x3, id_aa64mmfr1_el1 949 and x3, x3, #(ID_AA64MMFR1_HAFDBS_MASK) 950 cbz x3, 1f 951 orr x2, x2, #(TCR_HA) 9521: 953 954 msr tcr_el1, x2 955 956 /* 957 * Setup SCTLR. 958 */ 959 ldr x2, sctlr_set 960 ldr x3, sctlr_clear 961 mrs x1, sctlr_el1 962 bic x1, x1, x3 /* Clear the required bits */ 963 orr x1, x1, x2 /* Set the required bits */ 964 msr sctlr_el1, x1 965 isb 966 967 ret 968 969 .align 3 970mair: 971 .quad MAIR_ATTR(MAIR_DEVICE_nGnRnE, VM_MEMATTR_DEVICE_nGnRnE) | \ 972 MAIR_ATTR(MAIR_NORMAL_NC, VM_MEMATTR_UNCACHEABLE) | \ 973 MAIR_ATTR(MAIR_NORMAL_WB, VM_MEMATTR_WRITE_BACK) | \ 974 MAIR_ATTR(MAIR_NORMAL_WT, VM_MEMATTR_WRITE_THROUGH) | \ 975 MAIR_ATTR(MAIR_DEVICE_nGnRE, VM_MEMATTR_DEVICE_nGnRE) 976tcr: 977#if PAGE_SIZE == PAGE_SIZE_4K 978#define TCR_TG (TCR_TG1_4K | TCR_TG0_4K) 979#elif PAGE_SIZE == PAGE_SIZE_16K 980#define TCR_TG (TCR_TG1_16K | TCR_TG0_16K) 981#else 982#error Unsupported page size 983#endif 984 985 .quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_TG | \ 986 TCR_SH1_IS | TCR_ORGN1_WBWA | TCR_IRGN1_WBWA | \ 987 TCR_SH0_IS | TCR_ORGN0_WBWA | TCR_IRGN0_WBWA) 988sctlr_set: 989 /* Bits to set */ 990 .quad (SCTLR_LSMAOE | SCTLR_nTLSMD | SCTLR_UCI | SCTLR_SPAN | \ 991 SCTLR_nTWE | SCTLR_nTWI | SCTLR_UCT | SCTLR_DZE | \ 992 SCTLR_I | SCTLR_SED | SCTLR_SA0 | SCTLR_SA | SCTLR_C | \ 993 SCTLR_M | SCTLR_CP15BEN | SCTLR_BT1 | SCTLR_BT0) 994sctlr_clear: 995 /* Bits to clear */ 996 .quad (SCTLR_EE | SCTLR_E0E | SCTLR_IESB | SCTLR_WXN | SCTLR_UMA | \ 997 SCTLR_ITD | SCTLR_A) 998LEND(start_mmu) 999 1000ENTRY(abort) 1001 b abort 1002END(abort) 1003 1004.bss 1005 .align PAGE_SHIFT 1006initstack: 1007 .space BOOT_STACK_SIZE 1008initstack_end: 1009 1010 .section .init_pagetable, "aw", %nobits 1011 .align PAGE_SHIFT 1012 /* 1013 * 6 initial tables (in the following order): 1014 * L2 for kernel (High addresses) 1015 * L1 for kernel 1016 * L0 for kernel 1017 * L1 bootstrap for user (Low addresses) 1018 * L0 bootstrap for user 1019 * L0 for user 1020 */ 1021 .globl pagetable_l0_ttbr1 1022pagetable: 1023#if PAGE_SIZE != PAGE_SIZE_4K 1024 .space (PAGE_SIZE * L3_PAGE_COUNT) 1025pagetable_l2_ttbr1: 1026#endif 1027 .space PAGE_SIZE 1028pagetable_l1_ttbr1: 1029 .space PAGE_SIZE 1030pagetable_l0_ttbr1: 1031 .space PAGE_SIZE 1032pagetable_l2_ttbr0_bootstrap: 1033 .space PAGE_SIZE 1034pagetable_l1_ttbr0_bootstrap: 1035 .space PAGE_SIZE 1036pagetable_l0_ttbr0_bootstrap: 1037 .space PAGE_SIZE 1038pagetable_l0_ttbr0: 1039 .space PAGE_SIZE 1040pagetable_end: 1041 1042el2_pagetable: 1043 .space PAGE_SIZE 1044 1045 .section .rodata, "a", %progbits 1046 .globl aarch32_sigcode 1047 .align 2 1048aarch32_sigcode: 1049 .word 0xe1a0000d // mov r0, sp 1050 .word 0xe2800040 // add r0, r0, #SIGF_UC 1051 .word 0xe59f700c // ldr r7, [pc, #12] 1052 .word 0xef000000 // swi #0 1053 .word 0xe59f7008 // ldr r7, [pc, #8] 1054 .word 0xef000000 // swi #0 1055 .word 0xeafffffa // b . - 16 1056 .word SYS_sigreturn 1057 .word SYS_exit 1058 .align 3 1059 .size aarch32_sigcode, . - aarch32_sigcode 1060aarch32_esigcode: 1061 .data 1062 .global sz_aarch32_sigcode 1063sz_aarch32_sigcode: 1064 .quad aarch32_esigcode - aarch32_sigcode 1065 1066GNU_PROPERTY_AARCH64_FEATURE_1_NOTE(GNU_PROPERTY_AARCH64_FEATURE_1_VAL) 1067