1 //==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This class prints an AArch64 MCInst to a .s file. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "AArch64InstPrinter.h" 14 #include "MCTargetDesc/AArch64AddressingModes.h" 15 #include "Utils/AArch64BaseInfo.h" 16 #include "llvm/ADT/STLExtras.h" 17 #include "llvm/ADT/StringExtras.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/MC/MCAsmInfo.h" 20 #include "llvm/MC/MCExpr.h" 21 #include "llvm/MC/MCInst.h" 22 #include "llvm/MC/MCRegisterInfo.h" 23 #include "llvm/MC/MCSubtargetInfo.h" 24 #include "llvm/Support/Casting.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/Format.h" 27 #include "llvm/Support/MathExtras.h" 28 #include "llvm/Support/raw_ostream.h" 29 #include <cassert> 30 #include <cstdint> 31 #include <string> 32 33 using namespace llvm; 34 35 #define DEBUG_TYPE "asm-printer" 36 37 #define GET_INSTRUCTION_NAME 38 #define PRINT_ALIAS_INSTR 39 #include "AArch64GenAsmWriter.inc" 40 #define GET_INSTRUCTION_NAME 41 #define PRINT_ALIAS_INSTR 42 #include "AArch64GenAsmWriter1.inc" 43 44 AArch64InstPrinter::AArch64InstPrinter(const MCAsmInfo &MAI, 45 const MCInstrInfo &MII, 46 const MCRegisterInfo &MRI) 47 : MCInstPrinter(MAI, MII, MRI) {} 48 49 AArch64AppleInstPrinter::AArch64AppleInstPrinter(const MCAsmInfo &MAI, 50 const MCInstrInfo &MII, 51 const MCRegisterInfo &MRI) 52 : AArch64InstPrinter(MAI, MII, MRI) {} 53 54 bool AArch64InstPrinter::applyTargetSpecificCLOption(StringRef Opt) { 55 if (Opt == "no-aliases") { 56 PrintAliases = false; 57 return true; 58 } 59 return false; 60 } 61 62 void AArch64InstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const { 63 markup(OS, Markup::Register) << getRegisterName(Reg); 64 } 65 66 void AArch64InstPrinter::printRegName(raw_ostream &OS, MCRegister Reg, 67 unsigned AltIdx) const { 68 markup(OS, Markup::Register) << getRegisterName(Reg, AltIdx); 69 } 70 71 StringRef AArch64InstPrinter::getRegName(MCRegister Reg) const { 72 return getRegisterName(Reg); 73 } 74 75 void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address, 76 StringRef Annot, const MCSubtargetInfo &STI, 77 raw_ostream &O) { 78 // Check for special encodings and print the canonical alias instead. 79 80 unsigned Opcode = MI->getOpcode(); 81 82 if (Opcode == AArch64::SYSxt) 83 if (printSysAlias(MI, STI, O)) { 84 printAnnotation(O, Annot); 85 return; 86 } 87 88 if (Opcode == AArch64::SYSPxt || Opcode == AArch64::SYSPxt_XZR) 89 if (printSyspAlias(MI, STI, O)) { 90 printAnnotation(O, Annot); 91 return; 92 } 93 94 // RPRFM overlaps PRFM (reg), so try to print it as RPRFM here. 95 if ((Opcode == AArch64::PRFMroX) || (Opcode == AArch64::PRFMroW)) { 96 if (printRangePrefetchAlias(MI, STI, O, Annot)) 97 return; 98 } 99 100 // SBFM/UBFM should print to a nicer aliased form if possible. 101 if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri || 102 Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) { 103 const MCOperand &Op0 = MI->getOperand(0); 104 const MCOperand &Op1 = MI->getOperand(1); 105 const MCOperand &Op2 = MI->getOperand(2); 106 const MCOperand &Op3 = MI->getOperand(3); 107 108 bool IsSigned = (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri); 109 bool Is64Bit = (Opcode == AArch64::SBFMXri || Opcode == AArch64::UBFMXri); 110 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) { 111 const char *AsmMnemonic = nullptr; 112 113 switch (Op3.getImm()) { 114 default: 115 break; 116 case 7: 117 if (IsSigned) 118 AsmMnemonic = "sxtb"; 119 else if (!Is64Bit) 120 AsmMnemonic = "uxtb"; 121 break; 122 case 15: 123 if (IsSigned) 124 AsmMnemonic = "sxth"; 125 else if (!Is64Bit) 126 AsmMnemonic = "uxth"; 127 break; 128 case 31: 129 // *xtw is only valid for signed 64-bit operations. 130 if (Is64Bit && IsSigned) 131 AsmMnemonic = "sxtw"; 132 break; 133 } 134 135 if (AsmMnemonic) { 136 O << '\t' << AsmMnemonic << '\t'; 137 printRegName(O, Op0.getReg()); 138 O << ", "; 139 printRegName(O, getWRegFromXReg(Op1.getReg())); 140 printAnnotation(O, Annot); 141 return; 142 } 143 } 144 145 // All immediate shifts are aliases, implemented using the Bitfield 146 // instruction. In all cases the immediate shift amount shift must be in 147 // the range 0 to (reg.size -1). 148 if (Op2.isImm() && Op3.isImm()) { 149 const char *AsmMnemonic = nullptr; 150 int shift = 0; 151 int64_t immr = Op2.getImm(); 152 int64_t imms = Op3.getImm(); 153 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) { 154 AsmMnemonic = "lsl"; 155 shift = 31 - imms; 156 } else if (Opcode == AArch64::UBFMXri && imms != 0x3f && 157 ((imms + 1 == immr))) { 158 AsmMnemonic = "lsl"; 159 shift = 63 - imms; 160 } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) { 161 AsmMnemonic = "lsr"; 162 shift = immr; 163 } else if (Opcode == AArch64::UBFMXri && imms == 0x3f) { 164 AsmMnemonic = "lsr"; 165 shift = immr; 166 } else if (Opcode == AArch64::SBFMWri && imms == 0x1f) { 167 AsmMnemonic = "asr"; 168 shift = immr; 169 } else if (Opcode == AArch64::SBFMXri && imms == 0x3f) { 170 AsmMnemonic = "asr"; 171 shift = immr; 172 } 173 if (AsmMnemonic) { 174 O << '\t' << AsmMnemonic << '\t'; 175 printRegName(O, Op0.getReg()); 176 O << ", "; 177 printRegName(O, Op1.getReg()); 178 O << ", "; 179 markup(O, Markup::Immediate) << "#" << shift; 180 printAnnotation(O, Annot); 181 return; 182 } 183 } 184 185 // SBFIZ/UBFIZ aliases 186 if (Op2.getImm() > Op3.getImm()) { 187 O << '\t' << (IsSigned ? "sbfiz" : "ubfiz") << '\t'; 188 printRegName(O, Op0.getReg()); 189 O << ", "; 190 printRegName(O, Op1.getReg()); 191 O << ", "; 192 markup(O, Markup::Immediate) << "#" << (Is64Bit ? 64 : 32) - Op2.getImm(); 193 O << ", "; 194 markup(O, Markup::Immediate) << "#" << Op3.getImm() + 1; 195 printAnnotation(O, Annot); 196 return; 197 } 198 199 // Otherwise SBFX/UBFX is the preferred form 200 O << '\t' << (IsSigned ? "sbfx" : "ubfx") << '\t'; 201 printRegName(O, Op0.getReg()); 202 O << ", "; 203 printRegName(O, Op1.getReg()); 204 O << ", "; 205 markup(O, Markup::Immediate) << "#" << Op2.getImm(); 206 O << ", "; 207 markup(O, Markup::Immediate) << "#" << Op3.getImm() - Op2.getImm() + 1; 208 printAnnotation(O, Annot); 209 return; 210 } 211 212 if (Opcode == AArch64::BFMXri || Opcode == AArch64::BFMWri) { 213 const MCOperand &Op0 = MI->getOperand(0); // Op1 == Op0 214 const MCOperand &Op2 = MI->getOperand(2); 215 int ImmR = MI->getOperand(3).getImm(); 216 int ImmS = MI->getOperand(4).getImm(); 217 218 if ((Op2.getReg() == AArch64::WZR || Op2.getReg() == AArch64::XZR) && 219 (ImmR == 0 || ImmS < ImmR) && STI.hasFeature(AArch64::HasV8_2aOps)) { 220 // BFC takes precedence over its entire range, sligtly differently to BFI. 221 int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32; 222 int LSB = (BitWidth - ImmR) % BitWidth; 223 int Width = ImmS + 1; 224 225 O << "\tbfc\t"; 226 printRegName(O, Op0.getReg()); 227 O << ", "; 228 markup(O, Markup::Immediate) << "#" << LSB; 229 O << ", "; 230 markup(O, Markup::Immediate) << "#" << Width; 231 printAnnotation(O, Annot); 232 return; 233 } else if (ImmS < ImmR) { 234 // BFI alias 235 int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32; 236 int LSB = (BitWidth - ImmR) % BitWidth; 237 int Width = ImmS + 1; 238 239 O << "\tbfi\t"; 240 printRegName(O, Op0.getReg()); 241 O << ", "; 242 printRegName(O, Op2.getReg()); 243 O << ", "; 244 markup(O, Markup::Immediate) << "#" << LSB; 245 O << ", "; 246 markup(O, Markup::Immediate) << "#" << Width; 247 printAnnotation(O, Annot); 248 return; 249 } 250 251 int LSB = ImmR; 252 int Width = ImmS - ImmR + 1; 253 // Otherwise BFXIL the preferred form 254 O << "\tbfxil\t"; 255 printRegName(O, Op0.getReg()); 256 O << ", "; 257 printRegName(O, Op2.getReg()); 258 O << ", "; 259 markup(O, Markup::Immediate) << "#" << LSB; 260 O << ", "; 261 markup(O, Markup::Immediate) << "#" << Width; 262 printAnnotation(O, Annot); 263 return; 264 } 265 266 // Symbolic operands for MOVZ, MOVN and MOVK already imply a shift 267 // (e.g. :gottprel_g1: is always going to be "lsl #16") so it should not be 268 // printed. 269 if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi || 270 Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) && 271 MI->getOperand(1).isExpr()) { 272 if (Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi) 273 O << "\tmovz\t"; 274 else 275 O << "\tmovn\t"; 276 277 printRegName(O, MI->getOperand(0).getReg()); 278 O << ", "; 279 { 280 WithMarkup M = markup(O, Markup::Immediate); 281 O << "#"; 282 MI->getOperand(1).getExpr()->print(O, &MAI); 283 } 284 return; 285 } 286 287 if ((Opcode == AArch64::MOVKXi || Opcode == AArch64::MOVKWi) && 288 MI->getOperand(2).isExpr()) { 289 O << "\tmovk\t"; 290 printRegName(O, MI->getOperand(0).getReg()); 291 O << ", "; 292 { 293 WithMarkup M = markup(O, Markup::Immediate); 294 O << "#"; 295 MI->getOperand(2).getExpr()->print(O, &MAI); 296 } 297 return; 298 } 299 300 auto PrintMovImm = [&](uint64_t Value, int RegWidth) { 301 int64_t SExtVal = SignExtend64(Value, RegWidth); 302 O << "\tmov\t"; 303 printRegName(O, MI->getOperand(0).getReg()); 304 O << ", "; 305 markup(O, Markup::Immediate) << "#" << formatImm(SExtVal); 306 if (CommentStream) { 307 // Do the opposite to that used for instruction operands. 308 if (getPrintImmHex()) 309 *CommentStream << '=' << formatDec(SExtVal) << '\n'; 310 else { 311 uint64_t Mask = maskTrailingOnes<uint64_t>(RegWidth); 312 *CommentStream << '=' << formatHex(SExtVal & Mask) << '\n'; 313 } 314 } 315 }; 316 317 // MOVZ, MOVN and "ORR wzr, #imm" instructions are aliases for MOV, but their 318 // domains overlap so they need to be prioritized. The chain is "MOVZ lsl #0 > 319 // MOVZ lsl #N > MOVN lsl #0 > MOVN lsl #N > ORR". The highest instruction 320 // that can represent the move is the MOV alias, and the rest get printed 321 // normally. 322 if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi) && 323 MI->getOperand(1).isImm() && MI->getOperand(2).isImm()) { 324 int RegWidth = Opcode == AArch64::MOVZXi ? 64 : 32; 325 int Shift = MI->getOperand(2).getImm(); 326 uint64_t Value = (uint64_t)MI->getOperand(1).getImm() << Shift; 327 328 if (AArch64_AM::isMOVZMovAlias(Value, Shift, 329 Opcode == AArch64::MOVZXi ? 64 : 32)) { 330 PrintMovImm(Value, RegWidth); 331 return; 332 } 333 } 334 335 if ((Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) && 336 MI->getOperand(1).isImm() && MI->getOperand(2).isImm()) { 337 int RegWidth = Opcode == AArch64::MOVNXi ? 64 : 32; 338 int Shift = MI->getOperand(2).getImm(); 339 uint64_t Value = ~((uint64_t)MI->getOperand(1).getImm() << Shift); 340 if (RegWidth == 32) 341 Value = Value & 0xffffffff; 342 343 if (AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth)) { 344 PrintMovImm(Value, RegWidth); 345 return; 346 } 347 } 348 349 if ((Opcode == AArch64::ORRXri || Opcode == AArch64::ORRWri) && 350 (MI->getOperand(1).getReg() == AArch64::XZR || 351 MI->getOperand(1).getReg() == AArch64::WZR) && 352 MI->getOperand(2).isImm()) { 353 int RegWidth = Opcode == AArch64::ORRXri ? 64 : 32; 354 uint64_t Value = AArch64_AM::decodeLogicalImmediate( 355 MI->getOperand(2).getImm(), RegWidth); 356 if (!AArch64_AM::isAnyMOVWMovAlias(Value, RegWidth)) { 357 PrintMovImm(Value, RegWidth); 358 return; 359 } 360 } 361 362 if (Opcode == AArch64::SPACE) { 363 O << '\t' << MAI.getCommentString() << " SPACE " 364 << MI->getOperand(1).getImm(); 365 printAnnotation(O, Annot); 366 return; 367 } 368 369 // Instruction TSB is specified as a one operand instruction, but 'csync' is 370 // not encoded, so for printing it is treated as a special case here: 371 if (Opcode == AArch64::TSB) { 372 O << "\ttsb\tcsync"; 373 return; 374 } 375 376 if (!PrintAliases || !printAliasInstr(MI, Address, STI, O)) 377 printInstruction(MI, Address, STI, O); 378 379 printAnnotation(O, Annot); 380 381 if (atomicBarrierDroppedOnZero(Opcode) && 382 (MI->getOperand(0).getReg() == AArch64::XZR || 383 MI->getOperand(0).getReg() == AArch64::WZR)) { 384 printAnnotation(O, "acquire semantics dropped since destination is zero"); 385 } 386 } 387 388 static bool isTblTbxInstruction(unsigned Opcode, StringRef &Layout, 389 bool &IsTbx) { 390 switch (Opcode) { 391 case AArch64::TBXv8i8One: 392 case AArch64::TBXv8i8Two: 393 case AArch64::TBXv8i8Three: 394 case AArch64::TBXv8i8Four: 395 IsTbx = true; 396 Layout = ".8b"; 397 return true; 398 case AArch64::TBLv8i8One: 399 case AArch64::TBLv8i8Two: 400 case AArch64::TBLv8i8Three: 401 case AArch64::TBLv8i8Four: 402 IsTbx = false; 403 Layout = ".8b"; 404 return true; 405 case AArch64::TBXv16i8One: 406 case AArch64::TBXv16i8Two: 407 case AArch64::TBXv16i8Three: 408 case AArch64::TBXv16i8Four: 409 IsTbx = true; 410 Layout = ".16b"; 411 return true; 412 case AArch64::TBLv16i8One: 413 case AArch64::TBLv16i8Two: 414 case AArch64::TBLv16i8Three: 415 case AArch64::TBLv16i8Four: 416 IsTbx = false; 417 Layout = ".16b"; 418 return true; 419 default: 420 return false; 421 } 422 } 423 424 struct LdStNInstrDesc { 425 unsigned Opcode; 426 const char *Mnemonic; 427 const char *Layout; 428 int ListOperand; 429 bool HasLane; 430 int NaturalOffset; 431 }; 432 433 static const LdStNInstrDesc LdStNInstInfo[] = { 434 { AArch64::LD1i8, "ld1", ".b", 1, true, 0 }, 435 { AArch64::LD1i16, "ld1", ".h", 1, true, 0 }, 436 { AArch64::LD1i32, "ld1", ".s", 1, true, 0 }, 437 { AArch64::LD1i64, "ld1", ".d", 1, true, 0 }, 438 { AArch64::LD1i8_POST, "ld1", ".b", 2, true, 1 }, 439 { AArch64::LD1i16_POST, "ld1", ".h", 2, true, 2 }, 440 { AArch64::LD1i32_POST, "ld1", ".s", 2, true, 4 }, 441 { AArch64::LD1i64_POST, "ld1", ".d", 2, true, 8 }, 442 { AArch64::LD1Rv16b, "ld1r", ".16b", 0, false, 0 }, 443 { AArch64::LD1Rv8h, "ld1r", ".8h", 0, false, 0 }, 444 { AArch64::LD1Rv4s, "ld1r", ".4s", 0, false, 0 }, 445 { AArch64::LD1Rv2d, "ld1r", ".2d", 0, false, 0 }, 446 { AArch64::LD1Rv8b, "ld1r", ".8b", 0, false, 0 }, 447 { AArch64::LD1Rv4h, "ld1r", ".4h", 0, false, 0 }, 448 { AArch64::LD1Rv2s, "ld1r", ".2s", 0, false, 0 }, 449 { AArch64::LD1Rv1d, "ld1r", ".1d", 0, false, 0 }, 450 { AArch64::LD1Rv16b_POST, "ld1r", ".16b", 1, false, 1 }, 451 { AArch64::LD1Rv8h_POST, "ld1r", ".8h", 1, false, 2 }, 452 { AArch64::LD1Rv4s_POST, "ld1r", ".4s", 1, false, 4 }, 453 { AArch64::LD1Rv2d_POST, "ld1r", ".2d", 1, false, 8 }, 454 { AArch64::LD1Rv8b_POST, "ld1r", ".8b", 1, false, 1 }, 455 { AArch64::LD1Rv4h_POST, "ld1r", ".4h", 1, false, 2 }, 456 { AArch64::LD1Rv2s_POST, "ld1r", ".2s", 1, false, 4 }, 457 { AArch64::LD1Rv1d_POST, "ld1r", ".1d", 1, false, 8 }, 458 { AArch64::LD1Onev16b, "ld1", ".16b", 0, false, 0 }, 459 { AArch64::LD1Onev8h, "ld1", ".8h", 0, false, 0 }, 460 { AArch64::LD1Onev4s, "ld1", ".4s", 0, false, 0 }, 461 { AArch64::LD1Onev2d, "ld1", ".2d", 0, false, 0 }, 462 { AArch64::LD1Onev8b, "ld1", ".8b", 0, false, 0 }, 463 { AArch64::LD1Onev4h, "ld1", ".4h", 0, false, 0 }, 464 { AArch64::LD1Onev2s, "ld1", ".2s", 0, false, 0 }, 465 { AArch64::LD1Onev1d, "ld1", ".1d", 0, false, 0 }, 466 { AArch64::LD1Onev16b_POST, "ld1", ".16b", 1, false, 16 }, 467 { AArch64::LD1Onev8h_POST, "ld1", ".8h", 1, false, 16 }, 468 { AArch64::LD1Onev4s_POST, "ld1", ".4s", 1, false, 16 }, 469 { AArch64::LD1Onev2d_POST, "ld1", ".2d", 1, false, 16 }, 470 { AArch64::LD1Onev8b_POST, "ld1", ".8b", 1, false, 8 }, 471 { AArch64::LD1Onev4h_POST, "ld1", ".4h", 1, false, 8 }, 472 { AArch64::LD1Onev2s_POST, "ld1", ".2s", 1, false, 8 }, 473 { AArch64::LD1Onev1d_POST, "ld1", ".1d", 1, false, 8 }, 474 { AArch64::LD1Twov16b, "ld1", ".16b", 0, false, 0 }, 475 { AArch64::LD1Twov8h, "ld1", ".8h", 0, false, 0 }, 476 { AArch64::LD1Twov4s, "ld1", ".4s", 0, false, 0 }, 477 { AArch64::LD1Twov2d, "ld1", ".2d", 0, false, 0 }, 478 { AArch64::LD1Twov8b, "ld1", ".8b", 0, false, 0 }, 479 { AArch64::LD1Twov4h, "ld1", ".4h", 0, false, 0 }, 480 { AArch64::LD1Twov2s, "ld1", ".2s", 0, false, 0 }, 481 { AArch64::LD1Twov1d, "ld1", ".1d", 0, false, 0 }, 482 { AArch64::LD1Twov16b_POST, "ld1", ".16b", 1, false, 32 }, 483 { AArch64::LD1Twov8h_POST, "ld1", ".8h", 1, false, 32 }, 484 { AArch64::LD1Twov4s_POST, "ld1", ".4s", 1, false, 32 }, 485 { AArch64::LD1Twov2d_POST, "ld1", ".2d", 1, false, 32 }, 486 { AArch64::LD1Twov8b_POST, "ld1", ".8b", 1, false, 16 }, 487 { AArch64::LD1Twov4h_POST, "ld1", ".4h", 1, false, 16 }, 488 { AArch64::LD1Twov2s_POST, "ld1", ".2s", 1, false, 16 }, 489 { AArch64::LD1Twov1d_POST, "ld1", ".1d", 1, false, 16 }, 490 { AArch64::LD1Threev16b, "ld1", ".16b", 0, false, 0 }, 491 { AArch64::LD1Threev8h, "ld1", ".8h", 0, false, 0 }, 492 { AArch64::LD1Threev4s, "ld1", ".4s", 0, false, 0 }, 493 { AArch64::LD1Threev2d, "ld1", ".2d", 0, false, 0 }, 494 { AArch64::LD1Threev8b, "ld1", ".8b", 0, false, 0 }, 495 { AArch64::LD1Threev4h, "ld1", ".4h", 0, false, 0 }, 496 { AArch64::LD1Threev2s, "ld1", ".2s", 0, false, 0 }, 497 { AArch64::LD1Threev1d, "ld1", ".1d", 0, false, 0 }, 498 { AArch64::LD1Threev16b_POST, "ld1", ".16b", 1, false, 48 }, 499 { AArch64::LD1Threev8h_POST, "ld1", ".8h", 1, false, 48 }, 500 { AArch64::LD1Threev4s_POST, "ld1", ".4s", 1, false, 48 }, 501 { AArch64::LD1Threev2d_POST, "ld1", ".2d", 1, false, 48 }, 502 { AArch64::LD1Threev8b_POST, "ld1", ".8b", 1, false, 24 }, 503 { AArch64::LD1Threev4h_POST, "ld1", ".4h", 1, false, 24 }, 504 { AArch64::LD1Threev2s_POST, "ld1", ".2s", 1, false, 24 }, 505 { AArch64::LD1Threev1d_POST, "ld1", ".1d", 1, false, 24 }, 506 { AArch64::LD1Fourv16b, "ld1", ".16b", 0, false, 0 }, 507 { AArch64::LD1Fourv8h, "ld1", ".8h", 0, false, 0 }, 508 { AArch64::LD1Fourv4s, "ld1", ".4s", 0, false, 0 }, 509 { AArch64::LD1Fourv2d, "ld1", ".2d", 0, false, 0 }, 510 { AArch64::LD1Fourv8b, "ld1", ".8b", 0, false, 0 }, 511 { AArch64::LD1Fourv4h, "ld1", ".4h", 0, false, 0 }, 512 { AArch64::LD1Fourv2s, "ld1", ".2s", 0, false, 0 }, 513 { AArch64::LD1Fourv1d, "ld1", ".1d", 0, false, 0 }, 514 { AArch64::LD1Fourv16b_POST, "ld1", ".16b", 1, false, 64 }, 515 { AArch64::LD1Fourv8h_POST, "ld1", ".8h", 1, false, 64 }, 516 { AArch64::LD1Fourv4s_POST, "ld1", ".4s", 1, false, 64 }, 517 { AArch64::LD1Fourv2d_POST, "ld1", ".2d", 1, false, 64 }, 518 { AArch64::LD1Fourv8b_POST, "ld1", ".8b", 1, false, 32 }, 519 { AArch64::LD1Fourv4h_POST, "ld1", ".4h", 1, false, 32 }, 520 { AArch64::LD1Fourv2s_POST, "ld1", ".2s", 1, false, 32 }, 521 { AArch64::LD1Fourv1d_POST, "ld1", ".1d", 1, false, 32 }, 522 { AArch64::LD2i8, "ld2", ".b", 1, true, 0 }, 523 { AArch64::LD2i16, "ld2", ".h", 1, true, 0 }, 524 { AArch64::LD2i32, "ld2", ".s", 1, true, 0 }, 525 { AArch64::LD2i64, "ld2", ".d", 1, true, 0 }, 526 { AArch64::LD2i8_POST, "ld2", ".b", 2, true, 2 }, 527 { AArch64::LD2i16_POST, "ld2", ".h", 2, true, 4 }, 528 { AArch64::LD2i32_POST, "ld2", ".s", 2, true, 8 }, 529 { AArch64::LD2i64_POST, "ld2", ".d", 2, true, 16 }, 530 { AArch64::LD2Rv16b, "ld2r", ".16b", 0, false, 0 }, 531 { AArch64::LD2Rv8h, "ld2r", ".8h", 0, false, 0 }, 532 { AArch64::LD2Rv4s, "ld2r", ".4s", 0, false, 0 }, 533 { AArch64::LD2Rv2d, "ld2r", ".2d", 0, false, 0 }, 534 { AArch64::LD2Rv8b, "ld2r", ".8b", 0, false, 0 }, 535 { AArch64::LD2Rv4h, "ld2r", ".4h", 0, false, 0 }, 536 { AArch64::LD2Rv2s, "ld2r", ".2s", 0, false, 0 }, 537 { AArch64::LD2Rv1d, "ld2r", ".1d", 0, false, 0 }, 538 { AArch64::LD2Rv16b_POST, "ld2r", ".16b", 1, false, 2 }, 539 { AArch64::LD2Rv8h_POST, "ld2r", ".8h", 1, false, 4 }, 540 { AArch64::LD2Rv4s_POST, "ld2r", ".4s", 1, false, 8 }, 541 { AArch64::LD2Rv2d_POST, "ld2r", ".2d", 1, false, 16 }, 542 { AArch64::LD2Rv8b_POST, "ld2r", ".8b", 1, false, 2 }, 543 { AArch64::LD2Rv4h_POST, "ld2r", ".4h", 1, false, 4 }, 544 { AArch64::LD2Rv2s_POST, "ld2r", ".2s", 1, false, 8 }, 545 { AArch64::LD2Rv1d_POST, "ld2r", ".1d", 1, false, 16 }, 546 { AArch64::LD2Twov16b, "ld2", ".16b", 0, false, 0 }, 547 { AArch64::LD2Twov8h, "ld2", ".8h", 0, false, 0 }, 548 { AArch64::LD2Twov4s, "ld2", ".4s", 0, false, 0 }, 549 { AArch64::LD2Twov2d, "ld2", ".2d", 0, false, 0 }, 550 { AArch64::LD2Twov8b, "ld2", ".8b", 0, false, 0 }, 551 { AArch64::LD2Twov4h, "ld2", ".4h", 0, false, 0 }, 552 { AArch64::LD2Twov2s, "ld2", ".2s", 0, false, 0 }, 553 { AArch64::LD2Twov16b_POST, "ld2", ".16b", 1, false, 32 }, 554 { AArch64::LD2Twov8h_POST, "ld2", ".8h", 1, false, 32 }, 555 { AArch64::LD2Twov4s_POST, "ld2", ".4s", 1, false, 32 }, 556 { AArch64::LD2Twov2d_POST, "ld2", ".2d", 1, false, 32 }, 557 { AArch64::LD2Twov8b_POST, "ld2", ".8b", 1, false, 16 }, 558 { AArch64::LD2Twov4h_POST, "ld2", ".4h", 1, false, 16 }, 559 { AArch64::LD2Twov2s_POST, "ld2", ".2s", 1, false, 16 }, 560 { AArch64::LD3i8, "ld3", ".b", 1, true, 0 }, 561 { AArch64::LD3i16, "ld3", ".h", 1, true, 0 }, 562 { AArch64::LD3i32, "ld3", ".s", 1, true, 0 }, 563 { AArch64::LD3i64, "ld3", ".d", 1, true, 0 }, 564 { AArch64::LD3i8_POST, "ld3", ".b", 2, true, 3 }, 565 { AArch64::LD3i16_POST, "ld3", ".h", 2, true, 6 }, 566 { AArch64::LD3i32_POST, "ld3", ".s", 2, true, 12 }, 567 { AArch64::LD3i64_POST, "ld3", ".d", 2, true, 24 }, 568 { AArch64::LD3Rv16b, "ld3r", ".16b", 0, false, 0 }, 569 { AArch64::LD3Rv8h, "ld3r", ".8h", 0, false, 0 }, 570 { AArch64::LD3Rv4s, "ld3r", ".4s", 0, false, 0 }, 571 { AArch64::LD3Rv2d, "ld3r", ".2d", 0, false, 0 }, 572 { AArch64::LD3Rv8b, "ld3r", ".8b", 0, false, 0 }, 573 { AArch64::LD3Rv4h, "ld3r", ".4h", 0, false, 0 }, 574 { AArch64::LD3Rv2s, "ld3r", ".2s", 0, false, 0 }, 575 { AArch64::LD3Rv1d, "ld3r", ".1d", 0, false, 0 }, 576 { AArch64::LD3Rv16b_POST, "ld3r", ".16b", 1, false, 3 }, 577 { AArch64::LD3Rv8h_POST, "ld3r", ".8h", 1, false, 6 }, 578 { AArch64::LD3Rv4s_POST, "ld3r", ".4s", 1, false, 12 }, 579 { AArch64::LD3Rv2d_POST, "ld3r", ".2d", 1, false, 24 }, 580 { AArch64::LD3Rv8b_POST, "ld3r", ".8b", 1, false, 3 }, 581 { AArch64::LD3Rv4h_POST, "ld3r", ".4h", 1, false, 6 }, 582 { AArch64::LD3Rv2s_POST, "ld3r", ".2s", 1, false, 12 }, 583 { AArch64::LD3Rv1d_POST, "ld3r", ".1d", 1, false, 24 }, 584 { AArch64::LD3Threev16b, "ld3", ".16b", 0, false, 0 }, 585 { AArch64::LD3Threev8h, "ld3", ".8h", 0, false, 0 }, 586 { AArch64::LD3Threev4s, "ld3", ".4s", 0, false, 0 }, 587 { AArch64::LD3Threev2d, "ld3", ".2d", 0, false, 0 }, 588 { AArch64::LD3Threev8b, "ld3", ".8b", 0, false, 0 }, 589 { AArch64::LD3Threev4h, "ld3", ".4h", 0, false, 0 }, 590 { AArch64::LD3Threev2s, "ld3", ".2s", 0, false, 0 }, 591 { AArch64::LD3Threev16b_POST, "ld3", ".16b", 1, false, 48 }, 592 { AArch64::LD3Threev8h_POST, "ld3", ".8h", 1, false, 48 }, 593 { AArch64::LD3Threev4s_POST, "ld3", ".4s", 1, false, 48 }, 594 { AArch64::LD3Threev2d_POST, "ld3", ".2d", 1, false, 48 }, 595 { AArch64::LD3Threev8b_POST, "ld3", ".8b", 1, false, 24 }, 596 { AArch64::LD3Threev4h_POST, "ld3", ".4h", 1, false, 24 }, 597 { AArch64::LD3Threev2s_POST, "ld3", ".2s", 1, false, 24 }, 598 { AArch64::LD4i8, "ld4", ".b", 1, true, 0 }, 599 { AArch64::LD4i16, "ld4", ".h", 1, true, 0 }, 600 { AArch64::LD4i32, "ld4", ".s", 1, true, 0 }, 601 { AArch64::LD4i64, "ld4", ".d", 1, true, 0 }, 602 { AArch64::LD4i8_POST, "ld4", ".b", 2, true, 4 }, 603 { AArch64::LD4i16_POST, "ld4", ".h", 2, true, 8 }, 604 { AArch64::LD4i32_POST, "ld4", ".s", 2, true, 16 }, 605 { AArch64::LD4i64_POST, "ld4", ".d", 2, true, 32 }, 606 { AArch64::LD4Rv16b, "ld4r", ".16b", 0, false, 0 }, 607 { AArch64::LD4Rv8h, "ld4r", ".8h", 0, false, 0 }, 608 { AArch64::LD4Rv4s, "ld4r", ".4s", 0, false, 0 }, 609 { AArch64::LD4Rv2d, "ld4r", ".2d", 0, false, 0 }, 610 { AArch64::LD4Rv8b, "ld4r", ".8b", 0, false, 0 }, 611 { AArch64::LD4Rv4h, "ld4r", ".4h", 0, false, 0 }, 612 { AArch64::LD4Rv2s, "ld4r", ".2s", 0, false, 0 }, 613 { AArch64::LD4Rv1d, "ld4r", ".1d", 0, false, 0 }, 614 { AArch64::LD4Rv16b_POST, "ld4r", ".16b", 1, false, 4 }, 615 { AArch64::LD4Rv8h_POST, "ld4r", ".8h", 1, false, 8 }, 616 { AArch64::LD4Rv4s_POST, "ld4r", ".4s", 1, false, 16 }, 617 { AArch64::LD4Rv2d_POST, "ld4r", ".2d", 1, false, 32 }, 618 { AArch64::LD4Rv8b_POST, "ld4r", ".8b", 1, false, 4 }, 619 { AArch64::LD4Rv4h_POST, "ld4r", ".4h", 1, false, 8 }, 620 { AArch64::LD4Rv2s_POST, "ld4r", ".2s", 1, false, 16 }, 621 { AArch64::LD4Rv1d_POST, "ld4r", ".1d", 1, false, 32 }, 622 { AArch64::LD4Fourv16b, "ld4", ".16b", 0, false, 0 }, 623 { AArch64::LD4Fourv8h, "ld4", ".8h", 0, false, 0 }, 624 { AArch64::LD4Fourv4s, "ld4", ".4s", 0, false, 0 }, 625 { AArch64::LD4Fourv2d, "ld4", ".2d", 0, false, 0 }, 626 { AArch64::LD4Fourv8b, "ld4", ".8b", 0, false, 0 }, 627 { AArch64::LD4Fourv4h, "ld4", ".4h", 0, false, 0 }, 628 { AArch64::LD4Fourv2s, "ld4", ".2s", 0, false, 0 }, 629 { AArch64::LD4Fourv16b_POST, "ld4", ".16b", 1, false, 64 }, 630 { AArch64::LD4Fourv8h_POST, "ld4", ".8h", 1, false, 64 }, 631 { AArch64::LD4Fourv4s_POST, "ld4", ".4s", 1, false, 64 }, 632 { AArch64::LD4Fourv2d_POST, "ld4", ".2d", 1, false, 64 }, 633 { AArch64::LD4Fourv8b_POST, "ld4", ".8b", 1, false, 32 }, 634 { AArch64::LD4Fourv4h_POST, "ld4", ".4h", 1, false, 32 }, 635 { AArch64::LD4Fourv2s_POST, "ld4", ".2s", 1, false, 32 }, 636 { AArch64::ST1i8, "st1", ".b", 0, true, 0 }, 637 { AArch64::ST1i16, "st1", ".h", 0, true, 0 }, 638 { AArch64::ST1i32, "st1", ".s", 0, true, 0 }, 639 { AArch64::ST1i64, "st1", ".d", 0, true, 0 }, 640 { AArch64::ST1i8_POST, "st1", ".b", 1, true, 1 }, 641 { AArch64::ST1i16_POST, "st1", ".h", 1, true, 2 }, 642 { AArch64::ST1i32_POST, "st1", ".s", 1, true, 4 }, 643 { AArch64::ST1i64_POST, "st1", ".d", 1, true, 8 }, 644 { AArch64::ST1Onev16b, "st1", ".16b", 0, false, 0 }, 645 { AArch64::ST1Onev8h, "st1", ".8h", 0, false, 0 }, 646 { AArch64::ST1Onev4s, "st1", ".4s", 0, false, 0 }, 647 { AArch64::ST1Onev2d, "st1", ".2d", 0, false, 0 }, 648 { AArch64::ST1Onev8b, "st1", ".8b", 0, false, 0 }, 649 { AArch64::ST1Onev4h, "st1", ".4h", 0, false, 0 }, 650 { AArch64::ST1Onev2s, "st1", ".2s", 0, false, 0 }, 651 { AArch64::ST1Onev1d, "st1", ".1d", 0, false, 0 }, 652 { AArch64::ST1Onev16b_POST, "st1", ".16b", 1, false, 16 }, 653 { AArch64::ST1Onev8h_POST, "st1", ".8h", 1, false, 16 }, 654 { AArch64::ST1Onev4s_POST, "st1", ".4s", 1, false, 16 }, 655 { AArch64::ST1Onev2d_POST, "st1", ".2d", 1, false, 16 }, 656 { AArch64::ST1Onev8b_POST, "st1", ".8b", 1, false, 8 }, 657 { AArch64::ST1Onev4h_POST, "st1", ".4h", 1, false, 8 }, 658 { AArch64::ST1Onev2s_POST, "st1", ".2s", 1, false, 8 }, 659 { AArch64::ST1Onev1d_POST, "st1", ".1d", 1, false, 8 }, 660 { AArch64::ST1Twov16b, "st1", ".16b", 0, false, 0 }, 661 { AArch64::ST1Twov8h, "st1", ".8h", 0, false, 0 }, 662 { AArch64::ST1Twov4s, "st1", ".4s", 0, false, 0 }, 663 { AArch64::ST1Twov2d, "st1", ".2d", 0, false, 0 }, 664 { AArch64::ST1Twov8b, "st1", ".8b", 0, false, 0 }, 665 { AArch64::ST1Twov4h, "st1", ".4h", 0, false, 0 }, 666 { AArch64::ST1Twov2s, "st1", ".2s", 0, false, 0 }, 667 { AArch64::ST1Twov1d, "st1", ".1d", 0, false, 0 }, 668 { AArch64::ST1Twov16b_POST, "st1", ".16b", 1, false, 32 }, 669 { AArch64::ST1Twov8h_POST, "st1", ".8h", 1, false, 32 }, 670 { AArch64::ST1Twov4s_POST, "st1", ".4s", 1, false, 32 }, 671 { AArch64::ST1Twov2d_POST, "st1", ".2d", 1, false, 32 }, 672 { AArch64::ST1Twov8b_POST, "st1", ".8b", 1, false, 16 }, 673 { AArch64::ST1Twov4h_POST, "st1", ".4h", 1, false, 16 }, 674 { AArch64::ST1Twov2s_POST, "st1", ".2s", 1, false, 16 }, 675 { AArch64::ST1Twov1d_POST, "st1", ".1d", 1, false, 16 }, 676 { AArch64::ST1Threev16b, "st1", ".16b", 0, false, 0 }, 677 { AArch64::ST1Threev8h, "st1", ".8h", 0, false, 0 }, 678 { AArch64::ST1Threev4s, "st1", ".4s", 0, false, 0 }, 679 { AArch64::ST1Threev2d, "st1", ".2d", 0, false, 0 }, 680 { AArch64::ST1Threev8b, "st1", ".8b", 0, false, 0 }, 681 { AArch64::ST1Threev4h, "st1", ".4h", 0, false, 0 }, 682 { AArch64::ST1Threev2s, "st1", ".2s", 0, false, 0 }, 683 { AArch64::ST1Threev1d, "st1", ".1d", 0, false, 0 }, 684 { AArch64::ST1Threev16b_POST, "st1", ".16b", 1, false, 48 }, 685 { AArch64::ST1Threev8h_POST, "st1", ".8h", 1, false, 48 }, 686 { AArch64::ST1Threev4s_POST, "st1", ".4s", 1, false, 48 }, 687 { AArch64::ST1Threev2d_POST, "st1", ".2d", 1, false, 48 }, 688 { AArch64::ST1Threev8b_POST, "st1", ".8b", 1, false, 24 }, 689 { AArch64::ST1Threev4h_POST, "st1", ".4h", 1, false, 24 }, 690 { AArch64::ST1Threev2s_POST, "st1", ".2s", 1, false, 24 }, 691 { AArch64::ST1Threev1d_POST, "st1", ".1d", 1, false, 24 }, 692 { AArch64::ST1Fourv16b, "st1", ".16b", 0, false, 0 }, 693 { AArch64::ST1Fourv8h, "st1", ".8h", 0, false, 0 }, 694 { AArch64::ST1Fourv4s, "st1", ".4s", 0, false, 0 }, 695 { AArch64::ST1Fourv2d, "st1", ".2d", 0, false, 0 }, 696 { AArch64::ST1Fourv8b, "st1", ".8b", 0, false, 0 }, 697 { AArch64::ST1Fourv4h, "st1", ".4h", 0, false, 0 }, 698 { AArch64::ST1Fourv2s, "st1", ".2s", 0, false, 0 }, 699 { AArch64::ST1Fourv1d, "st1", ".1d", 0, false, 0 }, 700 { AArch64::ST1Fourv16b_POST, "st1", ".16b", 1, false, 64 }, 701 { AArch64::ST1Fourv8h_POST, "st1", ".8h", 1, false, 64 }, 702 { AArch64::ST1Fourv4s_POST, "st1", ".4s", 1, false, 64 }, 703 { AArch64::ST1Fourv2d_POST, "st1", ".2d", 1, false, 64 }, 704 { AArch64::ST1Fourv8b_POST, "st1", ".8b", 1, false, 32 }, 705 { AArch64::ST1Fourv4h_POST, "st1", ".4h", 1, false, 32 }, 706 { AArch64::ST1Fourv2s_POST, "st1", ".2s", 1, false, 32 }, 707 { AArch64::ST1Fourv1d_POST, "st1", ".1d", 1, false, 32 }, 708 { AArch64::ST2i8, "st2", ".b", 0, true, 0 }, 709 { AArch64::ST2i16, "st2", ".h", 0, true, 0 }, 710 { AArch64::ST2i32, "st2", ".s", 0, true, 0 }, 711 { AArch64::ST2i64, "st2", ".d", 0, true, 0 }, 712 { AArch64::ST2i8_POST, "st2", ".b", 1, true, 2 }, 713 { AArch64::ST2i16_POST, "st2", ".h", 1, true, 4 }, 714 { AArch64::ST2i32_POST, "st2", ".s", 1, true, 8 }, 715 { AArch64::ST2i64_POST, "st2", ".d", 1, true, 16 }, 716 { AArch64::ST2Twov16b, "st2", ".16b", 0, false, 0 }, 717 { AArch64::ST2Twov8h, "st2", ".8h", 0, false, 0 }, 718 { AArch64::ST2Twov4s, "st2", ".4s", 0, false, 0 }, 719 { AArch64::ST2Twov2d, "st2", ".2d", 0, false, 0 }, 720 { AArch64::ST2Twov8b, "st2", ".8b", 0, false, 0 }, 721 { AArch64::ST2Twov4h, "st2", ".4h", 0, false, 0 }, 722 { AArch64::ST2Twov2s, "st2", ".2s", 0, false, 0 }, 723 { AArch64::ST2Twov16b_POST, "st2", ".16b", 1, false, 32 }, 724 { AArch64::ST2Twov8h_POST, "st2", ".8h", 1, false, 32 }, 725 { AArch64::ST2Twov4s_POST, "st2", ".4s", 1, false, 32 }, 726 { AArch64::ST2Twov2d_POST, "st2", ".2d", 1, false, 32 }, 727 { AArch64::ST2Twov8b_POST, "st2", ".8b", 1, false, 16 }, 728 { AArch64::ST2Twov4h_POST, "st2", ".4h", 1, false, 16 }, 729 { AArch64::ST2Twov2s_POST, "st2", ".2s", 1, false, 16 }, 730 { AArch64::ST3i8, "st3", ".b", 0, true, 0 }, 731 { AArch64::ST3i16, "st3", ".h", 0, true, 0 }, 732 { AArch64::ST3i32, "st3", ".s", 0, true, 0 }, 733 { AArch64::ST3i64, "st3", ".d", 0, true, 0 }, 734 { AArch64::ST3i8_POST, "st3", ".b", 1, true, 3 }, 735 { AArch64::ST3i16_POST, "st3", ".h", 1, true, 6 }, 736 { AArch64::ST3i32_POST, "st3", ".s", 1, true, 12 }, 737 { AArch64::ST3i64_POST, "st3", ".d", 1, true, 24 }, 738 { AArch64::ST3Threev16b, "st3", ".16b", 0, false, 0 }, 739 { AArch64::ST3Threev8h, "st3", ".8h", 0, false, 0 }, 740 { AArch64::ST3Threev4s, "st3", ".4s", 0, false, 0 }, 741 { AArch64::ST3Threev2d, "st3", ".2d", 0, false, 0 }, 742 { AArch64::ST3Threev8b, "st3", ".8b", 0, false, 0 }, 743 { AArch64::ST3Threev4h, "st3", ".4h", 0, false, 0 }, 744 { AArch64::ST3Threev2s, "st3", ".2s", 0, false, 0 }, 745 { AArch64::ST3Threev16b_POST, "st3", ".16b", 1, false, 48 }, 746 { AArch64::ST3Threev8h_POST, "st3", ".8h", 1, false, 48 }, 747 { AArch64::ST3Threev4s_POST, "st3", ".4s", 1, false, 48 }, 748 { AArch64::ST3Threev2d_POST, "st3", ".2d", 1, false, 48 }, 749 { AArch64::ST3Threev8b_POST, "st3", ".8b", 1, false, 24 }, 750 { AArch64::ST3Threev4h_POST, "st3", ".4h", 1, false, 24 }, 751 { AArch64::ST3Threev2s_POST, "st3", ".2s", 1, false, 24 }, 752 { AArch64::ST4i8, "st4", ".b", 0, true, 0 }, 753 { AArch64::ST4i16, "st4", ".h", 0, true, 0 }, 754 { AArch64::ST4i32, "st4", ".s", 0, true, 0 }, 755 { AArch64::ST4i64, "st4", ".d", 0, true, 0 }, 756 { AArch64::ST4i8_POST, "st4", ".b", 1, true, 4 }, 757 { AArch64::ST4i16_POST, "st4", ".h", 1, true, 8 }, 758 { AArch64::ST4i32_POST, "st4", ".s", 1, true, 16 }, 759 { AArch64::ST4i64_POST, "st4", ".d", 1, true, 32 }, 760 { AArch64::ST4Fourv16b, "st4", ".16b", 0, false, 0 }, 761 { AArch64::ST4Fourv8h, "st4", ".8h", 0, false, 0 }, 762 { AArch64::ST4Fourv4s, "st4", ".4s", 0, false, 0 }, 763 { AArch64::ST4Fourv2d, "st4", ".2d", 0, false, 0 }, 764 { AArch64::ST4Fourv8b, "st4", ".8b", 0, false, 0 }, 765 { AArch64::ST4Fourv4h, "st4", ".4h", 0, false, 0 }, 766 { AArch64::ST4Fourv2s, "st4", ".2s", 0, false, 0 }, 767 { AArch64::ST4Fourv16b_POST, "st4", ".16b", 1, false, 64 }, 768 { AArch64::ST4Fourv8h_POST, "st4", ".8h", 1, false, 64 }, 769 { AArch64::ST4Fourv4s_POST, "st4", ".4s", 1, false, 64 }, 770 { AArch64::ST4Fourv2d_POST, "st4", ".2d", 1, false, 64 }, 771 { AArch64::ST4Fourv8b_POST, "st4", ".8b", 1, false, 32 }, 772 { AArch64::ST4Fourv4h_POST, "st4", ".4h", 1, false, 32 }, 773 { AArch64::ST4Fourv2s_POST, "st4", ".2s", 1, false, 32 }, 774 }; 775 776 static const LdStNInstrDesc *getLdStNInstrDesc(unsigned Opcode) { 777 for (const auto &Info : LdStNInstInfo) 778 if (Info.Opcode == Opcode) 779 return &Info; 780 781 return nullptr; 782 } 783 784 void AArch64AppleInstPrinter::printInst(const MCInst *MI, uint64_t Address, 785 StringRef Annot, 786 const MCSubtargetInfo &STI, 787 raw_ostream &O) { 788 unsigned Opcode = MI->getOpcode(); 789 StringRef Layout; 790 791 bool IsTbx; 792 if (isTblTbxInstruction(MI->getOpcode(), Layout, IsTbx)) { 793 O << "\t" << (IsTbx ? "tbx" : "tbl") << Layout << '\t'; 794 printRegName(O, MI->getOperand(0).getReg(), AArch64::vreg); 795 O << ", "; 796 797 unsigned ListOpNum = IsTbx ? 2 : 1; 798 printVectorList(MI, ListOpNum, STI, O, ""); 799 800 O << ", "; 801 printRegName(O, MI->getOperand(ListOpNum + 1).getReg(), AArch64::vreg); 802 printAnnotation(O, Annot); 803 return; 804 } 805 806 if (const LdStNInstrDesc *LdStDesc = getLdStNInstrDesc(Opcode)) { 807 O << "\t" << LdStDesc->Mnemonic << LdStDesc->Layout << '\t'; 808 809 // Now onto the operands: first a vector list with possible lane 810 // specifier. E.g. { v0 }[2] 811 int OpNum = LdStDesc->ListOperand; 812 printVectorList(MI, OpNum++, STI, O, ""); 813 814 if (LdStDesc->HasLane) 815 O << '[' << MI->getOperand(OpNum++).getImm() << ']'; 816 817 // Next the address: [xN] 818 unsigned AddrReg = MI->getOperand(OpNum++).getReg(); 819 O << ", ["; 820 printRegName(O, AddrReg); 821 O << ']'; 822 823 // Finally, there might be a post-indexed offset. 824 if (LdStDesc->NaturalOffset != 0) { 825 unsigned Reg = MI->getOperand(OpNum++).getReg(); 826 if (Reg != AArch64::XZR) { 827 O << ", "; 828 printRegName(O, Reg); 829 } else { 830 assert(LdStDesc->NaturalOffset && "no offset on post-inc instruction?"); 831 O << ", "; 832 markup(O, Markup::Immediate) << "#" << LdStDesc->NaturalOffset; 833 } 834 } 835 836 printAnnotation(O, Annot); 837 return; 838 } 839 840 AArch64InstPrinter::printInst(MI, Address, Annot, STI, O); 841 } 842 843 StringRef AArch64AppleInstPrinter::getRegName(MCRegister Reg) const { 844 return getRegisterName(Reg); 845 } 846 847 bool AArch64InstPrinter::printRangePrefetchAlias(const MCInst *MI, 848 const MCSubtargetInfo &STI, 849 raw_ostream &O, 850 StringRef Annot) { 851 unsigned Opcode = MI->getOpcode(); 852 853 #ifndef NDEBUG 854 assert(((Opcode == AArch64::PRFMroX) || (Opcode == AArch64::PRFMroW)) && 855 "Invalid opcode for RPRFM alias!"); 856 #endif 857 858 unsigned PRFOp = MI->getOperand(0).getImm(); 859 unsigned Mask = 0x18; // 0b11000 860 if ((PRFOp & Mask) != Mask) 861 return false; // Rt != '11xxx', it's a PRFM instruction. 862 863 unsigned Rm = MI->getOperand(2).getReg(); 864 865 // "Rm" must be a 64-bit GPR for RPRFM. 866 if (MRI.getRegClass(AArch64::GPR32RegClassID).contains(Rm)) 867 Rm = MRI.getMatchingSuperReg(Rm, AArch64::sub_32, 868 &MRI.getRegClass(AArch64::GPR64RegClassID)); 869 870 unsigned SignExtend = MI->getOperand(3).getImm(); // encoded in "option<2>". 871 unsigned Shift = MI->getOperand(4).getImm(); // encoded in "S". 872 873 assert((SignExtend <= 1) && "sign extend should be a single bit!"); 874 assert((Shift <= 1) && "Shift should be a single bit!"); 875 876 unsigned Option0 = (Opcode == AArch64::PRFMroX) ? 1 : 0; 877 878 // encoded in "option<2>:option<0>:S:Rt<2:0>". 879 unsigned RPRFOp = 880 (SignExtend << 5) | (Option0 << 4) | (Shift << 3) | (PRFOp & 0x7); 881 882 O << "\trprfm "; 883 if (auto RPRFM = AArch64RPRFM::lookupRPRFMByEncoding(RPRFOp)) 884 O << RPRFM->Name << ", "; 885 else 886 O << "#" << formatImm(RPRFOp) << ", "; 887 O << getRegisterName(Rm); 888 O << ", ["; 889 printOperand(MI, 1, STI, O); // "Rn". 890 O << "]"; 891 892 printAnnotation(O, Annot); 893 894 return true; 895 } 896 897 bool AArch64InstPrinter::printSysAlias(const MCInst *MI, 898 const MCSubtargetInfo &STI, 899 raw_ostream &O) { 900 #ifndef NDEBUG 901 unsigned Opcode = MI->getOpcode(); 902 assert(Opcode == AArch64::SYSxt && "Invalid opcode for SYS alias!"); 903 #endif 904 905 const MCOperand &Op1 = MI->getOperand(0); 906 const MCOperand &Cn = MI->getOperand(1); 907 const MCOperand &Cm = MI->getOperand(2); 908 const MCOperand &Op2 = MI->getOperand(3); 909 910 unsigned Op1Val = Op1.getImm(); 911 unsigned CnVal = Cn.getImm(); 912 unsigned CmVal = Cm.getImm(); 913 unsigned Op2Val = Op2.getImm(); 914 915 uint16_t Encoding = Op2Val; 916 Encoding |= CmVal << 3; 917 Encoding |= CnVal << 7; 918 Encoding |= Op1Val << 11; 919 920 bool NeedsReg; 921 std::string Ins; 922 std::string Name; 923 924 if (CnVal == 7) { 925 switch (CmVal) { 926 default: return false; 927 // Maybe IC, maybe Prediction Restriction 928 case 1: 929 switch (Op1Val) { 930 default: return false; 931 case 0: goto Search_IC; 932 case 3: goto Search_PRCTX; 933 } 934 // Prediction Restriction aliases 935 case 3: { 936 Search_PRCTX: 937 if (Op1Val != 3 || CnVal != 7 || CmVal != 3) 938 return false; 939 940 const auto Requires = 941 Op2Val == 6 ? AArch64::FeatureSPECRES2 : AArch64::FeaturePredRes; 942 if (!(STI.hasFeature(AArch64::FeatureAll) || STI.hasFeature(Requires))) 943 return false; 944 945 NeedsReg = true; 946 switch (Op2Val) { 947 default: return false; 948 case 4: Ins = "cfp\t"; break; 949 case 5: Ins = "dvp\t"; break; 950 case 6: Ins = "cosp\t"; break; 951 case 7: Ins = "cpp\t"; break; 952 } 953 Name = "RCTX"; 954 } 955 break; 956 // IC aliases 957 case 5: { 958 Search_IC: 959 const AArch64IC::IC *IC = AArch64IC::lookupICByEncoding(Encoding); 960 if (!IC || !IC->haveFeatures(STI.getFeatureBits())) 961 return false; 962 963 NeedsReg = IC->NeedsReg; 964 Ins = "ic\t"; 965 Name = std::string(IC->Name); 966 } 967 break; 968 // DC aliases 969 case 4: case 6: case 10: case 11: case 12: case 13: case 14: 970 { 971 const AArch64DC::DC *DC = AArch64DC::lookupDCByEncoding(Encoding); 972 if (!DC || !DC->haveFeatures(STI.getFeatureBits())) 973 return false; 974 975 NeedsReg = true; 976 Ins = "dc\t"; 977 Name = std::string(DC->Name); 978 } 979 break; 980 // AT aliases 981 case 8: case 9: { 982 const AArch64AT::AT *AT = AArch64AT::lookupATByEncoding(Encoding); 983 if (!AT || !AT->haveFeatures(STI.getFeatureBits())) 984 return false; 985 986 NeedsReg = true; 987 Ins = "at\t"; 988 Name = std::string(AT->Name); 989 } 990 break; 991 } 992 } else if (CnVal == 8 || CnVal == 9) { 993 // TLBI aliases 994 const AArch64TLBI::TLBI *TLBI = AArch64TLBI::lookupTLBIByEncoding(Encoding); 995 if (!TLBI || !TLBI->haveFeatures(STI.getFeatureBits())) 996 return false; 997 998 NeedsReg = TLBI->NeedsReg; 999 Ins = "tlbi\t"; 1000 Name = std::string(TLBI->Name); 1001 } 1002 else 1003 return false; 1004 1005 std::string Str = Ins + Name; 1006 std::transform(Str.begin(), Str.end(), Str.begin(), ::tolower); 1007 1008 O << '\t' << Str; 1009 if (NeedsReg) { 1010 O << ", "; 1011 printRegName(O, MI->getOperand(4).getReg()); 1012 } 1013 1014 return true; 1015 } 1016 1017 bool AArch64InstPrinter::printSyspAlias(const MCInst *MI, 1018 const MCSubtargetInfo &STI, 1019 raw_ostream &O) { 1020 #ifndef NDEBUG 1021 unsigned Opcode = MI->getOpcode(); 1022 assert((Opcode == AArch64::SYSPxt || Opcode == AArch64::SYSPxt_XZR) && 1023 "Invalid opcode for SYSP alias!"); 1024 #endif 1025 1026 const MCOperand &Op1 = MI->getOperand(0); 1027 const MCOperand &Cn = MI->getOperand(1); 1028 const MCOperand &Cm = MI->getOperand(2); 1029 const MCOperand &Op2 = MI->getOperand(3); 1030 1031 unsigned Op1Val = Op1.getImm(); 1032 unsigned CnVal = Cn.getImm(); 1033 unsigned CmVal = Cm.getImm(); 1034 unsigned Op2Val = Op2.getImm(); 1035 1036 uint16_t Encoding = Op2Val; 1037 Encoding |= CmVal << 3; 1038 Encoding |= CnVal << 7; 1039 Encoding |= Op1Val << 11; 1040 1041 std::string Ins; 1042 std::string Name; 1043 1044 if (CnVal == 8 || CnVal == 9) { 1045 // TLBIP aliases 1046 1047 if (CnVal == 9) { 1048 if (!STI.hasFeature(AArch64::FeatureXS)) 1049 return false; 1050 Encoding &= ~(1 << 7); 1051 } 1052 1053 const AArch64TLBI::TLBI *TLBI = AArch64TLBI::lookupTLBIByEncoding(Encoding); 1054 if (!TLBI || !TLBI->haveFeatures(STI.getFeatureBits())) 1055 return false; 1056 1057 Ins = "tlbip\t"; 1058 Name = std::string(TLBI->Name); 1059 if (CnVal == 9) 1060 Name += "nXS"; 1061 } else 1062 return false; 1063 1064 std::string Str = Ins + Name; 1065 std::transform(Str.begin(), Str.end(), Str.begin(), ::tolower); 1066 1067 O << '\t' << Str; 1068 O << ", "; 1069 if (MI->getOperand(4).getReg() == AArch64::XZR) 1070 printSyspXzrPair(MI, 4, STI, O); 1071 else 1072 printGPRSeqPairsClassOperand<64>(MI, 4, STI, O); 1073 1074 return true; 1075 } 1076 1077 template <int EltSize> 1078 void AArch64InstPrinter::printMatrix(const MCInst *MI, unsigned OpNum, 1079 const MCSubtargetInfo &STI, 1080 raw_ostream &O) { 1081 const MCOperand &RegOp = MI->getOperand(OpNum); 1082 assert(RegOp.isReg() && "Unexpected operand type!"); 1083 1084 printRegName(O, RegOp.getReg()); 1085 switch (EltSize) { 1086 case 0: 1087 break; 1088 case 8: 1089 O << ".b"; 1090 break; 1091 case 16: 1092 O << ".h"; 1093 break; 1094 case 32: 1095 O << ".s"; 1096 break; 1097 case 64: 1098 O << ".d"; 1099 break; 1100 case 128: 1101 O << ".q"; 1102 break; 1103 default: 1104 llvm_unreachable("Unsupported element size"); 1105 } 1106 } 1107 1108 template <bool IsVertical> 1109 void AArch64InstPrinter::printMatrixTileVector(const MCInst *MI, unsigned OpNum, 1110 const MCSubtargetInfo &STI, 1111 raw_ostream &O) { 1112 const MCOperand &RegOp = MI->getOperand(OpNum); 1113 assert(RegOp.isReg() && "Unexpected operand type!"); 1114 StringRef RegName = getRegisterName(RegOp.getReg()); 1115 1116 // Insert the horizontal/vertical flag before the suffix. 1117 StringRef Base, Suffix; 1118 std::tie(Base, Suffix) = RegName.split('.'); 1119 O << Base << (IsVertical ? "v" : "h") << '.' << Suffix; 1120 } 1121 1122 void AArch64InstPrinter::printMatrixTile(const MCInst *MI, unsigned OpNum, 1123 const MCSubtargetInfo &STI, 1124 raw_ostream &O) { 1125 const MCOperand &RegOp = MI->getOperand(OpNum); 1126 assert(RegOp.isReg() && "Unexpected operand type!"); 1127 printRegName(O, RegOp.getReg()); 1128 } 1129 1130 void AArch64InstPrinter::printSVCROp(const MCInst *MI, unsigned OpNum, 1131 const MCSubtargetInfo &STI, 1132 raw_ostream &O) { 1133 const MCOperand &MO = MI->getOperand(OpNum); 1134 assert(MO.isImm() && "Unexpected operand type!"); 1135 unsigned svcrop = MO.getImm(); 1136 const auto *SVCR = AArch64SVCR::lookupSVCRByEncoding(svcrop); 1137 assert(SVCR && "Unexpected SVCR operand!"); 1138 O << SVCR->Name; 1139 } 1140 1141 void AArch64InstPrinter::printOperand(const MCInst *MI, unsigned OpNo, 1142 const MCSubtargetInfo &STI, 1143 raw_ostream &O) { 1144 const MCOperand &Op = MI->getOperand(OpNo); 1145 if (Op.isReg()) { 1146 unsigned Reg = Op.getReg(); 1147 printRegName(O, Reg); 1148 } else if (Op.isImm()) { 1149 printImm(MI, OpNo, STI, O); 1150 } else { 1151 assert(Op.isExpr() && "unknown operand kind in printOperand"); 1152 Op.getExpr()->print(O, &MAI); 1153 } 1154 } 1155 1156 void AArch64InstPrinter::printImm(const MCInst *MI, unsigned OpNo, 1157 const MCSubtargetInfo &STI, 1158 raw_ostream &O) { 1159 const MCOperand &Op = MI->getOperand(OpNo); 1160 markup(O, Markup::Immediate) << "#" << formatImm(Op.getImm()); 1161 } 1162 1163 void AArch64InstPrinter::printImmHex(const MCInst *MI, unsigned OpNo, 1164 const MCSubtargetInfo &STI, 1165 raw_ostream &O) { 1166 const MCOperand &Op = MI->getOperand(OpNo); 1167 markup(O, Markup::Immediate) << format("#%#llx", Op.getImm()); 1168 } 1169 1170 template<int Size> 1171 void AArch64InstPrinter::printSImm(const MCInst *MI, unsigned OpNo, 1172 const MCSubtargetInfo &STI, 1173 raw_ostream &O) { 1174 const MCOperand &Op = MI->getOperand(OpNo); 1175 if (Size == 8) 1176 markup(O, Markup::Immediate) << "#" << formatImm((signed char)Op.getImm()); 1177 else if (Size == 16) 1178 markup(O, Markup::Immediate) << "#" << formatImm((signed short)Op.getImm()); 1179 else 1180 markup(O, Markup::Immediate) << "#" << formatImm(Op.getImm()); 1181 } 1182 1183 void AArch64InstPrinter::printPostIncOperand(const MCInst *MI, unsigned OpNo, 1184 unsigned Imm, raw_ostream &O) { 1185 const MCOperand &Op = MI->getOperand(OpNo); 1186 if (Op.isReg()) { 1187 unsigned Reg = Op.getReg(); 1188 if (Reg == AArch64::XZR) 1189 markup(O, Markup::Immediate) << "#" << Imm; 1190 else 1191 printRegName(O, Reg); 1192 } else 1193 llvm_unreachable("unknown operand kind in printPostIncOperand64"); 1194 } 1195 1196 void AArch64InstPrinter::printVRegOperand(const MCInst *MI, unsigned OpNo, 1197 const MCSubtargetInfo &STI, 1198 raw_ostream &O) { 1199 const MCOperand &Op = MI->getOperand(OpNo); 1200 assert(Op.isReg() && "Non-register vreg operand!"); 1201 unsigned Reg = Op.getReg(); 1202 printRegName(O, Reg, AArch64::vreg); 1203 } 1204 1205 void AArch64InstPrinter::printSysCROperand(const MCInst *MI, unsigned OpNo, 1206 const MCSubtargetInfo &STI, 1207 raw_ostream &O) { 1208 const MCOperand &Op = MI->getOperand(OpNo); 1209 assert(Op.isImm() && "System instruction C[nm] operands must be immediates!"); 1210 O << "c" << Op.getImm(); 1211 } 1212 1213 void AArch64InstPrinter::printAddSubImm(const MCInst *MI, unsigned OpNum, 1214 const MCSubtargetInfo &STI, 1215 raw_ostream &O) { 1216 const MCOperand &MO = MI->getOperand(OpNum); 1217 if (MO.isImm()) { 1218 unsigned Val = (MO.getImm() & 0xfff); 1219 assert(Val == MO.getImm() && "Add/sub immediate out of range!"); 1220 unsigned Shift = 1221 AArch64_AM::getShiftValue(MI->getOperand(OpNum + 1).getImm()); 1222 markup(O, Markup::Immediate) << '#' << formatImm(Val); 1223 if (Shift != 0) { 1224 printShifter(MI, OpNum + 1, STI, O); 1225 if (CommentStream) 1226 *CommentStream << '=' << formatImm(Val << Shift) << '\n'; 1227 } 1228 } else { 1229 assert(MO.isExpr() && "Unexpected operand type!"); 1230 MO.getExpr()->print(O, &MAI); 1231 printShifter(MI, OpNum + 1, STI, O); 1232 } 1233 } 1234 1235 template <typename T> 1236 void AArch64InstPrinter::printLogicalImm(const MCInst *MI, unsigned OpNum, 1237 const MCSubtargetInfo &STI, 1238 raw_ostream &O) { 1239 uint64_t Val = MI->getOperand(OpNum).getImm(); 1240 WithMarkup M = markup(O, Markup::Immediate); 1241 O << "#0x"; 1242 O.write_hex(AArch64_AM::decodeLogicalImmediate(Val, 8 * sizeof(T))); 1243 } 1244 1245 void AArch64InstPrinter::printShifter(const MCInst *MI, unsigned OpNum, 1246 const MCSubtargetInfo &STI, 1247 raw_ostream &O) { 1248 unsigned Val = MI->getOperand(OpNum).getImm(); 1249 // LSL #0 should not be printed. 1250 if (AArch64_AM::getShiftType(Val) == AArch64_AM::LSL && 1251 AArch64_AM::getShiftValue(Val) == 0) 1252 return; 1253 O << ", " << AArch64_AM::getShiftExtendName(AArch64_AM::getShiftType(Val)) 1254 << " "; 1255 markup(O, Markup::Immediate) << "#" << AArch64_AM::getShiftValue(Val); 1256 } 1257 1258 void AArch64InstPrinter::printShiftedRegister(const MCInst *MI, unsigned OpNum, 1259 const MCSubtargetInfo &STI, 1260 raw_ostream &O) { 1261 printRegName(O, MI->getOperand(OpNum).getReg()); 1262 printShifter(MI, OpNum + 1, STI, O); 1263 } 1264 1265 void AArch64InstPrinter::printExtendedRegister(const MCInst *MI, unsigned OpNum, 1266 const MCSubtargetInfo &STI, 1267 raw_ostream &O) { 1268 printRegName(O, MI->getOperand(OpNum).getReg()); 1269 printArithExtend(MI, OpNum + 1, STI, O); 1270 } 1271 1272 void AArch64InstPrinter::printArithExtend(const MCInst *MI, unsigned OpNum, 1273 const MCSubtargetInfo &STI, 1274 raw_ostream &O) { 1275 unsigned Val = MI->getOperand(OpNum).getImm(); 1276 AArch64_AM::ShiftExtendType ExtType = AArch64_AM::getArithExtendType(Val); 1277 unsigned ShiftVal = AArch64_AM::getArithShiftValue(Val); 1278 1279 // If the destination or first source register operand is [W]SP, print 1280 // UXTW/UXTX as LSL, and if the shift amount is also zero, print nothing at 1281 // all. 1282 if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) { 1283 unsigned Dest = MI->getOperand(0).getReg(); 1284 unsigned Src1 = MI->getOperand(1).getReg(); 1285 if ( ((Dest == AArch64::SP || Src1 == AArch64::SP) && 1286 ExtType == AArch64_AM::UXTX) || 1287 ((Dest == AArch64::WSP || Src1 == AArch64::WSP) && 1288 ExtType == AArch64_AM::UXTW) ) { 1289 if (ShiftVal != 0) { 1290 O << ", lsl "; 1291 markup(O, Markup::Immediate) << "#" << ShiftVal; 1292 } 1293 return; 1294 } 1295 } 1296 O << ", " << AArch64_AM::getShiftExtendName(ExtType); 1297 if (ShiftVal != 0) { 1298 O << " "; 1299 markup(O, Markup::Immediate) << "#" << ShiftVal; 1300 } 1301 } 1302 1303 void AArch64InstPrinter::printMemExtendImpl(bool SignExtend, bool DoShift, 1304 unsigned Width, char SrcRegKind, 1305 raw_ostream &O) { 1306 // sxtw, sxtx, uxtw or lsl (== uxtx) 1307 bool IsLSL = !SignExtend && SrcRegKind == 'x'; 1308 if (IsLSL) 1309 O << "lsl"; 1310 else 1311 O << (SignExtend ? 's' : 'u') << "xt" << SrcRegKind; 1312 1313 if (DoShift || IsLSL) { 1314 O << " "; 1315 markup(O, Markup::Immediate) << "#" << Log2_32(Width / 8); 1316 } 1317 } 1318 1319 void AArch64InstPrinter::printMemExtend(const MCInst *MI, unsigned OpNum, 1320 raw_ostream &O, char SrcRegKind, 1321 unsigned Width) { 1322 bool SignExtend = MI->getOperand(OpNum).getImm(); 1323 bool DoShift = MI->getOperand(OpNum + 1).getImm(); 1324 printMemExtendImpl(SignExtend, DoShift, Width, SrcRegKind, O); 1325 } 1326 1327 template <bool SignExtend, int ExtWidth, char SrcRegKind, char Suffix> 1328 void AArch64InstPrinter::printRegWithShiftExtend(const MCInst *MI, 1329 unsigned OpNum, 1330 const MCSubtargetInfo &STI, 1331 raw_ostream &O) { 1332 printOperand(MI, OpNum, STI, O); 1333 if (Suffix == 's' || Suffix == 'd') 1334 O << '.' << Suffix; 1335 else 1336 assert(Suffix == 0 && "Unsupported suffix size"); 1337 1338 bool DoShift = ExtWidth != 8; 1339 if (SignExtend || DoShift || SrcRegKind == 'w') { 1340 O << ", "; 1341 printMemExtendImpl(SignExtend, DoShift, ExtWidth, SrcRegKind, O); 1342 } 1343 } 1344 1345 template <int EltSize> 1346 void AArch64InstPrinter::printPredicateAsCounter(const MCInst *MI, 1347 unsigned OpNum, 1348 const MCSubtargetInfo &STI, 1349 raw_ostream &O) { 1350 unsigned Reg = MI->getOperand(OpNum).getReg(); 1351 if (Reg < AArch64::PN0 || Reg > AArch64::PN15) 1352 llvm_unreachable("Unsupported predicate-as-counter register"); 1353 O << "pn" << Reg - AArch64::PN0; 1354 1355 switch (EltSize) { 1356 case 0: 1357 break; 1358 case 8: 1359 O << ".b"; 1360 break; 1361 case 16: 1362 O << ".h"; 1363 break; 1364 case 32: 1365 O << ".s"; 1366 break; 1367 case 64: 1368 O << ".d"; 1369 break; 1370 default: 1371 llvm_unreachable("Unsupported element size"); 1372 } 1373 } 1374 1375 void AArch64InstPrinter::printCondCode(const MCInst *MI, unsigned OpNum, 1376 const MCSubtargetInfo &STI, 1377 raw_ostream &O) { 1378 AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(OpNum).getImm(); 1379 O << AArch64CC::getCondCodeName(CC); 1380 } 1381 1382 void AArch64InstPrinter::printInverseCondCode(const MCInst *MI, unsigned OpNum, 1383 const MCSubtargetInfo &STI, 1384 raw_ostream &O) { 1385 AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(OpNum).getImm(); 1386 O << AArch64CC::getCondCodeName(AArch64CC::getInvertedCondCode(CC)); 1387 } 1388 1389 void AArch64InstPrinter::printAMNoIndex(const MCInst *MI, unsigned OpNum, 1390 const MCSubtargetInfo &STI, 1391 raw_ostream &O) { 1392 O << '['; 1393 printRegName(O, MI->getOperand(OpNum).getReg()); 1394 O << ']'; 1395 } 1396 1397 template <int Scale> 1398 void AArch64InstPrinter::printImmScale(const MCInst *MI, unsigned OpNum, 1399 const MCSubtargetInfo &STI, 1400 raw_ostream &O) { 1401 markup(O, Markup::Immediate) 1402 << '#' << formatImm(Scale * MI->getOperand(OpNum).getImm()); 1403 } 1404 1405 template <int Scale, int Offset> 1406 void AArch64InstPrinter::printImmRangeScale(const MCInst *MI, unsigned OpNum, 1407 const MCSubtargetInfo &STI, 1408 raw_ostream &O) { 1409 unsigned FirstImm = Scale * MI->getOperand(OpNum).getImm(); 1410 O << formatImm(FirstImm); 1411 O << ":" << formatImm(FirstImm + Offset); 1412 } 1413 1414 void AArch64InstPrinter::printUImm12Offset(const MCInst *MI, unsigned OpNum, 1415 unsigned Scale, raw_ostream &O) { 1416 const MCOperand MO = MI->getOperand(OpNum); 1417 if (MO.isImm()) { 1418 markup(O, Markup::Immediate) << '#' << formatImm(MO.getImm() * Scale); 1419 } else { 1420 assert(MO.isExpr() && "Unexpected operand type!"); 1421 MO.getExpr()->print(O, &MAI); 1422 } 1423 } 1424 1425 void AArch64InstPrinter::printAMIndexedWB(const MCInst *MI, unsigned OpNum, 1426 unsigned Scale, raw_ostream &O) { 1427 const MCOperand MO1 = MI->getOperand(OpNum + 1); 1428 O << '['; 1429 printRegName(O, MI->getOperand(OpNum).getReg()); 1430 if (MO1.isImm()) { 1431 O << ", "; 1432 markup(O, Markup::Immediate) << "#" << formatImm(MO1.getImm() * Scale); 1433 } else { 1434 assert(MO1.isExpr() && "Unexpected operand type!"); 1435 O << ", "; 1436 MO1.getExpr()->print(O, &MAI); 1437 } 1438 O << ']'; 1439 } 1440 1441 void AArch64InstPrinter::printRPRFMOperand(const MCInst *MI, unsigned OpNum, 1442 const MCSubtargetInfo &STI, 1443 raw_ostream &O) { 1444 unsigned prfop = MI->getOperand(OpNum).getImm(); 1445 if (auto PRFM = AArch64RPRFM::lookupRPRFMByEncoding(prfop)) { 1446 O << PRFM->Name; 1447 return; 1448 } 1449 1450 O << '#' << formatImm(prfop); 1451 } 1452 1453 template <bool IsSVEPrefetch> 1454 void AArch64InstPrinter::printPrefetchOp(const MCInst *MI, unsigned OpNum, 1455 const MCSubtargetInfo &STI, 1456 raw_ostream &O) { 1457 unsigned prfop = MI->getOperand(OpNum).getImm(); 1458 if (IsSVEPrefetch) { 1459 if (auto PRFM = AArch64SVEPRFM::lookupSVEPRFMByEncoding(prfop)) { 1460 O << PRFM->Name; 1461 return; 1462 } 1463 } else { 1464 auto PRFM = AArch64PRFM::lookupPRFMByEncoding(prfop); 1465 if (PRFM && PRFM->haveFeatures(STI.getFeatureBits())) { 1466 O << PRFM->Name; 1467 return; 1468 } 1469 } 1470 1471 markup(O, Markup::Immediate) << '#' << formatImm(prfop); 1472 } 1473 1474 void AArch64InstPrinter::printPSBHintOp(const MCInst *MI, unsigned OpNum, 1475 const MCSubtargetInfo &STI, 1476 raw_ostream &O) { 1477 unsigned psbhintop = MI->getOperand(OpNum).getImm(); 1478 auto PSB = AArch64PSBHint::lookupPSBByEncoding(psbhintop); 1479 if (PSB) 1480 O << PSB->Name; 1481 else 1482 markup(O, Markup::Immediate) << '#' << formatImm(psbhintop); 1483 } 1484 1485 void AArch64InstPrinter::printBTIHintOp(const MCInst *MI, unsigned OpNum, 1486 const MCSubtargetInfo &STI, 1487 raw_ostream &O) { 1488 unsigned btihintop = MI->getOperand(OpNum).getImm() ^ 32; 1489 auto BTI = AArch64BTIHint::lookupBTIByEncoding(btihintop); 1490 if (BTI) 1491 O << BTI->Name; 1492 else 1493 markup(O, Markup::Immediate) << '#' << formatImm(btihintop); 1494 } 1495 1496 void AArch64InstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum, 1497 const MCSubtargetInfo &STI, 1498 raw_ostream &O) { 1499 const MCOperand &MO = MI->getOperand(OpNum); 1500 float FPImm = MO.isDFPImm() ? bit_cast<double>(MO.getDFPImm()) 1501 : AArch64_AM::getFPImmFloat(MO.getImm()); 1502 1503 // 8 decimal places are enough to perfectly represent permitted floats. 1504 markup(O, Markup::Immediate) << format("#%.8f", FPImm); 1505 } 1506 1507 static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride = 1) { 1508 while (Stride--) { 1509 switch (Reg) { 1510 default: 1511 llvm_unreachable("Vector register expected!"); 1512 case AArch64::Q0: Reg = AArch64::Q1; break; 1513 case AArch64::Q1: Reg = AArch64::Q2; break; 1514 case AArch64::Q2: Reg = AArch64::Q3; break; 1515 case AArch64::Q3: Reg = AArch64::Q4; break; 1516 case AArch64::Q4: Reg = AArch64::Q5; break; 1517 case AArch64::Q5: Reg = AArch64::Q6; break; 1518 case AArch64::Q6: Reg = AArch64::Q7; break; 1519 case AArch64::Q7: Reg = AArch64::Q8; break; 1520 case AArch64::Q8: Reg = AArch64::Q9; break; 1521 case AArch64::Q9: Reg = AArch64::Q10; break; 1522 case AArch64::Q10: Reg = AArch64::Q11; break; 1523 case AArch64::Q11: Reg = AArch64::Q12; break; 1524 case AArch64::Q12: Reg = AArch64::Q13; break; 1525 case AArch64::Q13: Reg = AArch64::Q14; break; 1526 case AArch64::Q14: Reg = AArch64::Q15; break; 1527 case AArch64::Q15: Reg = AArch64::Q16; break; 1528 case AArch64::Q16: Reg = AArch64::Q17; break; 1529 case AArch64::Q17: Reg = AArch64::Q18; break; 1530 case AArch64::Q18: Reg = AArch64::Q19; break; 1531 case AArch64::Q19: Reg = AArch64::Q20; break; 1532 case AArch64::Q20: Reg = AArch64::Q21; break; 1533 case AArch64::Q21: Reg = AArch64::Q22; break; 1534 case AArch64::Q22: Reg = AArch64::Q23; break; 1535 case AArch64::Q23: Reg = AArch64::Q24; break; 1536 case AArch64::Q24: Reg = AArch64::Q25; break; 1537 case AArch64::Q25: Reg = AArch64::Q26; break; 1538 case AArch64::Q26: Reg = AArch64::Q27; break; 1539 case AArch64::Q27: Reg = AArch64::Q28; break; 1540 case AArch64::Q28: Reg = AArch64::Q29; break; 1541 case AArch64::Q29: Reg = AArch64::Q30; break; 1542 case AArch64::Q30: Reg = AArch64::Q31; break; 1543 // Vector lists can wrap around. 1544 case AArch64::Q31: 1545 Reg = AArch64::Q0; 1546 break; 1547 case AArch64::Z0: Reg = AArch64::Z1; break; 1548 case AArch64::Z1: Reg = AArch64::Z2; break; 1549 case AArch64::Z2: Reg = AArch64::Z3; break; 1550 case AArch64::Z3: Reg = AArch64::Z4; break; 1551 case AArch64::Z4: Reg = AArch64::Z5; break; 1552 case AArch64::Z5: Reg = AArch64::Z6; break; 1553 case AArch64::Z6: Reg = AArch64::Z7; break; 1554 case AArch64::Z7: Reg = AArch64::Z8; break; 1555 case AArch64::Z8: Reg = AArch64::Z9; break; 1556 case AArch64::Z9: Reg = AArch64::Z10; break; 1557 case AArch64::Z10: Reg = AArch64::Z11; break; 1558 case AArch64::Z11: Reg = AArch64::Z12; break; 1559 case AArch64::Z12: Reg = AArch64::Z13; break; 1560 case AArch64::Z13: Reg = AArch64::Z14; break; 1561 case AArch64::Z14: Reg = AArch64::Z15; break; 1562 case AArch64::Z15: Reg = AArch64::Z16; break; 1563 case AArch64::Z16: Reg = AArch64::Z17; break; 1564 case AArch64::Z17: Reg = AArch64::Z18; break; 1565 case AArch64::Z18: Reg = AArch64::Z19; break; 1566 case AArch64::Z19: Reg = AArch64::Z20; break; 1567 case AArch64::Z20: Reg = AArch64::Z21; break; 1568 case AArch64::Z21: Reg = AArch64::Z22; break; 1569 case AArch64::Z22: Reg = AArch64::Z23; break; 1570 case AArch64::Z23: Reg = AArch64::Z24; break; 1571 case AArch64::Z24: Reg = AArch64::Z25; break; 1572 case AArch64::Z25: Reg = AArch64::Z26; break; 1573 case AArch64::Z26: Reg = AArch64::Z27; break; 1574 case AArch64::Z27: Reg = AArch64::Z28; break; 1575 case AArch64::Z28: Reg = AArch64::Z29; break; 1576 case AArch64::Z29: Reg = AArch64::Z30; break; 1577 case AArch64::Z30: Reg = AArch64::Z31; break; 1578 // Vector lists can wrap around. 1579 case AArch64::Z31: 1580 Reg = AArch64::Z0; 1581 break; 1582 case AArch64::P0: Reg = AArch64::P1; break; 1583 case AArch64::P1: Reg = AArch64::P2; break; 1584 case AArch64::P2: Reg = AArch64::P3; break; 1585 case AArch64::P3: Reg = AArch64::P4; break; 1586 case AArch64::P4: Reg = AArch64::P5; break; 1587 case AArch64::P5: Reg = AArch64::P6; break; 1588 case AArch64::P6: Reg = AArch64::P7; break; 1589 case AArch64::P7: Reg = AArch64::P8; break; 1590 case AArch64::P8: Reg = AArch64::P9; break; 1591 case AArch64::P9: Reg = AArch64::P10; break; 1592 case AArch64::P10: Reg = AArch64::P11; break; 1593 case AArch64::P11: Reg = AArch64::P12; break; 1594 case AArch64::P12: Reg = AArch64::P13; break; 1595 case AArch64::P13: Reg = AArch64::P14; break; 1596 case AArch64::P14: Reg = AArch64::P15; break; 1597 // Vector lists can wrap around. 1598 case AArch64::P15: Reg = AArch64::P0; break; 1599 } 1600 } 1601 return Reg; 1602 } 1603 1604 template<unsigned size> 1605 void AArch64InstPrinter::printGPRSeqPairsClassOperand(const MCInst *MI, 1606 unsigned OpNum, 1607 const MCSubtargetInfo &STI, 1608 raw_ostream &O) { 1609 static_assert(size == 64 || size == 32, 1610 "Template parameter must be either 32 or 64"); 1611 unsigned Reg = MI->getOperand(OpNum).getReg(); 1612 1613 unsigned Sube = (size == 32) ? AArch64::sube32 : AArch64::sube64; 1614 unsigned Subo = (size == 32) ? AArch64::subo32 : AArch64::subo64; 1615 1616 unsigned Even = MRI.getSubReg(Reg, Sube); 1617 unsigned Odd = MRI.getSubReg(Reg, Subo); 1618 printRegName(O, Even); 1619 O << ", "; 1620 printRegName(O, Odd); 1621 } 1622 1623 void AArch64InstPrinter::printMatrixTileList(const MCInst *MI, unsigned OpNum, 1624 const MCSubtargetInfo &STI, 1625 raw_ostream &O) { 1626 unsigned MaxRegs = 8; 1627 unsigned RegMask = MI->getOperand(OpNum).getImm(); 1628 1629 unsigned NumRegs = 0; 1630 for (unsigned I = 0; I < MaxRegs; ++I) 1631 if ((RegMask & (1 << I)) != 0) 1632 ++NumRegs; 1633 1634 O << "{"; 1635 unsigned Printed = 0; 1636 for (unsigned I = 0; I < MaxRegs; ++I) { 1637 unsigned Reg = RegMask & (1 << I); 1638 if (Reg == 0) 1639 continue; 1640 printRegName(O, AArch64::ZAD0 + I); 1641 if (Printed + 1 != NumRegs) 1642 O << ", "; 1643 ++Printed; 1644 } 1645 O << "}"; 1646 } 1647 1648 void AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum, 1649 const MCSubtargetInfo &STI, 1650 raw_ostream &O, 1651 StringRef LayoutSuffix) { 1652 unsigned Reg = MI->getOperand(OpNum).getReg(); 1653 1654 O << "{ "; 1655 1656 // Work out how many registers there are in the list (if there is an actual 1657 // list). 1658 unsigned NumRegs = 1; 1659 if (MRI.getRegClass(AArch64::DDRegClassID).contains(Reg) || 1660 MRI.getRegClass(AArch64::ZPR2RegClassID).contains(Reg) || 1661 MRI.getRegClass(AArch64::QQRegClassID).contains(Reg) || 1662 MRI.getRegClass(AArch64::PPR2RegClassID).contains(Reg) || 1663 MRI.getRegClass(AArch64::ZPR2StridedRegClassID).contains(Reg)) 1664 NumRegs = 2; 1665 else if (MRI.getRegClass(AArch64::DDDRegClassID).contains(Reg) || 1666 MRI.getRegClass(AArch64::ZPR3RegClassID).contains(Reg) || 1667 MRI.getRegClass(AArch64::QQQRegClassID).contains(Reg)) 1668 NumRegs = 3; 1669 else if (MRI.getRegClass(AArch64::DDDDRegClassID).contains(Reg) || 1670 MRI.getRegClass(AArch64::ZPR4RegClassID).contains(Reg) || 1671 MRI.getRegClass(AArch64::QQQQRegClassID).contains(Reg) || 1672 MRI.getRegClass(AArch64::ZPR4StridedRegClassID).contains(Reg)) 1673 NumRegs = 4; 1674 1675 unsigned Stride = 1; 1676 if (MRI.getRegClass(AArch64::ZPR2StridedRegClassID).contains(Reg)) 1677 Stride = 8; 1678 else if (MRI.getRegClass(AArch64::ZPR4StridedRegClassID).contains(Reg)) 1679 Stride = 4; 1680 1681 // Now forget about the list and find out what the first register is. 1682 if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0)) 1683 Reg = FirstReg; 1684 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0)) 1685 Reg = FirstReg; 1686 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::zsub0)) 1687 Reg = FirstReg; 1688 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::psub0)) 1689 Reg = FirstReg; 1690 1691 // If it's a D-reg, we need to promote it to the equivalent Q-reg before 1692 // printing (otherwise getRegisterName fails). 1693 if (MRI.getRegClass(AArch64::FPR64RegClassID).contains(Reg)) { 1694 const MCRegisterClass &FPR128RC = 1695 MRI.getRegClass(AArch64::FPR128RegClassID); 1696 Reg = MRI.getMatchingSuperReg(Reg, AArch64::dsub, &FPR128RC); 1697 } 1698 1699 if ((MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg) || 1700 MRI.getRegClass(AArch64::PPRRegClassID).contains(Reg)) && 1701 NumRegs > 1 && Stride == 1 && 1702 // Do not print the range when the last register is lower than the first. 1703 // Because it is a wrap-around register. 1704 Reg < getNextVectorRegister(Reg, NumRegs - 1)) { 1705 printRegName(O, Reg); 1706 O << LayoutSuffix; 1707 if (NumRegs > 1) { 1708 // Set of two sve registers should be separated by ',' 1709 StringRef split_char = NumRegs == 2 ? ", " : " - "; 1710 O << split_char; 1711 printRegName(O, (getNextVectorRegister(Reg, NumRegs - 1))); 1712 O << LayoutSuffix; 1713 } 1714 } else { 1715 for (unsigned i = 0; i < NumRegs; 1716 ++i, Reg = getNextVectorRegister(Reg, Stride)) { 1717 // wrap-around sve register 1718 if (MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg) || 1719 MRI.getRegClass(AArch64::PPRRegClassID).contains(Reg)) 1720 printRegName(O, Reg); 1721 else 1722 printRegName(O, Reg, AArch64::vreg); 1723 O << LayoutSuffix; 1724 if (i + 1 != NumRegs) 1725 O << ", "; 1726 } 1727 } 1728 O << " }"; 1729 } 1730 1731 void 1732 AArch64InstPrinter::printImplicitlyTypedVectorList(const MCInst *MI, 1733 unsigned OpNum, 1734 const MCSubtargetInfo &STI, 1735 raw_ostream &O) { 1736 printVectorList(MI, OpNum, STI, O, ""); 1737 } 1738 1739 template <unsigned NumLanes, char LaneKind> 1740 void AArch64InstPrinter::printTypedVectorList(const MCInst *MI, unsigned OpNum, 1741 const MCSubtargetInfo &STI, 1742 raw_ostream &O) { 1743 if (LaneKind == 0) { 1744 printVectorList(MI, OpNum, STI, O, ""); 1745 return; 1746 } 1747 std::string Suffix("."); 1748 if (NumLanes) 1749 Suffix += itostr(NumLanes) + LaneKind; 1750 else 1751 Suffix += LaneKind; 1752 1753 printVectorList(MI, OpNum, STI, O, Suffix); 1754 } 1755 1756 template <unsigned Scale> 1757 void AArch64InstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum, 1758 const MCSubtargetInfo &STI, 1759 raw_ostream &O) { 1760 O << "[" << Scale * MI->getOperand(OpNum).getImm() << "]"; 1761 } 1762 1763 template <unsigned Scale> 1764 void AArch64InstPrinter::printMatrixIndex(const MCInst *MI, unsigned OpNum, 1765 const MCSubtargetInfo &STI, 1766 raw_ostream &O) { 1767 O << Scale * MI->getOperand(OpNum).getImm(); 1768 } 1769 1770 void AArch64InstPrinter::printAlignedLabel(const MCInst *MI, uint64_t Address, 1771 unsigned OpNum, 1772 const MCSubtargetInfo &STI, 1773 raw_ostream &O) { 1774 const MCOperand &Op = MI->getOperand(OpNum); 1775 1776 // If the label has already been resolved to an immediate offset (say, when 1777 // we're running the disassembler), just print the immediate. 1778 if (Op.isImm()) { 1779 int64_t Offset = Op.getImm() * 4; 1780 if (PrintBranchImmAsAddress) 1781 markup(O, Markup::Target) << formatHex(Address + Offset); 1782 else 1783 markup(O, Markup::Immediate) << "#" << formatImm(Offset); 1784 return; 1785 } 1786 1787 // If the branch target is simply an address then print it in hex. 1788 const MCConstantExpr *BranchTarget = 1789 dyn_cast<MCConstantExpr>(MI->getOperand(OpNum).getExpr()); 1790 int64_t TargetAddress; 1791 if (BranchTarget && BranchTarget->evaluateAsAbsolute(TargetAddress)) { 1792 markup(O, Markup::Target) << formatHex((uint64_t)TargetAddress); 1793 } else { 1794 // Otherwise, just print the expression. 1795 MI->getOperand(OpNum).getExpr()->print(O, &MAI); 1796 } 1797 } 1798 1799 void AArch64InstPrinter::printAdrAdrpLabel(const MCInst *MI, uint64_t Address, 1800 unsigned OpNum, 1801 const MCSubtargetInfo &STI, 1802 raw_ostream &O) { 1803 const MCOperand &Op = MI->getOperand(OpNum); 1804 1805 // If the label has already been resolved to an immediate offset (say, when 1806 // we're running the disassembler), just print the immediate. 1807 if (Op.isImm()) { 1808 int64_t Offset = Op.getImm(); 1809 if (MI->getOpcode() == AArch64::ADRP) { 1810 Offset = Offset * 4096; 1811 Address = Address & -4096; 1812 } 1813 WithMarkup M = markup(O, Markup::Immediate); 1814 if (PrintBranchImmAsAddress) 1815 markup(O, Markup::Target) << formatHex(Address + Offset); 1816 else 1817 markup(O, Markup::Immediate) << "#" << Offset; 1818 return; 1819 } 1820 1821 // Otherwise, just print the expression. 1822 MI->getOperand(OpNum).getExpr()->print(O, &MAI); 1823 } 1824 1825 void AArch64InstPrinter::printBarrierOption(const MCInst *MI, unsigned OpNo, 1826 const MCSubtargetInfo &STI, 1827 raw_ostream &O) { 1828 unsigned Val = MI->getOperand(OpNo).getImm(); 1829 unsigned Opcode = MI->getOpcode(); 1830 1831 StringRef Name; 1832 if (Opcode == AArch64::ISB) { 1833 auto ISB = AArch64ISB::lookupISBByEncoding(Val); 1834 Name = ISB ? ISB->Name : ""; 1835 } else if (Opcode == AArch64::TSB) { 1836 auto TSB = AArch64TSB::lookupTSBByEncoding(Val); 1837 Name = TSB ? TSB->Name : ""; 1838 } else { 1839 auto DB = AArch64DB::lookupDBByEncoding(Val); 1840 Name = DB ? DB->Name : ""; 1841 } 1842 if (!Name.empty()) 1843 O << Name; 1844 else 1845 markup(O, Markup::Immediate) << "#" << Val; 1846 } 1847 1848 void AArch64InstPrinter::printBarriernXSOption(const MCInst *MI, unsigned OpNo, 1849 const MCSubtargetInfo &STI, 1850 raw_ostream &O) { 1851 unsigned Val = MI->getOperand(OpNo).getImm(); 1852 assert(MI->getOpcode() == AArch64::DSBnXS); 1853 1854 StringRef Name; 1855 auto DB = AArch64DBnXS::lookupDBnXSByEncoding(Val); 1856 Name = DB ? DB->Name : ""; 1857 1858 if (!Name.empty()) 1859 O << Name; 1860 else 1861 markup(O, Markup::Immediate) << "#" << Val; 1862 } 1863 1864 static bool isValidSysReg(const AArch64SysReg::SysReg *Reg, bool Read, 1865 const MCSubtargetInfo &STI) { 1866 return (Reg && (Read ? Reg->Readable : Reg->Writeable) && 1867 Reg->haveFeatures(STI.getFeatureBits())); 1868 } 1869 1870 // Looks up a system register either by encoding or by name. Some system 1871 // registers share the same encoding between different architectures, 1872 // therefore a tablegen lookup by encoding will return an entry regardless 1873 // of the register's predication on a specific subtarget feature. To work 1874 // around this problem we keep an alternative name for such registers and 1875 // look them up by that name if the first lookup was unsuccessful. 1876 static const AArch64SysReg::SysReg *lookupSysReg(unsigned Val, bool Read, 1877 const MCSubtargetInfo &STI) { 1878 const AArch64SysReg::SysReg *Reg = AArch64SysReg::lookupSysRegByEncoding(Val); 1879 1880 if (Reg && !isValidSysReg(Reg, Read, STI)) 1881 Reg = AArch64SysReg::lookupSysRegByName(Reg->AltName); 1882 1883 return Reg; 1884 } 1885 1886 void AArch64InstPrinter::printMRSSystemRegister(const MCInst *MI, unsigned OpNo, 1887 const MCSubtargetInfo &STI, 1888 raw_ostream &O) { 1889 unsigned Val = MI->getOperand(OpNo).getImm(); 1890 1891 // Horrible hack for the one register that has identical encodings but 1892 // different names in MSR and MRS. Because of this, one of MRS and MSR is 1893 // going to get the wrong entry 1894 if (Val == AArch64SysReg::DBGDTRRX_EL0) { 1895 O << "DBGDTRRX_EL0"; 1896 return; 1897 } 1898 1899 // Horrible hack for two different registers having the same encoding. 1900 if (Val == AArch64SysReg::TRCEXTINSELR) { 1901 O << "TRCEXTINSELR"; 1902 return; 1903 } 1904 1905 const AArch64SysReg::SysReg *Reg = lookupSysReg(Val, true /*Read*/, STI); 1906 1907 if (isValidSysReg(Reg, true /*Read*/, STI)) 1908 O << Reg->Name; 1909 else 1910 O << AArch64SysReg::genericRegisterString(Val); 1911 } 1912 1913 void AArch64InstPrinter::printMSRSystemRegister(const MCInst *MI, unsigned OpNo, 1914 const MCSubtargetInfo &STI, 1915 raw_ostream &O) { 1916 unsigned Val = MI->getOperand(OpNo).getImm(); 1917 1918 // Horrible hack for the one register that has identical encodings but 1919 // different names in MSR and MRS. Because of this, one of MRS and MSR is 1920 // going to get the wrong entry 1921 if (Val == AArch64SysReg::DBGDTRTX_EL0) { 1922 O << "DBGDTRTX_EL0"; 1923 return; 1924 } 1925 1926 // Horrible hack for two different registers having the same encoding. 1927 if (Val == AArch64SysReg::TRCEXTINSELR) { 1928 O << "TRCEXTINSELR"; 1929 return; 1930 } 1931 1932 const AArch64SysReg::SysReg *Reg = lookupSysReg(Val, false /*Read*/, STI); 1933 1934 if (isValidSysReg(Reg, false /*Read*/, STI)) 1935 O << Reg->Name; 1936 else 1937 O << AArch64SysReg::genericRegisterString(Val); 1938 } 1939 1940 void AArch64InstPrinter::printSystemPStateField(const MCInst *MI, unsigned OpNo, 1941 const MCSubtargetInfo &STI, 1942 raw_ostream &O) { 1943 unsigned Val = MI->getOperand(OpNo).getImm(); 1944 1945 auto PStateImm15 = AArch64PState::lookupPStateImm0_15ByEncoding(Val); 1946 auto PStateImm1 = AArch64PState::lookupPStateImm0_1ByEncoding(Val); 1947 if (PStateImm15 && PStateImm15->haveFeatures(STI.getFeatureBits())) 1948 O << PStateImm15->Name; 1949 else if (PStateImm1 && PStateImm1->haveFeatures(STI.getFeatureBits())) 1950 O << PStateImm1->Name; 1951 else 1952 O << "#" << formatImm(Val); 1953 } 1954 1955 void AArch64InstPrinter::printSIMDType10Operand(const MCInst *MI, unsigned OpNo, 1956 const MCSubtargetInfo &STI, 1957 raw_ostream &O) { 1958 unsigned RawVal = MI->getOperand(OpNo).getImm(); 1959 uint64_t Val = AArch64_AM::decodeAdvSIMDModImmType10(RawVal); 1960 markup(O, Markup::Immediate) << format("#%#016llx", Val); 1961 } 1962 1963 template<int64_t Angle, int64_t Remainder> 1964 void AArch64InstPrinter::printComplexRotationOp(const MCInst *MI, unsigned OpNo, 1965 const MCSubtargetInfo &STI, 1966 raw_ostream &O) { 1967 unsigned Val = MI->getOperand(OpNo).getImm(); 1968 markup(O, Markup::Immediate) << "#" << (Val * Angle) + Remainder; 1969 } 1970 1971 void AArch64InstPrinter::printSVEPattern(const MCInst *MI, unsigned OpNum, 1972 const MCSubtargetInfo &STI, 1973 raw_ostream &O) { 1974 unsigned Val = MI->getOperand(OpNum).getImm(); 1975 if (auto Pat = AArch64SVEPredPattern::lookupSVEPREDPATByEncoding(Val)) 1976 O << Pat->Name; 1977 else 1978 markup(O, Markup::Immediate) << '#' << formatImm(Val); 1979 } 1980 1981 void AArch64InstPrinter::printSVEVecLenSpecifier(const MCInst *MI, 1982 unsigned OpNum, 1983 const MCSubtargetInfo &STI, 1984 raw_ostream &O) { 1985 unsigned Val = MI->getOperand(OpNum).getImm(); 1986 // Pattern has only 1 bit 1987 if (Val > 1) 1988 llvm_unreachable("Invalid vector length specifier"); 1989 if (auto Pat = 1990 AArch64SVEVecLenSpecifier::lookupSVEVECLENSPECIFIERByEncoding(Val)) 1991 O << Pat->Name; 1992 else 1993 llvm_unreachable("Invalid vector length specifier"); 1994 } 1995 1996 template <char suffix> 1997 void AArch64InstPrinter::printSVERegOp(const MCInst *MI, unsigned OpNum, 1998 const MCSubtargetInfo &STI, 1999 raw_ostream &O) { 2000 switch (suffix) { 2001 case 0: 2002 case 'b': 2003 case 'h': 2004 case 's': 2005 case 'd': 2006 case 'q': 2007 break; 2008 default: llvm_unreachable("Invalid kind specifier."); 2009 } 2010 2011 unsigned Reg = MI->getOperand(OpNum).getReg(); 2012 printRegName(O, Reg); 2013 if (suffix != 0) 2014 O << '.' << suffix; 2015 } 2016 2017 template <typename T> 2018 void AArch64InstPrinter::printImmSVE(T Value, raw_ostream &O) { 2019 std::make_unsigned_t<T> HexValue = Value; 2020 2021 if (getPrintImmHex()) 2022 markup(O, Markup::Immediate) << '#' << formatHex((uint64_t)HexValue); 2023 else 2024 markup(O, Markup::Immediate) << '#' << formatDec(Value); 2025 2026 if (CommentStream) { 2027 // Do the opposite to that used for instruction operands. 2028 if (getPrintImmHex()) 2029 *CommentStream << '=' << formatDec(HexValue) << '\n'; 2030 else 2031 *CommentStream << '=' << formatHex((uint64_t)Value) << '\n'; 2032 } 2033 } 2034 2035 template <typename T> 2036 void AArch64InstPrinter::printImm8OptLsl(const MCInst *MI, unsigned OpNum, 2037 const MCSubtargetInfo &STI, 2038 raw_ostream &O) { 2039 unsigned UnscaledVal = MI->getOperand(OpNum).getImm(); 2040 unsigned Shift = MI->getOperand(OpNum + 1).getImm(); 2041 assert(AArch64_AM::getShiftType(Shift) == AArch64_AM::LSL && 2042 "Unexepected shift type!"); 2043 2044 // #0 lsl #8 is never pretty printed 2045 if ((UnscaledVal == 0) && (AArch64_AM::getShiftValue(Shift) != 0)) { 2046 markup(O, Markup::Immediate) << '#' << formatImm(UnscaledVal); 2047 printShifter(MI, OpNum + 1, STI, O); 2048 return; 2049 } 2050 2051 T Val; 2052 if (std::is_signed<T>()) 2053 Val = (int8_t)UnscaledVal * (1 << AArch64_AM::getShiftValue(Shift)); 2054 else 2055 Val = (uint8_t)UnscaledVal * (1 << AArch64_AM::getShiftValue(Shift)); 2056 2057 printImmSVE(Val, O); 2058 } 2059 2060 template <typename T> 2061 void AArch64InstPrinter::printSVELogicalImm(const MCInst *MI, unsigned OpNum, 2062 const MCSubtargetInfo &STI, 2063 raw_ostream &O) { 2064 typedef std::make_signed_t<T> SignedT; 2065 typedef std::make_unsigned_t<T> UnsignedT; 2066 2067 uint64_t Val = MI->getOperand(OpNum).getImm(); 2068 UnsignedT PrintVal = AArch64_AM::decodeLogicalImmediate(Val, 64); 2069 2070 // Prefer the default format for 16bit values, hex otherwise. 2071 if ((int16_t)PrintVal == (SignedT)PrintVal) 2072 printImmSVE((T)PrintVal, O); 2073 else if ((uint16_t)PrintVal == PrintVal) 2074 printImmSVE(PrintVal, O); 2075 else 2076 markup(O, Markup::Immediate) << '#' << formatHex((uint64_t)PrintVal); 2077 } 2078 2079 template <int Width> 2080 void AArch64InstPrinter::printZPRasFPR(const MCInst *MI, unsigned OpNum, 2081 const MCSubtargetInfo &STI, 2082 raw_ostream &O) { 2083 unsigned Base; 2084 switch (Width) { 2085 case 8: Base = AArch64::B0; break; 2086 case 16: Base = AArch64::H0; break; 2087 case 32: Base = AArch64::S0; break; 2088 case 64: Base = AArch64::D0; break; 2089 case 128: Base = AArch64::Q0; break; 2090 default: 2091 llvm_unreachable("Unsupported width"); 2092 } 2093 unsigned Reg = MI->getOperand(OpNum).getReg(); 2094 printRegName(O, Reg - AArch64::Z0 + Base); 2095 } 2096 2097 template <unsigned ImmIs0, unsigned ImmIs1> 2098 void AArch64InstPrinter::printExactFPImm(const MCInst *MI, unsigned OpNum, 2099 const MCSubtargetInfo &STI, 2100 raw_ostream &O) { 2101 auto *Imm0Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmIs0); 2102 auto *Imm1Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmIs1); 2103 unsigned Val = MI->getOperand(OpNum).getImm(); 2104 markup(O, Markup::Immediate) 2105 << "#" << (Val ? Imm1Desc->Repr : Imm0Desc->Repr); 2106 } 2107 2108 void AArch64InstPrinter::printGPR64as32(const MCInst *MI, unsigned OpNum, 2109 const MCSubtargetInfo &STI, 2110 raw_ostream &O) { 2111 unsigned Reg = MI->getOperand(OpNum).getReg(); 2112 printRegName(O, getWRegFromXReg(Reg)); 2113 } 2114 2115 void AArch64InstPrinter::printGPR64x8(const MCInst *MI, unsigned OpNum, 2116 const MCSubtargetInfo &STI, 2117 raw_ostream &O) { 2118 unsigned Reg = MI->getOperand(OpNum).getReg(); 2119 printRegName(O, MRI.getSubReg(Reg, AArch64::x8sub_0)); 2120 } 2121 2122 void AArch64InstPrinter::printSyspXzrPair(const MCInst *MI, unsigned OpNum, 2123 const MCSubtargetInfo &STI, 2124 raw_ostream &O) { 2125 unsigned Reg = MI->getOperand(OpNum).getReg(); 2126 assert(Reg == AArch64::XZR && 2127 "MC representation of SyspXzrPair should be XZR"); 2128 O << getRegisterName(Reg) << ", " << getRegisterName(Reg); 2129 } 2130