1 //===-- VETargetMachine.cpp - Define TargetMachine for VE -----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11
12 #include "VETargetMachine.h"
13 #include "TargetInfo/VETargetInfo.h"
14 #include "VE.h"
15 #include "VEMachineFunctionInfo.h"
16 #include "VETargetTransformInfo.h"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
19 #include "llvm/CodeGen/TargetPassConfig.h"
20 #include "llvm/IR/LegacyPassManager.h"
21 #include "llvm/MC/TargetRegistry.h"
22 #include "llvm/Support/Compiler.h"
23 #include <optional>
24
25 using namespace llvm;
26
27 #define DEBUG_TYPE "ve"
28
LLVMInitializeVETarget()29 extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeVETarget() {
30 // Register the target.
31 RegisterTargetMachine<VETargetMachine> X(getTheVETarget());
32
33 PassRegistry &PR = *PassRegistry::getPassRegistry();
34 initializeVEAsmPrinterPass(PR);
35 initializeVEDAGToDAGISelLegacyPass(PR);
36 }
37
computeDataLayout(const Triple & T)38 static std::string computeDataLayout(const Triple &T) {
39 // Aurora VE is little endian
40 std::string Ret = "e";
41
42 // Use ELF mangling
43 Ret += "-m:e";
44
45 // Alignments for 64 bit integers.
46 Ret += "-i64:64";
47
48 // VE supports 32 bit and 64 bits integer on registers
49 Ret += "-n32:64";
50
51 // Stack alignment is 128 bits
52 Ret += "-S128";
53
54 // Vector alignments are 64 bits
55 // Need to define all of them. Otherwise, each alignment becomes
56 // the size of each data by default.
57 Ret += "-v64:64:64"; // for v2f32
58 Ret += "-v128:64:64";
59 Ret += "-v256:64:64";
60 Ret += "-v512:64:64";
61 Ret += "-v1024:64:64";
62 Ret += "-v2048:64:64";
63 Ret += "-v4096:64:64";
64 Ret += "-v8192:64:64";
65 Ret += "-v16384:64:64"; // for v256f64
66
67 return Ret;
68 }
69
getEffectiveRelocModel(std::optional<Reloc::Model> RM)70 static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
71 return RM.value_or(Reloc::Static);
72 }
73
74 namespace {
75 class VEELFTargetObjectFile : public TargetLoweringObjectFileELF {
Initialize(MCContext & Ctx,const TargetMachine & TM)76 void Initialize(MCContext &Ctx, const TargetMachine &TM) override {
77 TargetLoweringObjectFileELF::Initialize(Ctx, TM);
78 InitializeELF(TM.Options.UseInitArray);
79 }
80 };
81 } // namespace
82
createTLOF()83 static std::unique_ptr<TargetLoweringObjectFile> createTLOF() {
84 return std::make_unique<VEELFTargetObjectFile>();
85 }
86
87 /// Create an Aurora VE architecture model
VETargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOptLevel OL,bool JIT)88 VETargetMachine::VETargetMachine(const Target &T, const Triple &TT,
89 StringRef CPU, StringRef FS,
90 const TargetOptions &Options,
91 std::optional<Reloc::Model> RM,
92 std::optional<CodeModel::Model> CM,
93 CodeGenOptLevel OL, bool JIT)
94 : CodeGenTargetMachineImpl(T, computeDataLayout(TT), TT, CPU, FS, Options,
95 getEffectiveRelocModel(RM),
96 getEffectiveCodeModel(CM, CodeModel::Small), OL),
97 TLOF(createTLOF()),
98 Subtarget(TT, std::string(CPU), std::string(FS), *this) {
99 initAsmInfo();
100 }
101
102 VETargetMachine::~VETargetMachine() = default;
103
104 TargetTransformInfo
getTargetTransformInfo(const Function & F) const105 VETargetMachine::getTargetTransformInfo(const Function &F) const {
106 return TargetTransformInfo(std::make_unique<VETTIImpl>(this, F));
107 }
108
createMachineFunctionInfo(BumpPtrAllocator & Allocator,const Function & F,const TargetSubtargetInfo * STI) const109 MachineFunctionInfo *VETargetMachine::createMachineFunctionInfo(
110 BumpPtrAllocator &Allocator, const Function &F,
111 const TargetSubtargetInfo *STI) const {
112 return VEMachineFunctionInfo::create<VEMachineFunctionInfo>(Allocator, F,
113 STI);
114 }
115
116 namespace {
117 /// VE Code Generator Pass Configuration Options.
118 class VEPassConfig : public TargetPassConfig {
119 public:
VEPassConfig(VETargetMachine & TM,PassManagerBase & PM)120 VEPassConfig(VETargetMachine &TM, PassManagerBase &PM)
121 : TargetPassConfig(TM, PM) {}
122
getVETargetMachine() const123 VETargetMachine &getVETargetMachine() const {
124 return getTM<VETargetMachine>();
125 }
126
127 void addIRPasses() override;
128 bool addInstSelector() override;
129 void addPreEmitPass() override;
130 };
131 } // namespace
132
createPassConfig(PassManagerBase & PM)133 TargetPassConfig *VETargetMachine::createPassConfig(PassManagerBase &PM) {
134 return new VEPassConfig(*this, PM);
135 }
136
addIRPasses()137 void VEPassConfig::addIRPasses() {
138 // VE requires atomic expand pass.
139 addPass(createAtomicExpandLegacyPass());
140 TargetPassConfig::addIRPasses();
141 }
142
addInstSelector()143 bool VEPassConfig::addInstSelector() {
144 addPass(createVEISelDag(getVETargetMachine()));
145 return false;
146 }
147
addPreEmitPass()148 void VEPassConfig::addPreEmitPass() {
149 // LVLGen should be called after scheduling and register allocation
150 addPass(createLVLGenPass());
151 }
152