1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2024 AIROHA Inc 4 * Author: Lorenzo Bianconi <lorenzo@kernel.org> 5 */ 6 7 #ifndef AIROHA_REGS_H 8 #define AIROHA_REGS_H 9 10 #include <linux/types.h> 11 12 /* FE */ 13 #define PSE_BASE 0x0100 14 #define CSR_IFC_BASE 0x0200 15 #define CDM1_BASE 0x0400 16 #define GDM1_BASE 0x0500 17 #define PPE1_BASE 0x0c00 18 #define PPE2_BASE 0x1c00 19 20 #define CDM2_BASE 0x1400 21 #define GDM2_BASE 0x1500 22 23 #define GDM3_BASE 0x1100 24 #define GDM4_BASE 0x2500 25 26 #define GDM_BASE(_n) \ 27 ((_n) == 4 ? GDM4_BASE : \ 28 (_n) == 3 ? GDM3_BASE : \ 29 (_n) == 2 ? GDM2_BASE : GDM1_BASE) 30 31 #define REG_FE_DMA_GLO_CFG 0x0000 32 #define FE_DMA_GLO_L2_SPACE_MASK GENMASK(7, 4) 33 #define FE_DMA_GLO_PG_SZ_MASK BIT(3) 34 35 #define REG_FE_RST_GLO_CFG 0x0004 36 #define FE_RST_GDM4_MBI_ARB_MASK BIT(3) 37 #define FE_RST_GDM3_MBI_ARB_MASK BIT(2) 38 #define FE_RST_CORE_MASK BIT(0) 39 40 #define REG_FE_FOE_TS 0x0010 41 42 #define REG_FE_WAN_PORT 0x0024 43 #define WAN1_EN_MASK BIT(16) 44 #define WAN1_MASK GENMASK(12, 8) 45 #define WAN0_MASK GENMASK(4, 0) 46 47 #define REG_FE_WAN_MAC_H 0x0030 48 #define REG_FE_LAN_MAC_H 0x0040 49 50 #define REG_FE_MAC_LMIN(_n) ((_n) + 0x04) 51 #define REG_FE_MAC_LMAX(_n) ((_n) + 0x08) 52 53 #define REG_FE_CDM1_OQ_MAP0 0x0050 54 #define REG_FE_CDM1_OQ_MAP1 0x0054 55 #define REG_FE_CDM1_OQ_MAP2 0x0058 56 #define REG_FE_CDM1_OQ_MAP3 0x005c 57 58 #define REG_FE_PCE_CFG 0x0070 59 #define PCE_DPI_EN_MASK BIT(2) 60 #define PCE_KA_EN_MASK BIT(1) 61 #define PCE_MC_EN_MASK BIT(0) 62 63 #define REG_FE_PSE_QUEUE_CFG_WR 0x0080 64 #define PSE_CFG_PORT_ID_MASK GENMASK(27, 24) 65 #define PSE_CFG_QUEUE_ID_MASK GENMASK(20, 16) 66 #define PSE_CFG_WR_EN_MASK BIT(8) 67 #define PSE_CFG_OQRSV_SEL_MASK BIT(0) 68 69 #define REG_FE_PSE_QUEUE_CFG_VAL 0x0084 70 #define PSE_CFG_OQ_RSV_MASK GENMASK(13, 0) 71 72 #define PSE_FQ_CFG 0x008c 73 #define PSE_FQ_LIMIT_MASK GENMASK(14, 0) 74 75 #define REG_FE_PSE_BUF_SET 0x0090 76 #define PSE_SHARE_USED_LTHD_MASK GENMASK(31, 16) 77 #define PSE_ALLRSV_MASK GENMASK(14, 0) 78 79 #define REG_PSE_SHARE_USED_THD 0x0094 80 #define PSE_SHARE_USED_MTHD_MASK GENMASK(31, 16) 81 #define PSE_SHARE_USED_HTHD_MASK GENMASK(15, 0) 82 83 #define REG_GDM_MISC_CFG 0x0148 84 #define GDM2_RDM_ACK_WAIT_PREF_MASK BIT(9) 85 #define GDM2_CHN_VLD_MODE_MASK BIT(5) 86 87 #define REG_FE_CSR_IFC_CFG CSR_IFC_BASE 88 #define FE_IFC_EN_MASK BIT(0) 89 90 #define REG_FE_VIP_PORT_EN 0x01f0 91 #define REG_FE_IFC_PORT_EN 0x01f4 92 93 #define REG_PSE_IQ_REV1 (PSE_BASE + 0x08) 94 #define PSE_IQ_RES1_P2_MASK GENMASK(23, 16) 95 96 #define REG_PSE_IQ_REV2 (PSE_BASE + 0x0c) 97 #define PSE_IQ_RES2_P5_MASK GENMASK(15, 8) 98 #define PSE_IQ_RES2_P4_MASK GENMASK(7, 0) 99 100 #define REG_FE_VIP_EN(_n) (0x0300 + ((_n) << 3)) 101 #define PATN_FCPU_EN_MASK BIT(7) 102 #define PATN_SWP_EN_MASK BIT(6) 103 #define PATN_DP_EN_MASK BIT(5) 104 #define PATN_SP_EN_MASK BIT(4) 105 #define PATN_TYPE_MASK GENMASK(3, 1) 106 #define PATN_EN_MASK BIT(0) 107 108 #define REG_FE_VIP_PATN(_n) (0x0304 + ((_n) << 3)) 109 #define PATN_DP_MASK GENMASK(31, 16) 110 #define PATN_SP_MASK GENMASK(15, 0) 111 112 #define REG_CDM1_VLAN_CTRL CDM1_BASE 113 #define CDM1_VLAN_MASK GENMASK(31, 16) 114 115 #define REG_CDM1_FWD_CFG (CDM1_BASE + 0x08) 116 #define CDM1_VIP_QSEL_MASK GENMASK(24, 20) 117 118 #define REG_CDM1_CRSN_QSEL(_n) (CDM1_BASE + 0x10 + ((_n) << 2)) 119 #define CDM1_CRSN_QSEL_REASON_MASK(_n) \ 120 GENMASK(4 + (((_n) % 4) << 3), (((_n) % 4) << 3)) 121 122 #define REG_CDM2_FWD_CFG (CDM2_BASE + 0x08) 123 #define CDM2_OAM_QSEL_MASK GENMASK(31, 27) 124 #define CDM2_VIP_QSEL_MASK GENMASK(24, 20) 125 126 #define REG_CDM2_CRSN_QSEL(_n) (CDM2_BASE + 0x10 + ((_n) << 2)) 127 #define CDM2_CRSN_QSEL_REASON_MASK(_n) \ 128 GENMASK(4 + (((_n) % 4) << 3), (((_n) % 4) << 3)) 129 130 #define REG_GDM_FWD_CFG(_n) GDM_BASE(_n) 131 #define GDM_DROP_CRC_ERR BIT(23) 132 #define GDM_IP4_CKSUM BIT(22) 133 #define GDM_TCP_CKSUM BIT(21) 134 #define GDM_UDP_CKSUM BIT(20) 135 #define GDM_STRIP_CRC BIT(16) 136 #define GDM_UCFQ_MASK GENMASK(15, 12) 137 #define GDM_BCFQ_MASK GENMASK(11, 8) 138 #define GDM_MCFQ_MASK GENMASK(7, 4) 139 #define GDM_OCFQ_MASK GENMASK(3, 0) 140 141 #define REG_GDM_INGRESS_CFG(_n) (GDM_BASE(_n) + 0x10) 142 #define GDM_INGRESS_FC_EN_MASK BIT(1) 143 #define GDM_STAG_EN_MASK BIT(0) 144 145 #define REG_GDM_LEN_CFG(_n) (GDM_BASE(_n) + 0x14) 146 #define GDM_SHORT_LEN_MASK GENMASK(13, 0) 147 #define GDM_LONG_LEN_MASK GENMASK(29, 16) 148 149 #define REG_GDM_LPBK_CFG(_n) (GDM_BASE(_n) + 0x1c) 150 #define LPBK_GAP_MASK GENMASK(31, 24) 151 #define LPBK_LEN_MASK GENMASK(23, 10) 152 #define LPBK_CHAN_MASK GENMASK(8, 4) 153 #define LPBK_MODE_MASK GENMASK(3, 1) 154 #define LBK_GAP_MODE_MASK BIT(3) 155 #define LBK_LEN_MODE_MASK BIT(2) 156 #define LBK_CHAN_MODE_MASK BIT(1) 157 #define LPBK_EN_MASK BIT(0) 158 159 #define REG_GDM_TXCHN_EN(_n) (GDM_BASE(_n) + 0x24) 160 #define REG_GDM_RXCHN_EN(_n) (GDM_BASE(_n) + 0x28) 161 162 #define REG_FE_CPORT_CFG (GDM1_BASE + 0x40) 163 #define FE_CPORT_PAD BIT(26) 164 #define FE_CPORT_PORT_XFC_MASK BIT(25) 165 #define FE_CPORT_QUEUE_XFC_MASK BIT(24) 166 167 #define REG_FE_GDM_MIB_CLEAR(_n) (GDM_BASE(_n) + 0xf0) 168 #define FE_GDM_MIB_RX_CLEAR_MASK BIT(1) 169 #define FE_GDM_MIB_TX_CLEAR_MASK BIT(0) 170 171 #define REG_FE_GDM1_MIB_CFG (GDM1_BASE + 0xf4) 172 #define FE_STRICT_RFC2819_MODE_MASK BIT(31) 173 #define FE_GDM1_TX_MIB_SPLIT_EN_MASK BIT(17) 174 #define FE_GDM1_RX_MIB_SPLIT_EN_MASK BIT(16) 175 #define FE_TX_MIB_ID_MASK GENMASK(15, 8) 176 #define FE_RX_MIB_ID_MASK GENMASK(7, 0) 177 178 #define REG_FE_GDM_TX_OK_PKT_CNT_L(_n) (GDM_BASE(_n) + 0x104) 179 #define REG_FE_GDM_TX_OK_BYTE_CNT_L(_n) (GDM_BASE(_n) + 0x10c) 180 #define REG_FE_GDM_TX_ETH_PKT_CNT_L(_n) (GDM_BASE(_n) + 0x110) 181 #define REG_FE_GDM_TX_ETH_BYTE_CNT_L(_n) (GDM_BASE(_n) + 0x114) 182 #define REG_FE_GDM_TX_ETH_DROP_CNT(_n) (GDM_BASE(_n) + 0x118) 183 #define REG_FE_GDM_TX_ETH_BC_CNT(_n) (GDM_BASE(_n) + 0x11c) 184 #define REG_FE_GDM_TX_ETH_MC_CNT(_n) (GDM_BASE(_n) + 0x120) 185 #define REG_FE_GDM_TX_ETH_RUNT_CNT(_n) (GDM_BASE(_n) + 0x124) 186 #define REG_FE_GDM_TX_ETH_LONG_CNT(_n) (GDM_BASE(_n) + 0x128) 187 #define REG_FE_GDM_TX_ETH_E64_CNT_L(_n) (GDM_BASE(_n) + 0x12c) 188 #define REG_FE_GDM_TX_ETH_L64_CNT_L(_n) (GDM_BASE(_n) + 0x130) 189 #define REG_FE_GDM_TX_ETH_L127_CNT_L(_n) (GDM_BASE(_n) + 0x134) 190 #define REG_FE_GDM_TX_ETH_L255_CNT_L(_n) (GDM_BASE(_n) + 0x138) 191 #define REG_FE_GDM_TX_ETH_L511_CNT_L(_n) (GDM_BASE(_n) + 0x13c) 192 #define REG_FE_GDM_TX_ETH_L1023_CNT_L(_n) (GDM_BASE(_n) + 0x140) 193 194 #define REG_FE_GDM_RX_OK_PKT_CNT_L(_n) (GDM_BASE(_n) + 0x148) 195 #define REG_FE_GDM_RX_FC_DROP_CNT(_n) (GDM_BASE(_n) + 0x14c) 196 #define REG_FE_GDM_RX_RC_DROP_CNT(_n) (GDM_BASE(_n) + 0x150) 197 #define REG_FE_GDM_RX_OVERFLOW_DROP_CNT(_n) (GDM_BASE(_n) + 0x154) 198 #define REG_FE_GDM_RX_ERROR_DROP_CNT(_n) (GDM_BASE(_n) + 0x158) 199 #define REG_FE_GDM_RX_OK_BYTE_CNT_L(_n) (GDM_BASE(_n) + 0x15c) 200 #define REG_FE_GDM_RX_ETH_PKT_CNT_L(_n) (GDM_BASE(_n) + 0x160) 201 #define REG_FE_GDM_RX_ETH_BYTE_CNT_L(_n) (GDM_BASE(_n) + 0x164) 202 #define REG_FE_GDM_RX_ETH_DROP_CNT(_n) (GDM_BASE(_n) + 0x168) 203 #define REG_FE_GDM_RX_ETH_BC_CNT(_n) (GDM_BASE(_n) + 0x16c) 204 #define REG_FE_GDM_RX_ETH_MC_CNT(_n) (GDM_BASE(_n) + 0x170) 205 #define REG_FE_GDM_RX_ETH_CRC_ERR_CNT(_n) (GDM_BASE(_n) + 0x174) 206 #define REG_FE_GDM_RX_ETH_FRAG_CNT(_n) (GDM_BASE(_n) + 0x178) 207 #define REG_FE_GDM_RX_ETH_JABBER_CNT(_n) (GDM_BASE(_n) + 0x17c) 208 #define REG_FE_GDM_RX_ETH_RUNT_CNT(_n) (GDM_BASE(_n) + 0x180) 209 #define REG_FE_GDM_RX_ETH_LONG_CNT(_n) (GDM_BASE(_n) + 0x184) 210 #define REG_FE_GDM_RX_ETH_E64_CNT_L(_n) (GDM_BASE(_n) + 0x188) 211 #define REG_FE_GDM_RX_ETH_L64_CNT_L(_n) (GDM_BASE(_n) + 0x18c) 212 #define REG_FE_GDM_RX_ETH_L127_CNT_L(_n) (GDM_BASE(_n) + 0x190) 213 #define REG_FE_GDM_RX_ETH_L255_CNT_L(_n) (GDM_BASE(_n) + 0x194) 214 #define REG_FE_GDM_RX_ETH_L511_CNT_L(_n) (GDM_BASE(_n) + 0x198) 215 #define REG_FE_GDM_RX_ETH_L1023_CNT_L(_n) (GDM_BASE(_n) + 0x19c) 216 217 #define REG_PPE_GLO_CFG(_n) (((_n) ? PPE2_BASE : PPE1_BASE) + 0x200) 218 #define PPE_GLO_CFG_BUSY_MASK BIT(31) 219 #define PPE_GLO_CFG_FLOW_DROP_UPDATE_MASK BIT(9) 220 #define PPE_GLO_CFG_PSE_HASH_OFS_MASK BIT(6) 221 #define PPE_GLO_CFG_PPE_BSWAP_MASK BIT(5) 222 #define PPE_GLO_CFG_TTL_DROP_MASK BIT(4) 223 #define PPE_GLO_CFG_IP4_CS_DROP_MASK BIT(3) 224 #define PPE_GLO_CFG_IP4_L4_CS_DROP_MASK BIT(2) 225 #define PPE_GLO_CFG_EN_MASK BIT(0) 226 227 #define REG_PPE_PPE_FLOW_CFG(_n) (((_n) ? PPE2_BASE : PPE1_BASE) + 0x204) 228 #define PPE_FLOW_CFG_IP6_HASH_GRE_KEY_MASK BIT(20) 229 #define PPE_FLOW_CFG_IP4_HASH_GRE_KEY_MASK BIT(19) 230 #define PPE_FLOW_CFG_IP4_HASH_FLOW_LABEL_MASK BIT(18) 231 #define PPE_FLOW_CFG_IP4_NAT_FRAG_MASK BIT(17) 232 #define PPE_FLOW_CFG_IP_PROTO_BLACKLIST_MASK BIT(16) 233 #define PPE_FLOW_CFG_IP4_DSLITE_MASK BIT(14) 234 #define PPE_FLOW_CFG_IP4_NAPT_MASK BIT(13) 235 #define PPE_FLOW_CFG_IP4_NAT_MASK BIT(12) 236 #define PPE_FLOW_CFG_IP6_6RD_MASK BIT(10) 237 #define PPE_FLOW_CFG_IP6_5T_ROUTE_MASK BIT(9) 238 #define PPE_FLOW_CFG_IP6_3T_ROUTE_MASK BIT(8) 239 #define PPE_FLOW_CFG_IP4_UDP_FRAG_MASK BIT(7) 240 #define PPE_FLOW_CFG_IP4_TCP_FRAG_MASK BIT(6) 241 242 #define REG_PPE_IP_PROTO_CHK(_n) (((_n) ? PPE2_BASE : PPE1_BASE) + 0x208) 243 #define PPE_IP_PROTO_CHK_IPV4_MASK GENMASK(31, 16) 244 #define PPE_IP_PROTO_CHK_IPV6_MASK GENMASK(15, 0) 245 246 #define REG_PPE_TB_CFG(_n) (((_n) ? PPE2_BASE : PPE1_BASE) + 0x21c) 247 #define PPE_SRAM_TB_NUM_ENTRY_MASK GENMASK(26, 24) 248 #define PPE_TB_CFG_KEEPALIVE_MASK GENMASK(13, 12) 249 #define PPE_TB_CFG_AGE_TCP_FIN_MASK BIT(11) 250 #define PPE_TB_CFG_AGE_UDP_MASK BIT(10) 251 #define PPE_TB_CFG_AGE_TCP_MASK BIT(9) 252 #define PPE_TB_CFG_AGE_UNBIND_MASK BIT(8) 253 #define PPE_TB_CFG_AGE_NON_L4_MASK BIT(7) 254 #define PPE_TB_CFG_AGE_PREBIND_MASK BIT(6) 255 #define PPE_TB_CFG_SEARCH_MISS_MASK GENMASK(5, 4) 256 #define PPE_TB_ENTRY_SIZE_MASK BIT(3) 257 #define PPE_DRAM_TB_NUM_ENTRY_MASK GENMASK(2, 0) 258 259 #define REG_PPE_TB_BASE(_n) (((_n) ? PPE2_BASE : PPE1_BASE) + 0x220) 260 261 #define REG_PPE_BIND_RATE(_n) (((_n) ? PPE2_BASE : PPE1_BASE) + 0x228) 262 #define PPE_BIND_RATE_L2B_BIND_MASK GENMASK(31, 16) 263 #define PPE_BIND_RATE_BIND_MASK GENMASK(15, 0) 264 265 #define REG_PPE_BIND_LIMIT0(_n) (((_n) ? PPE2_BASE : PPE1_BASE) + 0x22c) 266 #define PPE_BIND_LIMIT0_HALF_MASK GENMASK(29, 16) 267 #define PPE_BIND_LIMIT0_QUARTER_MASK GENMASK(13, 0) 268 269 #define REG_PPE_BIND_LIMIT1(_n) (((_n) ? PPE2_BASE : PPE1_BASE) + 0x230) 270 #define PPE_BIND_LIMIT1_NON_L4_MASK GENMASK(23, 16) 271 #define PPE_BIND_LIMIT1_FULL_MASK GENMASK(13, 0) 272 273 #define REG_PPE_BND_AGE0(_n) (((_n) ? PPE2_BASE : PPE1_BASE) + 0x23c) 274 #define PPE_BIND_AGE0_DELTA_NON_L4 GENMASK(30, 16) 275 #define PPE_BIND_AGE0_DELTA_UDP GENMASK(14, 0) 276 277 #define REG_PPE_UNBIND_AGE(_n) (((_n) ? PPE2_BASE : PPE1_BASE) + 0x238) 278 #define PPE_UNBIND_AGE_MIN_PACKETS_MASK GENMASK(31, 16) 279 #define PPE_UNBIND_AGE_DELTA_MASK GENMASK(7, 0) 280 281 #define REG_PPE_BND_AGE1(_n) (((_n) ? PPE2_BASE : PPE1_BASE) + 0x240) 282 #define PPE_BIND_AGE1_DELTA_TCP_FIN GENMASK(30, 16) 283 #define PPE_BIND_AGE1_DELTA_TCP GENMASK(14, 0) 284 285 #define REG_PPE_HASH_SEED(_n) (((_n) ? PPE2_BASE : PPE1_BASE) + 0x244) 286 #define PPE_HASH_SEED 0x12345678 287 288 #define REG_PPE_DFT_CPORT0(_n) (((_n) ? PPE2_BASE : PPE1_BASE) + 0x248) 289 #define DFT_CPORT_MASK(_n) GENMASK(3 + ((_n) << 2), ((_n) << 2)) 290 291 #define REG_PPE_DFT_CPORT1(_n) (((_n) ? PPE2_BASE : PPE1_BASE) + 0x24c) 292 293 #define REG_PPE_TB_HASH_CFG(_n) (((_n) ? PPE2_BASE : PPE1_BASE) + 0x250) 294 #define PPE_DRAM_HASH1_MODE_MASK GENMASK(31, 28) 295 #define PPE_DRAM_HASH1_EN_MASK BIT(24) 296 #define PPE_DRAM_HASH0_MODE_MASK GENMASK(23, 20) 297 #define PPE_DRAM_TABLE_EN_MASK BIT(16) 298 #define PPE_SRAM_HASH1_MODE_MASK GENMASK(15, 12) 299 #define PPE_SRAM_HASH1_EN_MASK BIT(8) 300 #define PPE_SRAM_HASH0_MODE_MASK GENMASK(7, 4) 301 #define PPE_SRAM_TABLE_EN_MASK BIT(0) 302 303 #define REG_PPE_MTU_BASE(_n) (((_n) ? PPE2_BASE : PPE1_BASE) + 0x304) 304 #define REG_PPE_MTU(_m, _n) (REG_PPE_MTU_BASE(_m) + ((_n) << 2)) 305 #define FP1_EGRESS_MTU_MASK GENMASK(29, 16) 306 #define FP0_EGRESS_MTU_MASK GENMASK(13, 0) 307 308 #define REG_PPE_RAM_CTRL(_n) (((_n) ? PPE2_BASE : PPE1_BASE) + 0x31c) 309 #define PPE_SRAM_CTRL_ACK_MASK BIT(31) 310 #define PPE_SRAM_CTRL_DUAL_SUCESS_MASK BIT(30) 311 #define PPE_SRAM_CTRL_ENTRY_MASK GENMASK(23, 8) 312 #define PPE_SRAM_WR_DUAL_DIRECTION_MASK BIT(2) 313 #define PPE_SRAM_CTRL_WR_MASK BIT(1) 314 #define PPE_SRAM_CTRL_REQ_MASK BIT(0) 315 316 #define REG_PPE_RAM_BASE(_n) (((_n) ? PPE2_BASE : PPE1_BASE) + 0x320) 317 #define REG_PPE_RAM_ENTRY(_m, _n) (REG_PPE_RAM_BASE(_m) + ((_n) << 2)) 318 319 #define REG_UPDMEM_CTRL(_n) (((_n) ? PPE2_BASE : PPE1_BASE) + 0x370) 320 #define PPE_UPDMEM_ACK_MASK BIT(31) 321 #define PPE_UPDMEM_ADDR_MASK GENMASK(11, 8) 322 #define PPE_UPDMEM_OFFSET_MASK GENMASK(7, 4) 323 #define PPE_UPDMEM_SEL_MASK GENMASK(3, 2) 324 #define PPE_UPDMEM_WR_MASK BIT(1) 325 #define PPE_UPDMEM_REQ_MASK BIT(0) 326 327 #define REG_UPDMEM_DATA(_n) (((_n) ? PPE2_BASE : PPE1_BASE) + 0x374) 328 329 #define REG_FE_GDM_TX_OK_PKT_CNT_H(_n) (GDM_BASE(_n) + 0x280) 330 #define REG_FE_GDM_TX_OK_BYTE_CNT_H(_n) (GDM_BASE(_n) + 0x284) 331 #define REG_FE_GDM_TX_ETH_PKT_CNT_H(_n) (GDM_BASE(_n) + 0x288) 332 #define REG_FE_GDM_TX_ETH_BYTE_CNT_H(_n) (GDM_BASE(_n) + 0x28c) 333 334 #define REG_FE_GDM_RX_OK_PKT_CNT_H(_n) (GDM_BASE(_n) + 0x290) 335 #define REG_FE_GDM_RX_OK_BYTE_CNT_H(_n) (GDM_BASE(_n) + 0x294) 336 #define REG_FE_GDM_RX_ETH_PKT_CNT_H(_n) (GDM_BASE(_n) + 0x298) 337 #define REG_FE_GDM_RX_ETH_BYTE_CNT_H(_n) (GDM_BASE(_n) + 0x29c) 338 #define REG_FE_GDM_TX_ETH_E64_CNT_H(_n) (GDM_BASE(_n) + 0x2b8) 339 #define REG_FE_GDM_TX_ETH_L64_CNT_H(_n) (GDM_BASE(_n) + 0x2bc) 340 #define REG_FE_GDM_TX_ETH_L127_CNT_H(_n) (GDM_BASE(_n) + 0x2c0) 341 #define REG_FE_GDM_TX_ETH_L255_CNT_H(_n) (GDM_BASE(_n) + 0x2c4) 342 #define REG_FE_GDM_TX_ETH_L511_CNT_H(_n) (GDM_BASE(_n) + 0x2c8) 343 #define REG_FE_GDM_TX_ETH_L1023_CNT_H(_n) (GDM_BASE(_n) + 0x2cc) 344 #define REG_FE_GDM_RX_ETH_E64_CNT_H(_n) (GDM_BASE(_n) + 0x2e8) 345 #define REG_FE_GDM_RX_ETH_L64_CNT_H(_n) (GDM_BASE(_n) + 0x2ec) 346 #define REG_FE_GDM_RX_ETH_L127_CNT_H(_n) (GDM_BASE(_n) + 0x2f0) 347 #define REG_FE_GDM_RX_ETH_L255_CNT_H(_n) (GDM_BASE(_n) + 0x2f4) 348 #define REG_FE_GDM_RX_ETH_L511_CNT_H(_n) (GDM_BASE(_n) + 0x2f8) 349 #define REG_FE_GDM_RX_ETH_L1023_CNT_H(_n) (GDM_BASE(_n) + 0x2fc) 350 351 #define REG_GDM2_CHN_RLS (GDM2_BASE + 0x20) 352 #define MBI_RX_AGE_SEL_MASK GENMASK(26, 25) 353 #define MBI_TX_AGE_SEL_MASK GENMASK(18, 17) 354 355 #define REG_GDM3_FWD_CFG GDM3_BASE 356 #define GDM3_PAD_EN_MASK BIT(28) 357 358 #define REG_GDM4_FWD_CFG GDM4_BASE 359 #define GDM4_PAD_EN_MASK BIT(28) 360 #define GDM4_SPORT_OFFSET0_MASK GENMASK(11, 8) 361 362 #define REG_GDM4_SRC_PORT_SET (GDM4_BASE + 0x23c) 363 #define GDM4_SPORT_OFF2_MASK GENMASK(19, 16) 364 #define GDM4_SPORT_OFF1_MASK GENMASK(15, 12) 365 #define GDM4_SPORT_OFF0_MASK GENMASK(11, 8) 366 367 #define REG_IP_FRAG_FP 0x2010 368 #define IP_ASSEMBLE_PORT_MASK GENMASK(24, 21) 369 #define IP_ASSEMBLE_NBQ_MASK GENMASK(20, 16) 370 #define IP_FRAGMENT_PORT_MASK GENMASK(8, 5) 371 #define IP_FRAGMENT_NBQ_MASK GENMASK(4, 0) 372 373 #define REG_MC_VLAN_EN 0x2100 374 #define MC_VLAN_EN_MASK BIT(0) 375 376 #define REG_MC_VLAN_CFG 0x2104 377 #define MC_VLAN_CFG_CMD_DONE_MASK BIT(31) 378 #define MC_VLAN_CFG_TABLE_ID_MASK GENMASK(21, 16) 379 #define MC_VLAN_CFG_PORT_ID_MASK GENMASK(11, 8) 380 #define MC_VLAN_CFG_TABLE_SEL_MASK BIT(4) 381 #define MC_VLAN_CFG_RW_MASK BIT(0) 382 383 #define REG_MC_VLAN_DATA 0x2108 384 385 #define REG_SP_DFT_CPORT(_n) (0x20e0 + ((_n) << 2)) 386 #define SP_CPORT_PCIE1_MASK GENMASK(31, 28) 387 #define SP_CPORT_PCIE0_MASK GENMASK(27, 24) 388 #define SP_CPORT_USB_MASK GENMASK(7, 4) 389 #define SP_CPORT_ETH_MASK GENMASK(7, 4) 390 391 #define REG_SRC_PORT_FC_MAP6 0x2298 392 #define FC_ID_OF_SRC_PORT27_MASK GENMASK(28, 24) 393 #define FC_ID_OF_SRC_PORT26_MASK GENMASK(20, 16) 394 #define FC_ID_OF_SRC_PORT25_MASK GENMASK(12, 8) 395 #define FC_ID_OF_SRC_PORT24_MASK GENMASK(4, 0) 396 397 #define REG_CDM5_RX_OQ1_DROP_CNT 0x29d4 398 399 /* QDMA */ 400 #define REG_QDMA_GLOBAL_CFG 0x0004 401 #define GLOBAL_CFG_RX_2B_OFFSET_MASK BIT(31) 402 #define GLOBAL_CFG_DMA_PREFERENCE_MASK GENMASK(30, 29) 403 #define GLOBAL_CFG_CPU_TXR_RR_MASK BIT(28) 404 #define GLOBAL_CFG_DSCP_BYTE_SWAP_MASK BIT(27) 405 #define GLOBAL_CFG_PAYLOAD_BYTE_SWAP_MASK BIT(26) 406 #define GLOBAL_CFG_MULTICAST_MODIFY_FP_MASK BIT(25) 407 #define GLOBAL_CFG_OAM_MODIFY_MASK BIT(24) 408 #define GLOBAL_CFG_RESET_MASK BIT(23) 409 #define GLOBAL_CFG_RESET_DONE_MASK BIT(22) 410 #define GLOBAL_CFG_MULTICAST_EN_MASK BIT(21) 411 #define GLOBAL_CFG_IRQ1_EN_MASK BIT(20) 412 #define GLOBAL_CFG_IRQ0_EN_MASK BIT(19) 413 #define GLOBAL_CFG_LOOPCNT_EN_MASK BIT(18) 414 #define GLOBAL_CFG_RD_BYPASS_WR_MASK BIT(17) 415 #define GLOBAL_CFG_QDMA_LOOPBACK_MASK BIT(16) 416 #define GLOBAL_CFG_LPBK_RXQ_SEL_MASK GENMASK(13, 8) 417 #define GLOBAL_CFG_CHECK_DONE_MASK BIT(7) 418 #define GLOBAL_CFG_TX_WB_DONE_MASK BIT(6) 419 #define GLOBAL_CFG_MAX_ISSUE_NUM_MASK GENMASK(5, 4) 420 #define GLOBAL_CFG_RX_DMA_BUSY_MASK BIT(3) 421 #define GLOBAL_CFG_RX_DMA_EN_MASK BIT(2) 422 #define GLOBAL_CFG_TX_DMA_BUSY_MASK BIT(1) 423 #define GLOBAL_CFG_TX_DMA_EN_MASK BIT(0) 424 425 #define REG_FWD_DSCP_BASE 0x0010 426 #define REG_FWD_BUF_BASE 0x0014 427 428 #define REG_HW_FWD_DSCP_CFG 0x0018 429 #define HW_FWD_DSCP_PAYLOAD_SIZE_MASK GENMASK(29, 28) 430 #define HW_FWD_DSCP_SCATTER_LEN_MASK GENMASK(17, 16) 431 #define HW_FWD_DSCP_MIN_SCATTER_LEN_MASK GENMASK(15, 0) 432 433 #define REG_INT_STATUS(_n) \ 434 (((_n) == 4) ? 0x0730 : \ 435 ((_n) == 3) ? 0x0724 : \ 436 ((_n) == 2) ? 0x0720 : \ 437 ((_n) == 1) ? 0x0024 : 0x0020) 438 439 #define REG_INT_ENABLE(_b, _n) \ 440 (((_n) == 4) ? 0x0750 + ((_b) << 5) : \ 441 ((_n) == 3) ? 0x0744 + ((_b) << 5) : \ 442 ((_n) == 2) ? 0x0740 + ((_b) << 5) : \ 443 ((_n) == 1) ? 0x002c + ((_b) << 3) : \ 444 0x0028 + ((_b) << 3)) 445 446 /* QDMA_CSR_INT_ENABLE1 */ 447 #define RX15_COHERENT_INT_MASK BIT(31) 448 #define RX14_COHERENT_INT_MASK BIT(30) 449 #define RX13_COHERENT_INT_MASK BIT(29) 450 #define RX12_COHERENT_INT_MASK BIT(28) 451 #define RX11_COHERENT_INT_MASK BIT(27) 452 #define RX10_COHERENT_INT_MASK BIT(26) 453 #define RX9_COHERENT_INT_MASK BIT(25) 454 #define RX8_COHERENT_INT_MASK BIT(24) 455 #define RX7_COHERENT_INT_MASK BIT(23) 456 #define RX6_COHERENT_INT_MASK BIT(22) 457 #define RX5_COHERENT_INT_MASK BIT(21) 458 #define RX4_COHERENT_INT_MASK BIT(20) 459 #define RX3_COHERENT_INT_MASK BIT(19) 460 #define RX2_COHERENT_INT_MASK BIT(18) 461 #define RX1_COHERENT_INT_MASK BIT(17) 462 #define RX0_COHERENT_INT_MASK BIT(16) 463 #define TX7_COHERENT_INT_MASK BIT(15) 464 #define TX6_COHERENT_INT_MASK BIT(14) 465 #define TX5_COHERENT_INT_MASK BIT(13) 466 #define TX4_COHERENT_INT_MASK BIT(12) 467 #define TX3_COHERENT_INT_MASK BIT(11) 468 #define TX2_COHERENT_INT_MASK BIT(10) 469 #define TX1_COHERENT_INT_MASK BIT(9) 470 #define TX0_COHERENT_INT_MASK BIT(8) 471 #define CNT_OVER_FLOW_INT_MASK BIT(7) 472 #define IRQ1_FULL_INT_MASK BIT(5) 473 #define IRQ1_INT_MASK BIT(4) 474 #define HWFWD_DSCP_LOW_INT_MASK BIT(3) 475 #define HWFWD_DSCP_EMPTY_INT_MASK BIT(2) 476 #define IRQ0_FULL_INT_MASK BIT(1) 477 #define IRQ0_INT_MASK BIT(0) 478 479 #define RX_COHERENT_LOW_INT_MASK \ 480 (RX15_COHERENT_INT_MASK | RX14_COHERENT_INT_MASK | \ 481 RX13_COHERENT_INT_MASK | RX12_COHERENT_INT_MASK | \ 482 RX11_COHERENT_INT_MASK | RX10_COHERENT_INT_MASK | \ 483 RX9_COHERENT_INT_MASK | RX8_COHERENT_INT_MASK | \ 484 RX7_COHERENT_INT_MASK | RX6_COHERENT_INT_MASK | \ 485 RX5_COHERENT_INT_MASK | RX4_COHERENT_INT_MASK | \ 486 RX3_COHERENT_INT_MASK | RX2_COHERENT_INT_MASK | \ 487 RX1_COHERENT_INT_MASK | RX0_COHERENT_INT_MASK) 488 489 #define RX_COHERENT_LOW_OFFSET __ffs(RX_COHERENT_LOW_INT_MASK) 490 #define INT_RX0_MASK(_n) \ 491 (((_n) << RX_COHERENT_LOW_OFFSET) & RX_COHERENT_LOW_INT_MASK) 492 493 #define TX_COHERENT_LOW_INT_MASK \ 494 (TX7_COHERENT_INT_MASK | TX6_COHERENT_INT_MASK | \ 495 TX5_COHERENT_INT_MASK | TX4_COHERENT_INT_MASK | \ 496 TX3_COHERENT_INT_MASK | TX2_COHERENT_INT_MASK | \ 497 TX1_COHERENT_INT_MASK | TX0_COHERENT_INT_MASK) 498 499 #define TX_DONE_INT_MASK(_n) \ 500 ((_n) ? IRQ1_INT_MASK | IRQ1_FULL_INT_MASK \ 501 : IRQ0_INT_MASK | IRQ0_FULL_INT_MASK) 502 503 #define INT_TX_MASK \ 504 (IRQ1_INT_MASK | IRQ1_FULL_INT_MASK | \ 505 IRQ0_INT_MASK | IRQ0_FULL_INT_MASK) 506 507 /* QDMA_CSR_INT_ENABLE2 */ 508 #define RX15_NO_CPU_DSCP_INT_MASK BIT(31) 509 #define RX14_NO_CPU_DSCP_INT_MASK BIT(30) 510 #define RX13_NO_CPU_DSCP_INT_MASK BIT(29) 511 #define RX12_NO_CPU_DSCP_INT_MASK BIT(28) 512 #define RX11_NO_CPU_DSCP_INT_MASK BIT(27) 513 #define RX10_NO_CPU_DSCP_INT_MASK BIT(26) 514 #define RX9_NO_CPU_DSCP_INT_MASK BIT(25) 515 #define RX8_NO_CPU_DSCP_INT_MASK BIT(24) 516 #define RX7_NO_CPU_DSCP_INT_MASK BIT(23) 517 #define RX6_NO_CPU_DSCP_INT_MASK BIT(22) 518 #define RX5_NO_CPU_DSCP_INT_MASK BIT(21) 519 #define RX4_NO_CPU_DSCP_INT_MASK BIT(20) 520 #define RX3_NO_CPU_DSCP_INT_MASK BIT(19) 521 #define RX2_NO_CPU_DSCP_INT_MASK BIT(18) 522 #define RX1_NO_CPU_DSCP_INT_MASK BIT(17) 523 #define RX0_NO_CPU_DSCP_INT_MASK BIT(16) 524 #define RX15_DONE_INT_MASK BIT(15) 525 #define RX14_DONE_INT_MASK BIT(14) 526 #define RX13_DONE_INT_MASK BIT(13) 527 #define RX12_DONE_INT_MASK BIT(12) 528 #define RX11_DONE_INT_MASK BIT(11) 529 #define RX10_DONE_INT_MASK BIT(10) 530 #define RX9_DONE_INT_MASK BIT(9) 531 #define RX8_DONE_INT_MASK BIT(8) 532 #define RX7_DONE_INT_MASK BIT(7) 533 #define RX6_DONE_INT_MASK BIT(6) 534 #define RX5_DONE_INT_MASK BIT(5) 535 #define RX4_DONE_INT_MASK BIT(4) 536 #define RX3_DONE_INT_MASK BIT(3) 537 #define RX2_DONE_INT_MASK BIT(2) 538 #define RX1_DONE_INT_MASK BIT(1) 539 #define RX0_DONE_INT_MASK BIT(0) 540 541 #define RX_NO_CPU_DSCP_LOW_INT_MASK \ 542 (RX15_NO_CPU_DSCP_INT_MASK | RX14_NO_CPU_DSCP_INT_MASK | \ 543 RX13_NO_CPU_DSCP_INT_MASK | RX12_NO_CPU_DSCP_INT_MASK | \ 544 RX11_NO_CPU_DSCP_INT_MASK | RX10_NO_CPU_DSCP_INT_MASK | \ 545 RX9_NO_CPU_DSCP_INT_MASK | RX8_NO_CPU_DSCP_INT_MASK | \ 546 RX7_NO_CPU_DSCP_INT_MASK | RX6_NO_CPU_DSCP_INT_MASK | \ 547 RX5_NO_CPU_DSCP_INT_MASK | RX4_NO_CPU_DSCP_INT_MASK | \ 548 RX3_NO_CPU_DSCP_INT_MASK | RX2_NO_CPU_DSCP_INT_MASK | \ 549 RX1_NO_CPU_DSCP_INT_MASK | RX0_NO_CPU_DSCP_INT_MASK) 550 551 #define RX_DONE_LOW_INT_MASK \ 552 (RX15_DONE_INT_MASK | RX14_DONE_INT_MASK | \ 553 RX13_DONE_INT_MASK | RX12_DONE_INT_MASK | \ 554 RX11_DONE_INT_MASK | RX10_DONE_INT_MASK | \ 555 RX9_DONE_INT_MASK | RX8_DONE_INT_MASK | \ 556 RX7_DONE_INT_MASK | RX6_DONE_INT_MASK | \ 557 RX5_DONE_INT_MASK | RX4_DONE_INT_MASK | \ 558 RX3_DONE_INT_MASK | RX2_DONE_INT_MASK | \ 559 RX1_DONE_INT_MASK | RX0_DONE_INT_MASK) 560 561 #define RX_NO_CPU_DSCP_LOW_OFFSET __ffs(RX_NO_CPU_DSCP_LOW_INT_MASK) 562 #define INT_RX1_MASK(_n) \ 563 ((((_n) << RX_NO_CPU_DSCP_LOW_OFFSET) & RX_NO_CPU_DSCP_LOW_INT_MASK) | \ 564 (RX_DONE_LOW_INT_MASK & (_n))) 565 566 /* QDMA_CSR_INT_ENABLE3 */ 567 #define RX31_NO_CPU_DSCP_INT_MASK BIT(31) 568 #define RX30_NO_CPU_DSCP_INT_MASK BIT(30) 569 #define RX29_NO_CPU_DSCP_INT_MASK BIT(29) 570 #define RX28_NO_CPU_DSCP_INT_MASK BIT(28) 571 #define RX27_NO_CPU_DSCP_INT_MASK BIT(27) 572 #define RX26_NO_CPU_DSCP_INT_MASK BIT(26) 573 #define RX25_NO_CPU_DSCP_INT_MASK BIT(25) 574 #define RX24_NO_CPU_DSCP_INT_MASK BIT(24) 575 #define RX23_NO_CPU_DSCP_INT_MASK BIT(23) 576 #define RX22_NO_CPU_DSCP_INT_MASK BIT(22) 577 #define RX21_NO_CPU_DSCP_INT_MASK BIT(21) 578 #define RX20_NO_CPU_DSCP_INT_MASK BIT(20) 579 #define RX19_NO_CPU_DSCP_INT_MASK BIT(19) 580 #define RX18_NO_CPU_DSCP_INT_MASK BIT(18) 581 #define RX17_NO_CPU_DSCP_INT_MASK BIT(17) 582 #define RX16_NO_CPU_DSCP_INT_MASK BIT(16) 583 #define RX31_DONE_INT_MASK BIT(15) 584 #define RX30_DONE_INT_MASK BIT(14) 585 #define RX29_DONE_INT_MASK BIT(13) 586 #define RX28_DONE_INT_MASK BIT(12) 587 #define RX27_DONE_INT_MASK BIT(11) 588 #define RX26_DONE_INT_MASK BIT(10) 589 #define RX25_DONE_INT_MASK BIT(9) 590 #define RX24_DONE_INT_MASK BIT(8) 591 #define RX23_DONE_INT_MASK BIT(7) 592 #define RX22_DONE_INT_MASK BIT(6) 593 #define RX21_DONE_INT_MASK BIT(5) 594 #define RX20_DONE_INT_MASK BIT(4) 595 #define RX19_DONE_INT_MASK BIT(3) 596 #define RX18_DONE_INT_MASK BIT(2) 597 #define RX17_DONE_INT_MASK BIT(1) 598 #define RX16_DONE_INT_MASK BIT(0) 599 600 #define RX_NO_CPU_DSCP_HIGH_INT_MASK \ 601 (RX31_NO_CPU_DSCP_INT_MASK | RX30_NO_CPU_DSCP_INT_MASK | \ 602 RX29_NO_CPU_DSCP_INT_MASK | RX28_NO_CPU_DSCP_INT_MASK | \ 603 RX27_NO_CPU_DSCP_INT_MASK | RX26_NO_CPU_DSCP_INT_MASK | \ 604 RX25_NO_CPU_DSCP_INT_MASK | RX24_NO_CPU_DSCP_INT_MASK | \ 605 RX23_NO_CPU_DSCP_INT_MASK | RX22_NO_CPU_DSCP_INT_MASK | \ 606 RX21_NO_CPU_DSCP_INT_MASK | RX20_NO_CPU_DSCP_INT_MASK | \ 607 RX19_NO_CPU_DSCP_INT_MASK | RX18_NO_CPU_DSCP_INT_MASK | \ 608 RX17_NO_CPU_DSCP_INT_MASK | RX16_NO_CPU_DSCP_INT_MASK) 609 610 #define RX_DONE_HIGH_INT_MASK \ 611 (RX31_DONE_INT_MASK | RX30_DONE_INT_MASK | \ 612 RX29_DONE_INT_MASK | RX28_DONE_INT_MASK | \ 613 RX27_DONE_INT_MASK | RX26_DONE_INT_MASK | \ 614 RX25_DONE_INT_MASK | RX24_DONE_INT_MASK | \ 615 RX23_DONE_INT_MASK | RX22_DONE_INT_MASK | \ 616 RX21_DONE_INT_MASK | RX20_DONE_INT_MASK | \ 617 RX19_DONE_INT_MASK | RX18_DONE_INT_MASK | \ 618 RX17_DONE_INT_MASK | RX16_DONE_INT_MASK) 619 620 #define RX_DONE_HIGH_OFFSET fls(RX_DONE_HIGH_INT_MASK) 621 #define RX_DONE_INT_MASK \ 622 ((RX_DONE_HIGH_INT_MASK << RX_DONE_HIGH_OFFSET) | RX_DONE_LOW_INT_MASK) 623 624 #define INT_RX2_MASK(_n) \ 625 ((RX_NO_CPU_DSCP_HIGH_INT_MASK & (_n)) | \ 626 (((_n) >> RX_DONE_HIGH_OFFSET) & RX_DONE_HIGH_INT_MASK)) 627 628 /* QDMA_CSR_INT_ENABLE4 */ 629 #define RX31_COHERENT_INT_MASK BIT(31) 630 #define RX30_COHERENT_INT_MASK BIT(30) 631 #define RX29_COHERENT_INT_MASK BIT(29) 632 #define RX28_COHERENT_INT_MASK BIT(28) 633 #define RX27_COHERENT_INT_MASK BIT(27) 634 #define RX26_COHERENT_INT_MASK BIT(26) 635 #define RX25_COHERENT_INT_MASK BIT(25) 636 #define RX24_COHERENT_INT_MASK BIT(24) 637 #define RX23_COHERENT_INT_MASK BIT(23) 638 #define RX22_COHERENT_INT_MASK BIT(22) 639 #define RX21_COHERENT_INT_MASK BIT(21) 640 #define RX20_COHERENT_INT_MASK BIT(20) 641 #define RX19_COHERENT_INT_MASK BIT(19) 642 #define RX18_COHERENT_INT_MASK BIT(18) 643 #define RX17_COHERENT_INT_MASK BIT(17) 644 #define RX16_COHERENT_INT_MASK BIT(16) 645 646 #define RX_COHERENT_HIGH_INT_MASK \ 647 (RX31_COHERENT_INT_MASK | RX30_COHERENT_INT_MASK | \ 648 RX29_COHERENT_INT_MASK | RX28_COHERENT_INT_MASK | \ 649 RX27_COHERENT_INT_MASK | RX26_COHERENT_INT_MASK | \ 650 RX25_COHERENT_INT_MASK | RX24_COHERENT_INT_MASK | \ 651 RX23_COHERENT_INT_MASK | RX22_COHERENT_INT_MASK | \ 652 RX21_COHERENT_INT_MASK | RX20_COHERENT_INT_MASK | \ 653 RX19_COHERENT_INT_MASK | RX18_COHERENT_INT_MASK | \ 654 RX17_COHERENT_INT_MASK | RX16_COHERENT_INT_MASK) 655 656 #define INT_RX3_MASK(_n) (RX_COHERENT_HIGH_INT_MASK & (_n)) 657 658 /* QDMA_CSR_INT_ENABLE5 */ 659 #define TX31_COHERENT_INT_MASK BIT(31) 660 #define TX30_COHERENT_INT_MASK BIT(30) 661 #define TX29_COHERENT_INT_MASK BIT(29) 662 #define TX28_COHERENT_INT_MASK BIT(28) 663 #define TX27_COHERENT_INT_MASK BIT(27) 664 #define TX26_COHERENT_INT_MASK BIT(26) 665 #define TX25_COHERENT_INT_MASK BIT(25) 666 #define TX24_COHERENT_INT_MASK BIT(24) 667 #define TX23_COHERENT_INT_MASK BIT(23) 668 #define TX22_COHERENT_INT_MASK BIT(22) 669 #define TX21_COHERENT_INT_MASK BIT(21) 670 #define TX20_COHERENT_INT_MASK BIT(20) 671 #define TX19_COHERENT_INT_MASK BIT(19) 672 #define TX18_COHERENT_INT_MASK BIT(18) 673 #define TX17_COHERENT_INT_MASK BIT(17) 674 #define TX16_COHERENT_INT_MASK BIT(16) 675 #define TX15_COHERENT_INT_MASK BIT(15) 676 #define TX14_COHERENT_INT_MASK BIT(14) 677 #define TX13_COHERENT_INT_MASK BIT(13) 678 #define TX12_COHERENT_INT_MASK BIT(12) 679 #define TX11_COHERENT_INT_MASK BIT(11) 680 #define TX10_COHERENT_INT_MASK BIT(10) 681 #define TX9_COHERENT_INT_MASK BIT(9) 682 #define TX8_COHERENT_INT_MASK BIT(8) 683 684 #define TX_COHERENT_HIGH_INT_MASK \ 685 (TX31_COHERENT_INT_MASK | TX30_COHERENT_INT_MASK | \ 686 TX29_COHERENT_INT_MASK | TX28_COHERENT_INT_MASK | \ 687 TX27_COHERENT_INT_MASK | TX26_COHERENT_INT_MASK | \ 688 TX25_COHERENT_INT_MASK | TX24_COHERENT_INT_MASK | \ 689 TX23_COHERENT_INT_MASK | TX22_COHERENT_INT_MASK | \ 690 TX21_COHERENT_INT_MASK | TX20_COHERENT_INT_MASK | \ 691 TX19_COHERENT_INT_MASK | TX18_COHERENT_INT_MASK | \ 692 TX17_COHERENT_INT_MASK | TX16_COHERENT_INT_MASK | \ 693 TX15_COHERENT_INT_MASK | TX14_COHERENT_INT_MASK | \ 694 TX13_COHERENT_INT_MASK | TX12_COHERENT_INT_MASK | \ 695 TX11_COHERENT_INT_MASK | TX10_COHERENT_INT_MASK | \ 696 TX9_COHERENT_INT_MASK | TX8_COHERENT_INT_MASK) 697 698 #define REG_TX_IRQ_BASE(_n) ((_n) ? 0x0048 : 0x0050) 699 700 #define REG_TX_IRQ_CFG(_n) ((_n) ? 0x004c : 0x0054) 701 #define TX_IRQ_THR_MASK GENMASK(27, 16) 702 #define TX_IRQ_DEPTH_MASK GENMASK(11, 0) 703 704 #define REG_IRQ_CLEAR_LEN(_n) ((_n) ? 0x0064 : 0x0058) 705 #define IRQ_CLEAR_LEN_MASK GENMASK(7, 0) 706 707 #define REG_IRQ_STATUS(_n) ((_n) ? 0x0068 : 0x005c) 708 #define IRQ_ENTRY_LEN_MASK GENMASK(27, 16) 709 #define IRQ_HEAD_IDX_MASK GENMASK(11, 0) 710 711 #define REG_TX_RING_BASE(_n) \ 712 (((_n) < 8) ? 0x0100 + ((_n) << 5) : 0x0b00 + (((_n) - 8) << 5)) 713 714 #define REG_TX_RING_BLOCKING(_n) \ 715 (((_n) < 8) ? 0x0104 + ((_n) << 5) : 0x0b04 + (((_n) - 8) << 5)) 716 717 #define TX_RING_IRQ_BLOCKING_MAP_MASK BIT(6) 718 #define TX_RING_IRQ_BLOCKING_CFG_MASK BIT(4) 719 #define TX_RING_IRQ_BLOCKING_TX_DROP_EN_MASK BIT(2) 720 #define TX_RING_IRQ_BLOCKING_MAX_TH_TXRING_EN_MASK BIT(1) 721 #define TX_RING_IRQ_BLOCKING_MIN_TH_TXRING_EN_MASK BIT(0) 722 723 #define REG_TX_CPU_IDX(_n) \ 724 (((_n) < 8) ? 0x0108 + ((_n) << 5) : 0x0b08 + (((_n) - 8) << 5)) 725 726 #define TX_RING_CPU_IDX_MASK GENMASK(15, 0) 727 728 #define REG_TX_DMA_IDX(_n) \ 729 (((_n) < 8) ? 0x010c + ((_n) << 5) : 0x0b0c + (((_n) - 8) << 5)) 730 731 #define TX_RING_DMA_IDX_MASK GENMASK(15, 0) 732 733 #define IRQ_RING_IDX_MASK GENMASK(20, 16) 734 #define IRQ_DESC_IDX_MASK GENMASK(15, 0) 735 736 #define REG_RX_RING_BASE(_n) \ 737 (((_n) < 16) ? 0x0200 + ((_n) << 5) : 0x0e00 + (((_n) - 16) << 5)) 738 739 #define REG_RX_RING_SIZE(_n) \ 740 (((_n) < 16) ? 0x0204 + ((_n) << 5) : 0x0e04 + (((_n) - 16) << 5)) 741 742 #define RX_RING_THR_MASK GENMASK(31, 16) 743 #define RX_RING_SIZE_MASK GENMASK(15, 0) 744 745 #define REG_RX_CPU_IDX(_n) \ 746 (((_n) < 16) ? 0x0208 + ((_n) << 5) : 0x0e08 + (((_n) - 16) << 5)) 747 748 #define RX_RING_CPU_IDX_MASK GENMASK(15, 0) 749 750 #define REG_RX_DMA_IDX(_n) \ 751 (((_n) < 16) ? 0x020c + ((_n) << 5) : 0x0e0c + (((_n) - 16) << 5)) 752 753 #define REG_RX_DELAY_INT_IDX(_n) \ 754 (((_n) < 16) ? 0x0210 + ((_n) << 5) : 0x0e10 + (((_n) - 16) << 5)) 755 756 #define REG_RX_SCATTER_CFG(_n) \ 757 (((_n) < 16) ? 0x0214 + ((_n) << 5) : 0x0e14 + (((_n) - 16) << 5)) 758 759 #define RX_DELAY_INT_MASK GENMASK(15, 0) 760 761 #define RX_RING_DMA_IDX_MASK GENMASK(15, 0) 762 763 #define RX_RING_SG_EN_MASK BIT(0) 764 765 #define REG_INGRESS_TRTCM_CFG 0x0070 766 #define INGRESS_TRTCM_EN_MASK BIT(31) 767 #define INGRESS_TRTCM_MODE_MASK BIT(30) 768 #define INGRESS_SLOW_TICK_RATIO_MASK GENMASK(29, 16) 769 #define INGRESS_FAST_TICK_MASK GENMASK(15, 0) 770 771 #define REG_QUEUE_CLOSE_CFG(_n) (0x00a0 + ((_n) & 0xfc)) 772 #define TXQ_DISABLE_CHAN_QUEUE_MASK(_n, _m) BIT((_m) + (((_n) & 0x3) << 3)) 773 774 #define REG_TXQ_DIS_CFG_BASE(_n) ((_n) ? 0x20a0 : 0x00a0) 775 #define REG_TXQ_DIS_CFG(_n, _m) (REG_TXQ_DIS_CFG_BASE((_n)) + (_m) << 2) 776 777 #define REG_CNTR_CFG(_n) (0x0400 + ((_n) << 3)) 778 #define CNTR_EN_MASK BIT(31) 779 #define CNTR_ALL_CHAN_EN_MASK BIT(30) 780 #define CNTR_ALL_QUEUE_EN_MASK BIT(29) 781 #define CNTR_ALL_DSCP_RING_EN_MASK BIT(28) 782 #define CNTR_SRC_MASK GENMASK(27, 24) 783 #define CNTR_DSCP_RING_MASK GENMASK(20, 16) 784 #define CNTR_CHAN_MASK GENMASK(7, 3) 785 #define CNTR_QUEUE_MASK GENMASK(2, 0) 786 787 #define REG_CNTR_VAL(_n) (0x0404 + ((_n) << 3)) 788 789 #define REG_LMGR_INIT_CFG 0x1000 790 #define LMGR_INIT_START BIT(31) 791 #define LMGR_SRAM_MODE_MASK BIT(30) 792 #define HW_FWD_PKTSIZE_OVERHEAD_MASK GENMASK(27, 20) 793 #define HW_FWD_DESC_NUM_MASK GENMASK(16, 0) 794 795 #define REG_FWD_DSCP_LOW_THR 0x1004 796 #define FWD_DSCP_LOW_THR_MASK GENMASK(17, 0) 797 798 #define REG_EGRESS_RATE_METER_CFG 0x100c 799 #define EGRESS_RATE_METER_EN_MASK BIT(31) 800 #define EGRESS_RATE_METER_EQ_RATE_EN_MASK BIT(17) 801 #define EGRESS_RATE_METER_WINDOW_SZ_MASK GENMASK(16, 12) 802 #define EGRESS_RATE_METER_TIMESLICE_MASK GENMASK(10, 0) 803 804 #define REG_EGRESS_TRTCM_CFG 0x1010 805 #define EGRESS_TRTCM_EN_MASK BIT(31) 806 #define EGRESS_TRTCM_MODE_MASK BIT(30) 807 #define EGRESS_SLOW_TICK_RATIO_MASK GENMASK(29, 16) 808 #define EGRESS_FAST_TICK_MASK GENMASK(15, 0) 809 810 #define TRTCM_PARAM_RW_MASK BIT(31) 811 #define TRTCM_PARAM_RW_DONE_MASK BIT(30) 812 #define TRTCM_PARAM_TYPE_MASK GENMASK(29, 28) 813 #define TRTCM_METER_GROUP_MASK GENMASK(27, 26) 814 #define TRTCM_PARAM_INDEX_MASK GENMASK(23, 17) 815 #define TRTCM_PARAM_RATE_TYPE_MASK BIT(16) 816 817 #define REG_TRTCM_CFG_PARAM(_n) ((_n) + 0x4) 818 #define REG_TRTCM_DATA_LOW(_n) ((_n) + 0x8) 819 #define REG_TRTCM_DATA_HIGH(_n) ((_n) + 0xc) 820 821 #define RATE_LIMIT_PARAM_RW_MASK BIT(31) 822 #define RATE_LIMIT_PARAM_RW_DONE_MASK BIT(30) 823 #define RATE_LIMIT_PARAM_TYPE_MASK GENMASK(29, 28) 824 #define RATE_LIMIT_METER_GROUP_MASK GENMASK(27, 26) 825 #define RATE_LIMIT_PARAM_INDEX_MASK GENMASK(23, 16) 826 827 #define REG_TXWRR_MODE_CFG 0x1020 828 #define TWRR_WEIGHT_SCALE_MASK BIT(31) 829 #define TWRR_WEIGHT_BASE_MASK BIT(3) 830 831 #define REG_TXWRR_WEIGHT_CFG 0x1024 832 #define TWRR_RW_CMD_MASK BIT(31) 833 #define TWRR_RW_CMD_DONE BIT(30) 834 #define TWRR_CHAN_IDX_MASK GENMASK(23, 19) 835 #define TWRR_QUEUE_IDX_MASK GENMASK(18, 16) 836 #define TWRR_VALUE_MASK GENMASK(15, 0) 837 838 #define REG_PSE_BUF_USAGE_CFG 0x1028 839 #define PSE_BUF_ESTIMATE_EN_MASK BIT(29) 840 841 #define REG_CHAN_QOS_MODE(_n) (0x1040 + ((_n) << 2)) 842 #define CHAN_QOS_MODE_MASK(_n) GENMASK(2 + ((_n) << 2), (_n) << 2) 843 844 #define REG_GLB_TRTCM_CFG 0x1080 845 #define GLB_TRTCM_EN_MASK BIT(31) 846 #define GLB_TRTCM_MODE_MASK BIT(30) 847 #define GLB_SLOW_TICK_RATIO_MASK GENMASK(29, 16) 848 #define GLB_FAST_TICK_MASK GENMASK(15, 0) 849 850 #define REG_TXQ_CNGST_CFG 0x10a0 851 #define TXQ_CNGST_DROP_EN BIT(31) 852 #define TXQ_CNGST_DEI_DROP_EN BIT(30) 853 854 #define REG_SLA_TRTCM_CFG 0x1150 855 #define SLA_TRTCM_EN_MASK BIT(31) 856 #define SLA_TRTCM_MODE_MASK BIT(30) 857 #define SLA_SLOW_TICK_RATIO_MASK GENMASK(29, 16) 858 #define SLA_FAST_TICK_MASK GENMASK(15, 0) 859 860 /* CTRL */ 861 #define QDMA_DESC_DONE_MASK BIT(31) 862 #define QDMA_DESC_DROP_MASK BIT(30) /* tx: drop - rx: overflow */ 863 #define QDMA_DESC_MORE_MASK BIT(29) /* more SG elements */ 864 #define QDMA_DESC_DEI_MASK BIT(25) 865 #define QDMA_DESC_NO_DROP_MASK BIT(24) 866 #define QDMA_DESC_LEN_MASK GENMASK(15, 0) 867 /* DATA */ 868 #define QDMA_DESC_NEXT_ID_MASK GENMASK(15, 0) 869 /* TX MSG0 */ 870 #define QDMA_ETH_TXMSG_MIC_IDX_MASK BIT(30) 871 #define QDMA_ETH_TXMSG_SP_TAG_MASK GENMASK(29, 14) 872 #define QDMA_ETH_TXMSG_ICO_MASK BIT(13) 873 #define QDMA_ETH_TXMSG_UCO_MASK BIT(12) 874 #define QDMA_ETH_TXMSG_TCO_MASK BIT(11) 875 #define QDMA_ETH_TXMSG_TSO_MASK BIT(10) 876 #define QDMA_ETH_TXMSG_FAST_MASK BIT(9) 877 #define QDMA_ETH_TXMSG_OAM_MASK BIT(8) 878 #define QDMA_ETH_TXMSG_CHAN_MASK GENMASK(7, 3) 879 #define QDMA_ETH_TXMSG_QUEUE_MASK GENMASK(2, 0) 880 /* TX MSG1 */ 881 #define QDMA_ETH_TXMSG_NO_DROP BIT(31) 882 #define QDMA_ETH_TXMSG_METER_MASK GENMASK(30, 24) /* 0x7f no meters */ 883 #define QDMA_ETH_TXMSG_FPORT_MASK GENMASK(23, 20) 884 #define QDMA_ETH_TXMSG_NBOQ_MASK GENMASK(19, 15) 885 #define QDMA_ETH_TXMSG_HWF_MASK BIT(14) 886 #define QDMA_ETH_TXMSG_HOP_MASK BIT(13) 887 #define QDMA_ETH_TXMSG_PTP_MASK BIT(12) 888 #define QDMA_ETH_TXMSG_ACNT_G1_MASK GENMASK(10, 6) /* 0x1f do not count */ 889 #define QDMA_ETH_TXMSG_ACNT_G0_MASK GENMASK(5, 0) /* 0x3f do not count */ 890 891 /* RX MSG0 */ 892 #define QDMA_ETH_RXMSG_SPTAG GENMASK(21, 14) 893 /* RX MSG1 */ 894 #define QDMA_ETH_RXMSG_DEI_MASK BIT(31) 895 #define QDMA_ETH_RXMSG_IP6_MASK BIT(30) 896 #define QDMA_ETH_RXMSG_IP4_MASK BIT(29) 897 #define QDMA_ETH_RXMSG_IP4F_MASK BIT(28) 898 #define QDMA_ETH_RXMSG_L4_VALID_MASK BIT(27) 899 #define QDMA_ETH_RXMSG_L4F_MASK BIT(26) 900 #define QDMA_ETH_RXMSG_SPORT_MASK GENMASK(25, 21) 901 #define QDMA_ETH_RXMSG_CRSN_MASK GENMASK(20, 16) 902 #define QDMA_ETH_RXMSG_PPE_ENTRY_MASK GENMASK(15, 0) 903 904 struct airoha_qdma_desc { 905 __le32 rsv; 906 __le32 ctrl; 907 __le32 addr; 908 __le32 data; 909 __le32 msg0; 910 __le32 msg1; 911 __le32 msg2; 912 __le32 msg3; 913 }; 914 915 /* CTRL0 */ 916 #define QDMA_FWD_DESC_CTX_MASK BIT(31) 917 #define QDMA_FWD_DESC_RING_MASK GENMASK(30, 28) 918 #define QDMA_FWD_DESC_IDX_MASK GENMASK(27, 16) 919 #define QDMA_FWD_DESC_LEN_MASK GENMASK(15, 0) 920 /* CTRL1 */ 921 #define QDMA_FWD_DESC_FIRST_IDX_MASK GENMASK(15, 0) 922 /* CTRL2 */ 923 #define QDMA_FWD_DESC_MORE_PKT_NUM_MASK GENMASK(2, 0) 924 925 struct airoha_qdma_fwd_desc { 926 __le32 addr; 927 __le32 ctrl0; 928 __le32 ctrl1; 929 __le32 ctrl2; 930 __le32 msg0; 931 __le32 msg1; 932 __le32 rsv0; 933 __le32 rsv1; 934 }; 935 936 #endif /* AIROHA_REGS_H */ 937