1/*- 2 * Copyright (c) 2012-2014 Andrew Turner 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include "assym.inc" 28#include "opt_kstack_pages.h" 29#include <sys/elf_common.h> 30#include <sys/syscall.h> 31#include <machine/asm.h> 32#include <machine/armreg.h> 33#include <machine/cpu.h> 34#include <machine/hypervisor.h> 35#include <machine/param.h> 36#include <machine/pte.h> 37#include <machine/vm.h> 38#include <machine/vmparam.h> 39 40#define VIRT_BITS 48 41 42#if PAGE_SIZE == PAGE_SIZE_16K 43/* 44 * The number of level 3 tables to create. 32 will allow for 1G of address 45 * space, the same as a single level 2 page with 4k pages. 46 */ 47#define L3_PAGE_COUNT 32 48#endif 49 50/* 51 * The size of our bootstrap stack. 52 */ 53#define BOOT_STACK_SIZE (KSTACK_PAGES * PAGE_SIZE) 54 55 .globl kernbase 56 .set kernbase, KERNBASE 57 58/* 59 * We assume: 60 * MMU on with an identity map, or off 61 * D-Cache: off 62 * I-Cache: on or off 63 * We are loaded at a 2MiB aligned address 64 */ 65 66ENTRY(_start) 67 /* Enter the kernel exception level */ 68 bl enter_kernel_el 69 70 /* Set the context id */ 71 msr contextidr_el1, xzr 72 73 /* Get the virt -> phys offset */ 74 bl get_load_phys_addr 75 76 /* 77 * At this point: 78 * x28 = Our physical load address 79 */ 80 81 /* Create the page tables */ 82 bl create_pagetables 83 84 /* 85 * At this point: 86 * x27 = TTBR0 table 87 * x26 = Kernel L1 table 88 * x24 = TTBR1 table 89 * x22 = PTE shareability attributes 90 */ 91 92 /* Enable the mmu */ 93 bl start_mmu 94 95 /* Load the new ttbr0 pagetable */ 96 adrp x27, pagetable_l0_ttbr0 97 add x27, x27, :lo12:pagetable_l0_ttbr0 98 99 /* Jump to the virtual address space */ 100 ldr x15, .Lvirtdone 101 br x15 102 103virtdone: 104 BTI_J 105 106 /* Set up the stack */ 107 adrp x25, initstack_end 108 add x25, x25, :lo12:initstack_end 109 sub sp, x25, #PCB_SIZE 110 111 /* Zero the BSS */ 112 ldr x15, .Lbss 113 ldr x14, .Lend 1141: 115 stp xzr, xzr, [x15], #16 116 cmp x15, x14 117 b.lo 1b 118 119#if defined(PERTHREAD_SSP) 120 /* Set sp_el0 to the boot canary for early per-thread SSP to work */ 121 adrp x15, boot_canary 122 add x15, x15, :lo12:boot_canary 123 msr sp_el0, x15 124#endif 125 126 /* Backup the module pointer */ 127 mov x1, x0 128 129 sub sp, sp, #BOOTPARAMS_SIZE 130 mov x0, sp 131 132 str x1, [x0, #BP_MODULEP] 133 adrp x25, initstack 134 add x25, x25, :lo12:initstack 135 str x25, [x0, #BP_KERN_STACK] 136 str x27, [x0, #BP_KERN_TTBR0] 137 str x23, [x0, #BP_BOOT_EL] 138 139 /* Set this before it's used in kasan_init_early */ 140 adrp x1, pmap_sh_attr 141 str x22, [x1, :lo12:pmap_sh_attr] 142 143#ifdef KASAN 144 /* Save bootparams */ 145 mov x19, x0 146 147 /* Bootstrap an early shadow map for the boot stack. */ 148 ldr x0, [x0, #BP_KERN_STACK] 149 ldr x1, =BOOT_STACK_SIZE 150 bl kasan_init_early 151 152 /* Restore bootparams */ 153 mov x0, x19 154#endif 155 156 /* trace back starts here */ 157 mov fp, #0 158 /* Branch to C code */ 159 bl initarm 160 /* We are done with the boot params */ 161 add sp, sp, #BOOTPARAMS_SIZE 162 163 /* 164 * Enable pointer authentication in the kernel. We set the keys for 165 * thread0 in initarm so have to wait until it returns to enable it. 166 * If we were to enable it in initarm then any authentication when 167 * returning would fail as it was called with pointer authentication 168 * disabled. 169 */ 170 bl ptrauth_start 171 172 bl mi_startup 173 174 /* We should not get here */ 175 brk 0 176 177 .align 3 178.Lvirtdone: 179 .quad virtdone 180.Lbss: 181 .quad __bss_start 182.Lend: 183 .quad __bss_end 184END(_start) 185 186#ifdef SMP 187/* 188 * void 189 * mpentry_psci(unsigned long) 190 * 191 * Called by a core when it is being brought online with psci. 192 * The data in x0 is passed straight to init_secondary. 193 */ 194ENTRY(mpentry_psci) 195 mov x26, xzr 196 b mpentry_common 197END(mpentry_psci) 198 199/* 200 * void 201 * mpentry_spintable(void) 202 * 203 * Called by a core when it is being brought online with a spin-table. 204 * Reads the new CPU ID and passes this to init_secondary. 205 */ 206ENTRY(mpentry_spintable) 207 ldr x26, =spintable_wait 208 b mpentry_common 209END(mpentry_spintable) 210 211/* Wait for the current CPU to be released */ 212LENTRY(spintable_wait) 213 /* Read the affinity bits from mpidr_el1 */ 214 mrs x1, mpidr_el1 215 ldr x2, =CPU_AFF_MASK 216 and x1, x1, x2 217 218 adrp x2, ap_cpuid 2191: 220 ldr x0, [x2, :lo12:ap_cpuid] 221 cmp x0, x1 222 b.ne 1b 223 224 str xzr, [x2, :lo12:ap_cpuid] 225 dsb sy 226 sev 227 228 ret 229LEND(mpentry_spintable) 230 231LENTRY(mpentry_common) 232 /* Disable interrupts */ 233 msr daifset, #DAIF_INTR 234 235 /* Enter the kernel exception level */ 236 bl enter_kernel_el 237 238 /* Set the context id */ 239 msr contextidr_el1, xzr 240 241 /* Load the kernel page table */ 242 adrp x24, pagetable_l0_ttbr1 243 add x24, x24, :lo12:pagetable_l0_ttbr1 244 /* Load the identity page table */ 245 adrp x27, pagetable_l0_ttbr0_bootstrap 246 add x27, x27, :lo12:pagetable_l0_ttbr0_bootstrap 247 248 /* Enable the mmu */ 249 bl start_mmu 250 251 /* Load the new ttbr0 pagetable */ 252 adrp x27, pagetable_l0_ttbr0 253 add x27, x27, :lo12:pagetable_l0_ttbr0 254 255 /* Jump to the virtual address space */ 256 ldr x15, =mp_virtdone 257 br x15 258 259mp_virtdone: 260 BTI_J 261 262 /* 263 * Allow this CPU to wait until the kernel is ready for it, 264 * e.g. with spin-table but each CPU uses the same release address 265 */ 266 cbz x26, 1f 267 blr x26 2681: 269 270 /* Start using the AP boot stack */ 271 adrp x4, bootstack 272 ldr x4, [x4, :lo12:bootstack] 273 mov sp, x4 274 275#if defined(PERTHREAD_SSP) 276 /* Set sp_el0 to the boot canary for early per-thread SSP to work */ 277 adrp x15, boot_canary 278 add x15, x15, :lo12:boot_canary 279 msr sp_el0, x15 280#endif 281 282 /* Load the kernel ttbr0 pagetable */ 283 msr ttbr0_el1, x27 284 isb 285 286 /* Invalidate the TLB */ 287 tlbi vmalle1 288 dsb sy 289 isb 290 291 /* 292 * Initialize the per-CPU pointer before calling into C code, for the 293 * benefit of kernel sanitizers. 294 */ 295 adrp x18, bootpcpu 296 ldr x18, [x18, :lo12:bootpcpu] 297 msr tpidr_el1, x18 298 299 b init_secondary 300LEND(mpentry_common) 301#endif 302 303/* 304 * Enter the exception level the kernel will use: 305 * 306 * - If in EL1 continue in EL1 307 * - If the CPU supports FEAT_VHE then set HCR_E2H and HCR_TGE and continue 308 * in EL2 309 * - Configure EL2 to support running the kernel at EL1 and exit to that 310 */ 311LENTRY(enter_kernel_el) 312#define INIT_SCTLR_EL1 (SCTLR_LSMAOE | SCTLR_nTLSMD | SCTLR_EIS | \ 313 SCTLR_TSCXT | SCTLR_EOS) 314 mrs x23, CurrentEL 315 and x23, x23, #(CURRENTEL_EL_MASK) 316 cmp x23, #(CURRENTEL_EL_EL2) 317 b.eq 1f 318 319 ldr x2, =INIT_SCTLR_EL1 320 msr sctlr_el1, x2 321 /* SCTLR_EOS is set so eret is a context synchronizing event so we 322 * need an isb here to ensure it's observed by later instructions, 323 * but don't need it in the eret below. 324 */ 325 isb 326 327 /* Ensure SPSR_EL1 and pstate are in sync. The only wat to set the 328 * latter is to set the former and return from an exception with eret. 329 */ 330 mov x2, #(PSR_DAIF | PSR_M_EL1h) 331 msr spsr_el1, x2 332 msr elr_el1, lr 333 eret 334 3351: 336 dsb sy 337 /* 338 * Set just the reserved bits in sctlr_el2. This will disable the 339 * MMU which may have broken the kernel if we enter the kernel in 340 * EL2, e.g. when using VHE. 341 */ 342 ldr x2, =(SCTLR_EL2_RES1 | SCTLR_EL2_EIS | SCTLR_EL2_EOS) 343 msr sctlr_el2, x2 344 isb 345 346 /* Configure the Hypervisor */ 347 ldr x2, =(HCR_RW | HCR_APK | HCR_API | HCR_E2H) 348 msr hcr_el2, x2 349 350 /* Stash value of HCR_EL2 for later */ 351 isb 352 mrs x4, hcr_el2 353 354 /* Load the Virtualization Process ID Register */ 355 mrs x2, midr_el1 356 msr vpidr_el2, x2 357 358 /* Load the Virtualization Multiprocess ID Register */ 359 mrs x2, mpidr_el1 360 msr vmpidr_el2, x2 361 362 /* Set the initial sctlr_el1 */ 363 ldr x2, =INIT_SCTLR_EL1 364 msr sctlr_el1, x2 365 366 /* Check if the E2H flag is set */ 367 tst x4, #HCR_E2H 368 b.eq .Lno_vhe 369 370 /* 371 * The kernel will be running in EL2, route exceptions here rather 372 * than EL1. 373 */ 374 orr x4, x4, #(HCR_TGE) 375 msr hcr_el2, x4 376 isb 377 378 msr SCTLR_EL12_REG, x2 379 mov x2, xzr /* CPTR_EL2 is managed by vfp.c */ 380 ldr x3, =(CNTHCTL_E2H_EL1PCTEN | CNTHCTL_E2H_EL1PTEN) 381 ldr x5, =(PSR_DAIF | PSR_M_EL2h) 382 b .Ldone_vhe 383 384.Lno_vhe: 385 /* Hypervisor trap functions */ 386 adrp x2, hyp_stub_vectors 387 add x2, x2, :lo12:hyp_stub_vectors 388 msr vbar_el2, x2 389 390 ldr x2, =(CPTR_RES1) 391 ldr x3, =(CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN) 392 ldr x5, =(PSR_DAIF | PSR_M_EL1h) 393 394.Ldone_vhe: 395 396 msr cptr_el2, x2 397 /* Enable access to the physical timers at EL1 */ 398 msr cnthctl_el2, x3 399 /* Set the return PSTATE */ 400 msr spsr_el2, x5 401 402 /* 403 * Configure the Extended Hypervisor register. This is only valid if 404 * FEAT_HCX is enabled. 405 */ 406 CHECK_CPU_FEAT(x2, ID_AA64MMFR1, HCX, 2f) 407 /* Extended Hypervisor Configuration */ 408 mov x2, xzr 409 msr HCRX_EL2_REG, x2 410 isb 4112: 412 413 /* Don't trap to EL2 for CP15 traps */ 414 msr hstr_el2, xzr 415 416 /* Set the counter offset to a known value */ 417 msr cntvoff_el2, xzr 418 419 /* Zero vttbr_el2 so a hypervisor can tell the host and guest apart */ 420 msr vttbr_el2, xzr 421 422 /* Check the CPU supports GIC, and configure the CPU interface */ 423 CHECK_CPU_FEAT(x2, ID_AA64PFR0, GIC, 3f) 424 425 mrs x2, icc_sre_el2 426 orr x2, x2, #ICC_SRE_EL2_EN /* Enable access from insecure EL1 */ 427 orr x2, x2, #ICC_SRE_EL2_SRE /* Enable system registers */ 428 msr icc_sre_el2, x2 4293: 430 431 /* Set the address to return to our return address */ 432 msr elr_el2, x30 433 isb 434 435 eret 436#undef INIT_SCTLR_EL1 437LEND(enter_kernel_el) 438 439/* 440 * Get the physical address the kernel was loaded at. 441 */ 442LENTRY(get_load_phys_addr) 443 /* Load the offset of get_load_phys_addr from KERNBASE */ 444 ldr x28, =(get_load_phys_addr - KERNBASE) 445 /* Load the physical address of get_load_phys_addr */ 446 adr x29, get_load_phys_addr 447 /* Find the physical address of KERNBASE, i.e. our load address */ 448 sub x28, x29, x28 449 ret 450LEND(get_load_phys_addr) 451 452/* 453 * This builds the page tables containing the identity map, and the kernel 454 * virtual map. 455 * 456 * It relys on: 457 * We were loaded to an address that is on a 2MiB boundary 458 * All the memory must not cross a 1GiB boundaty 459 * x28 contains the physical address we were loaded from 460 * 461 * There are 7 or 8 pages before that address for the page tables 462 * The pages used are: 463 * - The Kernel L3 tables (only for 16k kernel) 464 * - The Kernel L2 table 465 * - The Kernel L1 table 466 * - The Kernel L0 table (TTBR1) 467 * - The identity (PA = VA) L2 table 468 * - The identity (PA = VA) L1 table 469 * - The identity (PA = VA) L0 table (Early TTBR0) 470 * - The Kernel empty L0 table (Late TTBR0) 471 */ 472LENTRY(create_pagetables) 473 /* Save the Link register */ 474 mov x5, x30 475 476 /* Clean the page table */ 477 adrp x6, pagetable 478 add x6, x6, :lo12:pagetable 479 mov x26, x6 480 adrp x27, pagetable_end 481 add x27, x27, :lo12:pagetable_end 4821: 483 stp xzr, xzr, [x6], #16 484 stp xzr, xzr, [x6], #16 485 stp xzr, xzr, [x6], #16 486 stp xzr, xzr, [x6], #16 487 cmp x6, x27 488 b.lo 1b 489 490 /* 491 * Find the shareability attribute we should use. If FEAT_LPA2 is 492 * enabled then the shareability field is moved from the page table 493 * to tcr_el1 and the bits in the page table are reused by the 494 * address field. 495 */ 496#if PAGE_SIZE == PAGE_SIZE_4K 497#define LPA2_MASK ID_AA64MMFR0_TGran4_MASK 498#define LPA2_VAL ID_AA64MMFR0_TGran4_LPA2 499#elif PAGE_SIZE == PAGE_SIZE_16K 500#define LPA2_MASK ID_AA64MMFR0_TGran16_MASK 501#define LPA2_VAL ID_AA64MMFR0_TGran16_LPA2 502#else 503#error Unsupported page size 504#endif 505 mrs x6, id_aa64mmfr0_el1 506 mov x7, LPA2_VAL 507 and x6, x6, LPA2_MASK 508 cmp x6, x7 509 ldr x22, =(ATTR_SH(ATTR_SH_IS)) 510 csel x22, xzr, x22, eq 511#undef LPA2_MASK 512#undef LPA2_VAL 513 514 /* 515 * Build the TTBR1 maps. 516 */ 517 518 /* Find the size of the kernel */ 519 mov x6, #(KERNBASE) 520 521#if defined(LINUX_BOOT_ABI) 522 /* X19 is used as 'map FDT data' flag */ 523 mov x19, xzr 524 525 /* No modules or FDT pointer ? */ 526 cbz x0, booti_no_fdt 527 528 /* 529 * Test if x0 points to modules descriptor(virtual address) or 530 * to FDT (physical address) 531 */ 532 cmp x0, x6 /* x6 is #(KERNBASE) */ 533 b.lo booti_fdt 534#endif 535 536 /* Booted with modules pointer */ 537 /* Find modulep - begin */ 538 sub x8, x0, x6 539 /* 540 * Add space for the module data. When PAGE_SIZE is 4k this will 541 * add at least 2 level 2 blocks (2 * 2MiB). When PAGE_SIZE is 542 * larger it will be at least as large as we use smaller level 3 543 * pages. 544 */ 545 ldr x7, =((6 * 1024 * 1024) - 1) 546 add x8, x8, x7 547 b common 548 549#if defined(LINUX_BOOT_ABI) 550booti_fdt: 551 /* Booted by U-Boot booti with FDT data */ 552 /* Set 'map FDT data' flag */ 553 mov x19, #1 554 555booti_no_fdt: 556 /* Booted by U-Boot booti without FTD data */ 557 /* Find the end - begin */ 558 ldr x7, .Lend 559 sub x8, x7, x6 560 561 /* 562 * Add one 2MiB page for copy of FDT data (maximum FDT size), 563 * one for metadata and round up 564 */ 565 ldr x7, =(3 * L2_SIZE - 1) 566 add x8, x8, x7 567#endif 568 569common: 570#if PAGE_SIZE != PAGE_SIZE_4K 571 /* 572 * Create L3 and L3C pages. The kernel will be loaded at a 2M aligned 573 * address, enabling the creation of L3C pages. However, when the page 574 * size is larger than 4k, L2 blocks are too large to map the kernel 575 * with 2M alignment. 576 */ 577#define PTE_SHIFT L3_SHIFT 578#define BUILD_PTE_FUNC build_l3_page_pagetable 579#else 580#define PTE_SHIFT L2_SHIFT 581#define BUILD_PTE_FUNC build_l2_block_pagetable 582#endif 583 584 /* Get the number of blocks/pages to allocate, rounded down */ 585 lsr x10, x8, #(PTE_SHIFT) 586 587 /* Create the kernel space PTE table */ 588 mov x6, x26 589 mov x7, #(ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK)) 590 mov x8, #(KERNBASE) 591 mov x9, x28 592 bl BUILD_PTE_FUNC 593 594#undef PTE_SHIFT 595#undef BUILD_PTE_FUNC 596 597#if PAGE_SIZE != PAGE_SIZE_4K 598 /* Move to the l2 table */ 599 ldr x9, =(PAGE_SIZE * L3_PAGE_COUNT) 600 add x26, x26, x9 601 602 /* Link the l2 -> l3 table */ 603 mov x9, x6 604 mov x6, x26 605 bl link_l2_pagetable 606#endif 607 608 /* Move to the l1 table */ 609 add x26, x26, #PAGE_SIZE 610 611 /* Link the l1 -> l2 table */ 612 mov x9, x6 613 mov x6, x26 614 bl link_l1_pagetable 615 616 /* Move to the l0 table */ 617 add x24, x26, #PAGE_SIZE 618 619 /* Link the l0 -> l1 table */ 620 mov x9, x6 621 mov x6, x24 622 mov x10, #1 623 bl link_l0_pagetable 624 625 /* 626 * Build the TTBR0 maps. As TTBR0 maps, they must specify ATTR_S1_nG. 627 * They are only needed early on, so the VA = PA map is uncached. 628 */ 629 add x27, x24, #PAGE_SIZE 630 631 mov x6, x27 /* The initial page table */ 632 633 /* Create the VA = PA map */ 634 mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK)) 635 adrp x16, _start 636 and x16, x16, #(~L2_OFFSET) 637 mov x9, x16 /* PA start */ 638 mov x8, x16 /* VA start (== PA start) */ 639 mov x10, #1 640 bl build_l2_block_pagetable 641 642#if defined(SOCDEV_PA) 643 /* Create a table for the UART */ 644 mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_DEVICE)) 645 ldr x9, =(L2_SIZE) 646 add x16, x16, x9 /* VA start */ 647 mov x8, x16 648 649 /* Store the socdev virtual address */ 650 add x17, x8, #(SOCDEV_PA & L2_OFFSET) 651 adrp x9, socdev_va 652 str x17, [x9, :lo12:socdev_va] 653 654 mov x9, #(SOCDEV_PA & ~L2_OFFSET) /* PA start */ 655 mov x10, #1 656 bl build_l2_block_pagetable 657#endif 658 659#if defined(LINUX_BOOT_ABI) 660 /* Map FDT data ? */ 661 cbz x19, 1f 662 663 /* Create the mapping for FDT data (2 MiB max) */ 664 mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK)) 665 ldr x9, =(L2_SIZE) 666 add x16, x16, x9 /* VA start */ 667 mov x8, x16 668 mov x9, x0 /* PA start */ 669 /* Update the module pointer to point at the allocated memory */ 670 and x0, x0, #(L2_OFFSET) /* Keep the lower bits */ 671 add x0, x0, x8 /* Add the aligned virtual address */ 672 673 mov x10, #1 674 bl build_l2_block_pagetable 675 6761: 677#endif 678 679 /* Move to the l1 table */ 680 add x27, x27, #PAGE_SIZE 681 682 /* Link the l1 -> l2 table */ 683 mov x9, x6 684 mov x6, x27 685 bl link_l1_pagetable 686 687 /* Move to the l0 table */ 688 add x27, x27, #PAGE_SIZE 689 690 /* Link the l0 -> l1 table */ 691 mov x9, x6 692 mov x6, x27 693 mov x10, #1 694 bl link_l0_pagetable 695 696 /* Restore the Link register */ 697 mov x30, x5 698 ret 699LEND(create_pagetables) 700 701/* 702 * Builds an L0 -> L1 table descriptor 703 * 704 * x6 = L0 table 705 * x8 = Virtual Address 706 * x9 = L1 PA (trashed) 707 * x10 = Entry count (trashed) 708 * x11, x12 and x13 are trashed 709 */ 710LENTRY(link_l0_pagetable) 711 /* 712 * Link an L0 -> L1 table entry. 713 */ 714 /* Find the table index */ 715 lsr x11, x8, #L0_SHIFT 716 and x11, x11, #L0_ADDR_MASK 717 718 /* Build the L0 block entry */ 719 mov x12, #L0_TABLE 720 orr x12, x12, #(TATTR_UXN_TABLE | TATTR_AP_TABLE_NO_EL0) 721 722 /* Only use the output address bits */ 723 lsr x9, x9, #PAGE_SHIFT 7241: orr x13, x12, x9, lsl #PAGE_SHIFT 725 726 /* Store the entry */ 727 str x13, [x6, x11, lsl #3] 728 729 sub x10, x10, #1 730 add x11, x11, #1 731 add x9, x9, #1 732 cbnz x10, 1b 733 734 ret 735LEND(link_l0_pagetable) 736 737/* 738 * Builds an L1 -> L2 table descriptor 739 * 740 * x6 = L1 table 741 * x8 = Virtual Address 742 * x9 = L2 PA (trashed) 743 * x11, x12 and x13 are trashed 744 */ 745LENTRY(link_l1_pagetable) 746 /* 747 * Link an L1 -> L2 table entry. 748 */ 749 /* Find the table index */ 750 lsr x11, x8, #L1_SHIFT 751 and x11, x11, #Ln_ADDR_MASK 752 753 /* Build the L1 block entry */ 754 mov x12, #L1_TABLE 755 756 /* Only use the output address bits */ 757 lsr x9, x9, #PAGE_SHIFT 758 orr x13, x12, x9, lsl #PAGE_SHIFT 759 760 /* Store the entry */ 761 str x13, [x6, x11, lsl #3] 762 763 ret 764LEND(link_l1_pagetable) 765 766/* 767 * Builds count 2 MiB page table entry 768 * x6 = L2 table 769 * x7 = Block attributes 770 * x8 = VA start 771 * x9 = PA start (trashed) 772 * x10 = Entry count (trashed) 773 * x11, x12 and x13 are trashed 774 */ 775LENTRY(build_l2_block_pagetable) 776 /* 777 * Build the L2 table entry. 778 */ 779 /* Find the table index */ 780 lsr x11, x8, #L2_SHIFT 781 and x11, x11, #Ln_ADDR_MASK 782 783 /* Build the L2 block entry */ 784 orr x12, x7, #L2_BLOCK 785 orr x12, x12, #(ATTR_AF) 786 orr x12, x12, #(ATTR_S1_UXN) 787#ifdef __ARM_FEATURE_BTI_DEFAULT 788 orr x12, x12, #(ATTR_S1_GP) 789#endif 790 /* Set the shareability attribute */ 791 orr x12, x12, x22 792 793 /* Only use the output address bits */ 794 lsr x9, x9, #L2_SHIFT 795 796 /* Set the physical address for this virtual address */ 7971: orr x13, x12, x9, lsl #L2_SHIFT 798 799 /* Store the entry */ 800 str x13, [x6, x11, lsl #3] 801 802 sub x10, x10, #1 803 add x11, x11, #1 804 add x9, x9, #1 805 cbnz x10, 1b 806 807 ret 808LEND(build_l2_block_pagetable) 809 810#if PAGE_SIZE != PAGE_SIZE_4K 811/* 812 * Builds an L2 -> L3 table descriptor 813 * 814 * x6 = L2 table 815 * x8 = Virtual Address 816 * x9 = L3 PA (trashed) 817 * x11, x12 and x13 are trashed 818 */ 819LENTRY(link_l2_pagetable) 820 /* 821 * Link an L2 -> L3 table entry. 822 */ 823 /* Find the table index */ 824 lsr x11, x8, #L2_SHIFT 825 and x11, x11, #Ln_ADDR_MASK 826 827 /* Build the L1 block entry */ 828 mov x12, #L2_TABLE 829 830 /* Only use the output address bits */ 831 lsr x9, x9, #PAGE_SHIFT 832 orr x13, x12, x9, lsl #PAGE_SHIFT 833 834 /* Store the entry */ 835 str x13, [x6, x11, lsl #3] 836 837 ret 838LEND(link_l2_pagetable) 839 840/* 841 * Builds count level 3 page table entries. Uses ATTR_CONTIGUOUS to create 842 * large page (L3C) mappings when the current VA and remaining count allow 843 * it. 844 * x6 = L3 table 845 * x7 = Block attributes 846 * x8 = VA start 847 * x9 = PA start (trashed) 848 * x10 = Entry count (trashed) 849 * x11, x12 and x13 are trashed 850 * 851 * VA start (x8) modulo L3C_SIZE must equal PA start (x9) modulo L3C_SIZE. 852 */ 853LENTRY(build_l3_page_pagetable) 854 /* 855 * Build the L3 table entry. 856 */ 857 /* Find the table index */ 858 lsr x11, x8, #L3_SHIFT 859 and x11, x11, #Ln_ADDR_MASK 860 861 /* Build the L3 page entry */ 862 orr x12, x7, #L3_PAGE 863 orr x12, x12, #(ATTR_AF) 864 orr x12, x12, #(ATTR_S1_UXN) 865#ifdef __ARM_FEATURE_BTI_DEFAULT 866 orr x12, x12, #(ATTR_S1_GP) 867#endif 868 /* Set the shareability attribute */ 869 orr x12, x12, x22 870 871 /* Only use the output address bits */ 872 lsr x9, x9, #L3_SHIFT 873 874 /* Check if an ATTR_CONTIGUOUS mapping is possible */ 8751: tst x11, #(L3C_ENTRIES - 1) 876 b.ne 2f 877 cmp x10, #L3C_ENTRIES 878 b.lo 3f 879 orr x12, x12, #(ATTR_CONTIGUOUS) 880 b 2f 8813: and x12, x12, #(~ATTR_CONTIGUOUS) 882 883 /* Set the physical address for this virtual address */ 8842: orr x13, x12, x9, lsl #L3_SHIFT 885 886 /* Store the entry */ 887 str x13, [x6, x11, lsl #3] 888 889 sub x10, x10, #1 890 add x11, x11, #1 891 add x9, x9, #1 892 cbnz x10, 1b 893 894 ret 895LEND(build_l3_page_pagetable) 896#endif 897 898LENTRY(start_mmu) 899 dsb sy 900 901 /* Load the exception vectors */ 902 ldr x2, =exception_vectors 903 msr vbar_el1, x2 904 905 /* Load ttbr0 and ttbr1 */ 906 msr ttbr0_el1, x27 907 msr ttbr1_el1, x24 908 isb 909 910 /* Clear the Monitor Debug System control register */ 911 msr mdscr_el1, xzr 912 913 /* Invalidate the TLB */ 914 tlbi vmalle1is 915 dsb ish 916 isb 917 918 ldr x2, mair 919 msr mair_el1, x2 920 921 /* 922 * Setup TCR according to the PARange and ASIDBits fields 923 * from ID_AA64MMFR0_EL1 and the HAFDBS field from the 924 * ID_AA64MMFR1_EL1. More precisely, set TCR_EL1.AS 925 * to 1 only if the ASIDBits field equals 0b0010. 926 */ 927 ldr x2, tcr 928 929 /* If x22 contains a non-zero value then LPA2 is not implemented */ 930 cbnz x22, .Lno_lpa2 931 ldr x3, =(TCR_DS) 932 orr x2, x2, x3 933.Lno_lpa2: 934 935 mrs x3, id_aa64mmfr0_el1 936 937 /* Copy the bottom 3 bits from id_aa64mmfr0_el1 into TCR.IPS */ 938 bfi x2, x3, #(TCR_IPS_SHIFT), #(TCR_IPS_WIDTH) 939 and x3, x3, #(ID_AA64MMFR0_ASIDBits_MASK) 940 941 /* Check if the HW supports 16 bit ASIDS */ 942 cmp x3, #(ID_AA64MMFR0_ASIDBits_16) 943 /* If so x3 == 1, else x3 == 0 */ 944 cset x3, eq 945 /* Set TCR.AS with x3 */ 946 bfi x2, x3, #(TCR_ASID_SHIFT), #(TCR_ASID_WIDTH) 947 948 /* 949 * Check if the HW supports access flag updates, and set 950 * TCR_EL1.HA accordingly. The TCR_EL1.HD flag to enable 951 * HW management of dirty state is set in C code as it may 952 * need to be disabled because of CPU errata. 953 */ 954 CHECK_CPU_FEAT(x3, ID_AA64MMFR1, HAFDBS, 1f) 955 orr x2, x2, #(TCR_HA) 9561: 957 958 msr tcr_el1, x2 959 960 /* 961 * Setup SCTLR. 962 */ 963 ldr x2, sctlr_set 964 ldr x3, sctlr_clear 965 mrs x1, sctlr_el1 966 bic x1, x1, x3 /* Clear the required bits */ 967 orr x1, x1, x2 /* Set the required bits */ 968 msr sctlr_el1, x1 969 isb 970 971 ret 972 973 .align 3 974mair: 975 .quad MAIR_ATTR(MAIR_DEVICE_nGnRnE, VM_MEMATTR_DEVICE_nGnRnE) | \ 976 MAIR_ATTR(MAIR_NORMAL_NC, VM_MEMATTR_UNCACHEABLE) | \ 977 MAIR_ATTR(MAIR_NORMAL_WB, VM_MEMATTR_WRITE_BACK) | \ 978 MAIR_ATTR(MAIR_NORMAL_WT, VM_MEMATTR_WRITE_THROUGH) | \ 979 MAIR_ATTR(MAIR_DEVICE_nGnRE, VM_MEMATTR_DEVICE_nGnRE) 980tcr: 981#if PAGE_SIZE == PAGE_SIZE_4K 982#define TCR_TG (TCR_TG1_4K | TCR_TG0_4K) 983#elif PAGE_SIZE == PAGE_SIZE_16K 984#define TCR_TG (TCR_TG1_16K | TCR_TG0_16K) 985#else 986#error Unsupported page size 987#endif 988 989 .quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_TG | \ 990 TCR_SH1_IS | TCR_ORGN1_WBWA | TCR_IRGN1_WBWA | \ 991 TCR_SH0_IS | TCR_ORGN0_WBWA | TCR_IRGN0_WBWA) 992sctlr_set: 993 /* Bits to set */ 994 .quad (SCTLR_LSMAOE | SCTLR_nTLSMD | SCTLR_UCI | SCTLR_SPAN | \ 995 SCTLR_nTWE | SCTLR_nTWI | SCTLR_UCT | SCTLR_DZE | \ 996 SCTLR_I | SCTLR_SED | SCTLR_SA0 | SCTLR_SA | SCTLR_C | \ 997 SCTLR_M | SCTLR_CP15BEN | SCTLR_BT1 | SCTLR_BT0) 998sctlr_clear: 999 /* Bits to clear */ 1000 .quad (SCTLR_EE | SCTLR_E0E | SCTLR_IESB | SCTLR_WXN | SCTLR_UMA | \ 1001 SCTLR_ITD | SCTLR_A) 1002LEND(start_mmu) 1003 1004ENTRY(abort) 1005 b abort 1006END(abort) 1007 1008.bss 1009 .align PAGE_SHIFT 1010initstack: 1011 .space BOOT_STACK_SIZE 1012initstack_end: 1013 1014 .section .init_pagetable, "aw", %nobits 1015 .align PAGE_SHIFT 1016 /* 1017 * 6 initial tables (in the following order): 1018 * L2 for kernel (High addresses) 1019 * L1 for kernel 1020 * L0 for kernel 1021 * L1 bootstrap for user (Low addresses) 1022 * L0 bootstrap for user 1023 * L0 for user 1024 */ 1025 .globl pagetable_l0_ttbr1 1026pagetable: 1027#if PAGE_SIZE != PAGE_SIZE_4K 1028 .space (PAGE_SIZE * L3_PAGE_COUNT) 1029pagetable_l2_ttbr1: 1030#endif 1031 .space PAGE_SIZE 1032pagetable_l1_ttbr1: 1033 .space PAGE_SIZE 1034pagetable_l0_ttbr1: 1035 .space PAGE_SIZE 1036pagetable_l2_ttbr0_bootstrap: 1037 .space PAGE_SIZE 1038pagetable_l1_ttbr0_bootstrap: 1039 .space PAGE_SIZE 1040pagetable_l0_ttbr0_bootstrap: 1041 .space PAGE_SIZE 1042pagetable_l0_ttbr0: 1043 .space PAGE_SIZE 1044pagetable_end: 1045 1046el2_pagetable: 1047 .space PAGE_SIZE 1048 1049 .section .rodata, "a", %progbits 1050 .globl aarch32_sigcode 1051 .align 2 1052aarch32_sigcode: 1053 .word 0xe1a0000d // mov r0, sp 1054 .word 0xe2800040 // add r0, r0, #SIGF_UC 1055 .word 0xe59f700c // ldr r7, [pc, #12] 1056 .word 0xef000000 // swi #0 1057 .word 0xe59f7008 // ldr r7, [pc, #8] 1058 .word 0xef000000 // swi #0 1059 .word 0xeafffffa // b . - 16 1060 .word SYS_sigreturn 1061 .word SYS_exit 1062 .align 3 1063 .size aarch32_sigcode, . - aarch32_sigcode 1064aarch32_esigcode: 1065 .data 1066 .global sz_aarch32_sigcode 1067sz_aarch32_sigcode: 1068 .quad aarch32_esigcode - aarch32_sigcode 1069 1070GNU_PROPERTY_AARCH64_FEATURE_1_NOTE(GNU_PROPERTY_AARCH64_FEATURE_1_VAL) 1071