1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved. 23 */ 24 25 #ifndef _SYS_NXGE_NXGE_N2_ESR_HW_H 26 #define _SYS_NXGE_NXGE_N2_ESR_HW_H 27 28 #ifdef __cplusplus 29 extern "C" { 30 #endif 31 32 #define ESR_N2_DEV_ADDR 0x1E 33 #define ESR_N2_BASE 0x8000 34 35 /* 36 * Definitions for TI WIZ6C2xxN2x0 Macro Family. 37 */ 38 39 /* Register Blocks base address */ 40 41 #define ESR_N2_PLL_REG_OFFSET 0 42 #define ESR_N2_TEST_REG_OFFSET 0x004 43 #define ESR_N2_TX_REG_OFFSET 0x100 44 #define ESR_N2_TX_0_REG_OFFSET 0x100 45 #define ESR_N2_TX_1_REG_OFFSET 0x104 46 #define ESR_N2_TX_2_REG_OFFSET 0x108 47 #define ESR_N2_TX_3_REG_OFFSET 0x10c 48 #define ESR_N2_TX_4_REG_OFFSET 0x110 49 #define ESR_N2_TX_5_REG_OFFSET 0x114 50 #define ESR_N2_TX_6_REG_OFFSET 0x118 51 #define ESR_N2_TX_7_REG_OFFSET 0x11c 52 #define ESR_N2_RX_REG_OFFSET 0x120 53 #define ESR_N2_RX_0_REG_OFFSET 0x120 54 #define ESR_N2_RX_1_REG_OFFSET 0x124 55 #define ESR_N2_RX_2_REG_OFFSET 0x128 56 #define ESR_N2_RX_3_REG_OFFSET 0x12c 57 #define ESR_N2_RX_4_REG_OFFSET 0x130 58 #define ESR_N2_RX_5_REG_OFFSET 0x134 59 #define ESR_N2_RX_6_REG_OFFSET 0x138 60 #define ESR_N2_RX_7_REG_OFFSET 0x13c 61 #define ESR_N2_P1_REG_OFFSET 0x400 62 63 /* Register address */ 64 65 #define ESR_N2_PLL_CFG_REG ESR_N2_BASE + ESR_N2_PLL_REG_OFFSET 66 #define ESR_N2_PLL_CFG_L_REG ESR_N2_BASE + ESR_N2_PLL_REG_OFFSET 67 #define ESR_N2_PLL_CFG_H_REG ESR_N2_BASE + ESR_N2_PLL_REG_OFFSET + 1 68 #define ESR_N2_PLL_STS_REG ESR_N2_BASE + ESR_N2_PLL_REG_OFFSET + 2 69 #define ESR_N2_PLL_STS_L_REG ESR_N2_BASE + ESR_N2_PLL_REG_OFFSET + 2 70 #define ESR_N2_PLL_STS_H_REG ESR_N2_BASE + ESR_N2_PLL_REG_OFFSET + 3 71 #define ESR_N2_TEST_CFG_REG ESR_N2_BASE + ESR_N2_TEST_REG_OFFSET 72 #define ESR_N2_TEST_CFG_L_REG ESR_N2_BASE + ESR_N2_TEST_REG_OFFSET 73 #define ESR_N2_TEST_CFG_H_REG ESR_N2_BASE + ESR_N2_TEST_REG_OFFSET + 1 74 75 #define ESR_N2_TX_CFG_REG_ADDR(chan) (ESR_N2_BASE + ESR_N2_TX_REG_OFFSET +\ 76 (chan * 4)) 77 #define ESR_N2_TX_CFG_L_REG_ADDR(chan) (ESR_N2_BASE + ESR_N2_TX_REG_OFFSET +\ 78 (chan * 4)) 79 #define ESR_N2_TX_CFG_H_REG_ADDR(chan) (ESR_N2_BASE + ESR_N2_TX_REG_OFFSET +\ 80 (chan * 4) + 1) 81 #define ESR_N2_TX_STS_REG_ADDR(chan) (ESR_N2_BASE + ESR_N2_TX_REG_OFFSET +\ 82 (chan * 4) + 2) 83 #define ESR_N2_TX_STS_L_REG_ADDR(chan) (ESR_N2_BASE + ESR_N2_TX_REG_OFFSET +\ 84 (chan * 4) + 2) 85 #define ESR_N2_TX_STS_H_REG_ADDR(chan) (ESR_N2_BASE + ESR_N2_TX_REG_OFFSET +\ 86 (chan * 4) + 3) 87 #define ESR_N2_RX_CFG_REG_ADDR(chan) (ESR_N2_BASE + ESR_N2_RX_REG_OFFSET +\ 88 (chan * 4)) 89 #define ESR_N2_RX_CFG_L_REG_ADDR(chan) (ESR_N2_BASE + ESR_N2_RX_REG_OFFSET +\ 90 (chan * 4)) 91 #define ESR_N2_RX_CFG_H_REG_ADDR(chan) (ESR_N2_BASE + ESR_N2_RX_REG_OFFSET +\ 92 (chan * 4) + 1) 93 #define ESR_N2_RX_STS_REG_ADDR(chan) (ESR_N2_BASE + ESR_N2_RX_REG_OFFSET +\ 94 (chan * 4) + 2) 95 #define ESR_N2_RX_STS_L_REG_ADDR(chan) (ESR_N2_BASE + ESR_N2_RX_REG_OFFSET +\ 96 (chan * 4) + 2) 97 #define ESR_N2_RX_STS_H_REG_ADDR(chan) (ESR_N2_BASE + ESR_N2_RX_REG_OFFSET +\ 98 (chan * 4) + 3) 99 100 /* PLL Configuration Low 16-bit word */ 101 typedef union _esr_ti_cfgpll_l { 102 uint16_t value; 103 104 struct { 105 #if defined(_BIT_FIELDS_HTOL) 106 uint16_t res2 : 6; 107 uint16_t lb : 2; 108 uint16_t res1 : 3; 109 uint16_t mpy : 4; 110 uint16_t enpll : 1; 111 #elif defined(_BIT_FIELDS_LTOH) 112 uint16_t enpll : 1; 113 uint16_t mpy : 4; 114 uint16_t res1 : 3; 115 uint16_t lb : 2; 116 uint16_t res2 : 6; 117 #endif 118 } bits; 119 } esr_ti_cfgpll_l_t; 120 121 /* PLL Configurations */ 122 #define CFGPLL_LB_FREQ_DEP_BANDWIDTH 0 123 #define CFGPLL_LB_LOW_BANDWIDTH 0x2 124 #define CFGPLL_LB_HIGH_BANDWIDTH 0x3 125 #define CFGPLL_MPY_4X 0 126 #define CFGPLL_MPY_5X 0x1 127 #define CFGPLL_MPY_6X 0x2 128 #define CFGPLL_MPY_8X 0x4 129 #define CFGPLL_MPY_10X 0x5 130 #define CFGPLL_MPY_12X 0x6 131 #define CFGPLL_MPY_12P5X 0x7 132 133 /* Rx Configuration Low 16-bit word */ 134 135 typedef union _esr_ti_cfgrx_l { 136 uint16_t value; 137 138 struct { 139 #if defined(_BIT_FIELDS_HTOL) 140 uint16_t los : 2; 141 uint16_t align : 2; 142 uint16_t res : 1; 143 uint16_t term : 3; 144 uint16_t invpair : 1; 145 uint16_t rate : 2; 146 uint16_t buswidth : 3; 147 uint16_t entest : 1; 148 uint16_t enrx : 1; 149 #elif defined(_BIT_FIELDS_LTOH) 150 uint16_t enrx : 1; 151 uint16_t entest : 1; 152 uint16_t buswidth : 3; 153 uint16_t rate : 2; 154 uint16_t invpair : 1; 155 uint16_t term : 3; 156 uint16_t res : 1; 157 uint16_t align : 2; 158 uint16_t los : 2; 159 #endif 160 } bits; 161 } esr_ti_cfgrx_l_t; 162 163 /* Rx Configuration High 16-bit word */ 164 165 typedef union _esr_ti_cfgrx_h { 166 uint16_t value; 167 168 struct { 169 #if defined(_BIT_FIELDS_HTOL) 170 uint16_t res2 : 6; 171 uint16_t bsinrxn : 1; 172 uint16_t bsinrxp : 1; 173 uint16_t res1 : 1; 174 uint16_t eq : 4; 175 uint16_t cdr : 3; 176 #elif defined(_BIT_FIELDS_LTOH) 177 uint16_t cdr : 3; 178 uint16_t eq : 4; 179 uint16_t res1 : 1; 180 uint16_t bsinrxp : 1; 181 uint16_t bsinrxn : 1; 182 uint16_t res2 : 6; 183 #endif 184 } bits; 185 } esr_ti_cfgrx_h_t; 186 187 /* Receive Configurations */ 188 #define CFGRX_BUSWIDTH_10BIT 0 189 #define CFGRX_BUSWIDTH_8BIT 1 190 #define CFGRX_RATE_FULL 0 191 #define CFGRX_RATE_HALF 1 192 #define CFGRX_RATE_QUAD 2 193 #define CFGRX_TERM_VDDT 0 194 #define CFGRX_TERM_0P8VDDT 1 195 #define CFGRX_TERM_FLOAT 3 196 #define CFGRX_ALIGN_DIS 0 197 #define CFGRX_ALIGN_EN 1 198 #define CFGRX_ALIGN_JOG 2 199 #define CFGRX_LOS_DIS 0 200 #define CFGRX_LOS_HITHRES 1 201 #define CFGRX_LOS_LOTHRES 2 202 #define CFGRX_CDR_1ST_ORDER 0 203 #define CFGRX_CDR_2ND_ORDER_HP 1 204 #define CFGRX_CDR_2ND_ORDER_MP 2 205 #define CFGRX_CDR_2ND_ORDER_LP 3 206 #define CFGRX_CDR_1ST_ORDER_FAST_LOCK 4 207 #define CFGRX_CDR_2ND_ORDER_HP_FAST_LOCK 5 208 #define CFGRX_CDR_2ND_ORDER_MP_FAST_LOCK 6 209 #define CFGRX_CDR_2ND_ORDER_LP_FAST_LOCK 7 210 #define CFGRX_EQ_MAX_LF 0 211 #define CFGRX_EQ_ADAPTIVE_LP_ADAPTIVE_ZF 0x1 212 #define CFGRX_EQ_ADAPTIVE_LF_1084MHZ_ZF 0x8 213 #define CFGRX_EQ_ADAPTIVE_LF_805MHZ_ZF 0x9 214 #define CFGRX_EQ_ADAPTIVE_LP_573MHZ_ZF 0xA 215 #define CFGRX_EQ_ADAPTIVE_LP_402MHZ_ZF 0xB 216 #define CFGRX_EQ_ADAPTIVE_LP_304MHZ_ZF 0xC 217 #define CFGRX_EQ_ADAPTIVE_LP_216MHZ_ZF 0xD 218 #define CFGRX_EQ_ADAPTIVE_LP_156MHZ_ZF 0xE 219 #define CFGRX_EQ_ADAPTIVE_LP_135HZ_ZF 0xF 220 221 /* Rx Status Low 16-bit word */ 222 223 typedef union _esr_ti_stsrx_l { 224 uint16_t value; 225 226 struct { 227 #if defined(_BIT_FIELDS_HTOL) 228 uint16_t res : 10; 229 uint16_t bsrxn : 1; 230 uint16_t bsrxp : 1; 231 uint16_t losdtct : 1; 232 uint16_t oddcg : 1; 233 uint16_t sync : 1; 234 uint16_t testfail : 1; 235 #elif defined(_BIT_FIELDS_LTOH) 236 uint16_t testfail : 1; 237 uint16_t sync : 1; 238 uint16_t oddcg : 1; 239 uint16_t losdtct : 1; 240 uint16_t bsrxp : 1; 241 uint16_t bsrxn : 1; 242 uint16_t res : 10; 243 #endif 244 } bits; 245 } esr_ti_stsrx_l_t; 246 247 /* Tx Configuration Low 16-bit word */ 248 249 typedef union _esr_ti_cfgtx_l { 250 uint16_t value; 251 252 struct { 253 #if defined(_BIT_FIELDS_HTOL) 254 uint16_t de : 4; 255 uint16_t swing : 3; 256 uint16_t cm : 1; 257 uint16_t invpair : 1; 258 uint16_t rate : 2; 259 uint16_t buswwidth : 3; 260 uint16_t entest : 1; 261 uint16_t entx : 1; 262 #elif defined(_BIT_FIELDS_LTOH) 263 uint16_t entx : 1; 264 uint16_t entest : 1; 265 uint16_t buswwidth : 3; 266 uint16_t rate : 2; 267 uint16_t invpair : 1; 268 uint16_t cm : 1; 269 uint16_t swing : 3; 270 uint16_t de : 4; 271 #endif 272 } bits; 273 } esr_ti_cfgtx_l_t; 274 275 /* Tx Configuration High 16-bit word */ 276 277 typedef union _esr_ti_cfgtx_h { 278 uint16_t value; 279 280 struct { 281 #if defined(_BIT_FIELDS_HTOL) 282 uint16_t res : 14; 283 uint16_t bstx : 1; 284 uint16_t enftp : 1; 285 #elif defined(_BIT_FIELDS_LTOH) 286 uint16_t enftp : 1; 287 uint16_t bstx : 1; 288 uint16_t res : 14; 289 #endif 290 } bits; 291 } esr_ti_cfgtx_h_t; 292 293 /* Transmit Configurations */ 294 #define CFGTX_BUSWIDTH_10BIT 0 295 #define CFGTX_BUSWIDTH_8BIT 1 296 #define CFGTX_RATE_FULL 0 297 #define CFGTX_RATE_HALF 1 298 #define CFGTX_RATE_QUAD 2 299 #define CFGTX_SWING_125MV 0 300 #define CFGTX_SWING_250MV 1 301 #define CFGTX_SWING_500MV 2 302 #define CFGTX_SWING_625MV 3 303 #define CFGTX_SWING_750MV 4 304 #define CFGTX_SWING_1000MV 5 305 #define CFGTX_SWING_1250MV 6 306 #define CFGTX_SWING_1375MV 7 307 #define CFGTX_DE_0 0 308 #define CFGTX_DE_4P76 1 309 #define CFGTX_DE_9P52 2 310 #define CFGTX_DE_14P28 3 311 #define CFGTX_DE_19P04 4 312 #define CFGTX_DE_23P8 5 313 #define CFGTX_DE_28P56 6 314 #define CFGTX_DE_33P32 7 315 316 /* Test Configuration */ 317 318 typedef union _esr_ti_testcfg { 319 uint16_t value; 320 321 struct { 322 #if defined(_BIT_FIELDS_HTOL) 323 uint16_t res1 : 1; 324 uint16_t invpat : 1; 325 uint16_t rate : 2; 326 uint16_t res : 1; 327 uint16_t enbspls : 1; 328 uint16_t enbsrx : 1; 329 uint16_t enbstx : 1; 330 uint16_t loopback : 2; 331 uint16_t clkbyp : 2; 332 uint16_t enrxpatt : 1; 333 uint16_t entxpatt : 1; 334 uint16_t testpatt : 2; 335 #elif defined(_BIT_FIELDS_LTOH) 336 uint16_t testpatt : 2; 337 uint16_t entxpatt : 1; 338 uint16_t enrxpatt : 1; 339 uint16_t clkbyp : 2; 340 uint16_t loopback : 2; 341 uint16_t enbstx : 1; 342 uint16_t enbsrx : 1; 343 uint16_t enbspls : 1; 344 uint16_t res : 1; 345 uint16_t rate : 2; 346 uint16_t invpat : 1; 347 uint16_t res1 : 1; 348 #endif 349 } bits; 350 } esr_ti_testcfg_t; 351 352 #define TESTCFG_PAD_LOOPBACK 0x1 353 #define TESTCFG_INNER_CML_DIS_LOOPBACK 0x2 354 #define TESTCFG_INNER_CML_EN_LOOOPBACK 0x3 355 356 /* 357 * Definitions for TI WIZ7c2xxn5x1 Macro Family (KT/NIU). 358 */ 359 360 /* PLL_CFG: PLL Configuration Low 16-bit word */ 361 typedef union _k_esr_ti_cfgpll_l { 362 uint16_t value; 363 364 struct { 365 #if defined(_BIT_FIELDS_HTOL) 366 uint16_t res2 : 1; 367 uint16_t clkbyp : 2; 368 uint16_t lb : 2; 369 uint16_t res1 : 1; 370 uint16_t vrange : 1; 371 uint16_t divclken : 1; 372 uint16_t mpy : 7; 373 uint16_t enpll : 1; 374 #elif defined(_BIT_FIELDS_LTOH) 375 uint16_t enpll : 1; 376 uint16_t mpy : 7; 377 uint16_t divclken : 1; 378 uint16_t vrange : 1; 379 uint16_t res1 : 1; 380 uint16_t lb : 2; 381 uint16_t clkbyp : 2; 382 uint16_t res2 : 1; 383 #endif 384 } bits; 385 } k_esr_ti_cfgpll_l_t; 386 387 /* PLL Configurations */ 388 #define K_CFGPLL_ENABLE_PLL 1 389 #define K_CFGPLL_MPY_4X 0x10 390 #define K_CFGPLL_MPY_5X 0x14 391 #define K_CFGPLL_MPY_6X 0x18 392 #define K_CFGPLL_MPY_8X 0x20 393 #define K_CFGPLL_MPY_8P25X 0x21 394 #define K_CFGPLL_MPY_10X 0x28 395 #define K_CFGPLL_MPY_12X 0x30 396 #define K_CFGPLL_MPY_12P5X 0x32 397 #define K_CFGPLL_MPY_15X 0x3c 398 #define K_CFGPLL_MPY_16X 0x40 399 #define K_CFGPLL_MPY_16P5X 0x42 400 #define K_CFGPLL_MPY_20X 0x50 401 #define K_CFGPLL_MPY_22X 0x58 402 #define K_CFGPLL_MPY_25X 0x64 403 #define K_CFGPLL_ENABLE_DIVCLKEN 0x100 404 405 /* PLL_STS */ 406 typedef union _k_esr_ti_pll_sts { 407 uint16_t value; 408 409 struct { 410 #if defined(_BIT_FIELDS_HTOL) 411 uint16_t res2 : 12; 412 uint16_t res1 : 2; 413 uint16_t divclk : 1; 414 uint16_t lock : 1; 415 #elif defined(_BIT_FIELDS_LTOH) 416 uint16_t lock : 1; 417 uint16_t divclk : 1; 418 uint16_t res1 : 2; 419 uint16_t res2 : 12; 420 #endif 421 } bits; 422 } k_esr_ti_pll_sts_t; 423 424 /* TEST_CFT */ 425 typedef union _kt_esr_ti_testcfg { 426 uint16_t value; 427 428 struct { 429 #if defined(_BIT_FIELDS_HTOL) 430 uint16_t res : 7; 431 uint16_t testpatt2 : 3; 432 uint16_t testpatt1 : 3; 433 uint16_t enbspt : 1; 434 uint16_t enbsrx : 1; 435 uint16_t enbstx : 1; 436 #elif defined(_BIT_FIELDS_LTOH) 437 uint16_t enbstx : 1; 438 uint16_t enbsrx : 1; 439 uint16_t enbspt : 1; 440 uint16_t testpatt1 : 3; 441 uint16_t testpatt2 : 3; 442 uint16_t res : 7; 443 #endif 444 } bits; 445 } k_esr_ti_testcfg_t; 446 447 #define K_TESTCFG_ENBSTX 0x1 448 #define K_TESTCFG_ENBSRX 0x2 449 #define K_TESTCFG_ENBSPT 0x4 450 451 /* TX_CFG: Tx Configuration Low 16-bit word */ 452 453 typedef union _k_esr_ti_cfgtx_l { 454 uint16_t value; 455 456 struct { 457 #if defined(_BIT_FIELDS_HTOL) 458 uint16_t de : 3; 459 uint16_t swing : 4; 460 uint16_t cm : 1; 461 uint16_t invpair : 1; 462 uint16_t rate : 2; 463 uint16_t buswwidth : 4; 464 uint16_t entx : 1; 465 #elif defined(_BIT_FIELDS_LTOH) 466 uint16_t entx : 1; 467 uint16_t buswwidth : 4; 468 uint16_t rate : 2; 469 uint16_t invpair : 1; 470 uint16_t cm : 1; 471 uint16_t swing : 4; 472 uint16_t de : 3; 473 #endif 474 } bits; 475 } k_esr_ti_cfgtx_l_t; 476 477 /* Tx Configuration High 16-bit word */ 478 479 typedef union _k_esr_ti_cfgtx_h { 480 uint16_t value; 481 482 struct { 483 #if defined(_BIT_FIELDS_HTOL) 484 uint16_t res3 : 1; 485 uint16_t bstx : 1; 486 uint16_t res2 : 1; 487 uint16_t loopback : 2; 488 uint16_t rdtct : 2; 489 uint16_t enidl : 1; 490 uint16_t rsync : 1; 491 uint16_t msync : 1; 492 uint16_t res1 : 4; 493 uint16_t de : 2; 494 #elif defined(_BIT_FIELDS_LTOH) 495 uint16_t de : 2; 496 uint16_t res1 : 4; 497 uint16_t msync : 1; 498 uint16_t rsync : 1; 499 uint16_t enidl : 1; 500 uint16_t rdtct : 2; 501 uint16_t loopback : 2; 502 uint16_t res2 : 1; 503 uint16_t bstx : 1; 504 uint16_t res3 : 1; 505 #endif 506 } bits; 507 } k_esr_ti_cfgtx_h_t; 508 509 /* Transmit Configurations (TBD) */ 510 #define K_CFGTX_ENABLE_TX 0x1 511 #define K_CFGTX_ENABLE_MSYNC 0x1 512 513 #define K_CFGTX_BUSWIDTH_10BIT 0 514 #define K_CFGTX_BUSWIDTH_8BIT 1 515 #define K_CFGTX_RATE_FULL 0 516 #define K_CFGTX_RATE_HALF 0x1 517 #define K_CFGTX_RATE_QUAD 2 518 #define K_CFGTX_SWING_125MV 0 519 #define K_CFGTX_SWING_250MV 1 520 #define K_CFGTX_SWING_500MV 2 521 #define K_CFGTX_SWING_625MV 3 522 #define K_CFGTX_SWING_750MV 4 523 #define K_CFGTX_SWING_1000MV 5 524 #define K_CFGTX_SWING_1250MV 6 525 #define K_CFGTX_SWING_1375MV 7 526 #define K_CFGTX_SWING_2000MV 0xf 527 #define K_CFGTX_DE_0 0 528 #define K_CFGTX_DE_4P76 1 529 #define K_CFGTX_DE_9P52 2 530 #define K_CFGTX_DE_14P28 3 531 #define K_CFGTX_DE_19P04 4 532 #define K_CFGTX_DE_23P8 5 533 #define K_CFGTX_DE_28P56 6 534 #define K_CFGTX_DE_33P32 7 535 #define K_CFGTX_DIS_LOOPBACK 0x0 536 #define K_CFGTX_BUMP_PAD_LOOPBACK 0x1 537 #define K_CFGTX_INNER_CML_DIS_LOOPBACK 0x2 538 #define K_CFGTX_INNER_CML_ENA_LOOPBACK 0x3 539 540 /* TX_STS */ 541 typedef union _k_esr_ti_tx_sts { 542 uint16_t value; 543 544 struct { 545 #if defined(_BIT_FIELDS_HTOL) 546 uint16_t res1 : 14; 547 uint16_t rdtctip : 1; 548 uint16_t testfail : 1; 549 #elif defined(_BIT_FIELDS_LTOH) 550 uint16_t testfail : 1; 551 uint16_t rdtctip : 1; 552 uint16_t res1 : 14; 553 #endif 554 } bits; 555 } k_esr_ti_tx_sts_t; 556 557 /* Rx Configuration Low 16-bit word */ 558 559 typedef union _k_esr_ti_cfgrx_l { 560 uint16_t value; 561 562 struct { 563 #if defined(_BIT_FIELDS_HTOL) 564 uint16_t los : 3; 565 uint16_t align : 2; 566 uint16_t term : 3; 567 uint16_t invpair : 1; 568 uint16_t rate : 2; 569 uint16_t buswidth : 4; 570 uint16_t enrx : 1; 571 #elif defined(_BIT_FIELDS_LTOH) 572 uint16_t enrx : 1; 573 uint16_t buswidth : 4; 574 uint16_t rate : 2; 575 uint16_t invpair : 1; 576 uint16_t term : 3; 577 uint16_t align : 2; 578 uint16_t los : 3; 579 #endif 580 } bits; 581 } k_esr_ti_cfgrx_l_t; 582 583 /* Rx Configuration High 16-bit word */ 584 585 typedef union _k_esr_ti_cfgrx_h { 586 uint16_t value; 587 588 struct { 589 #if defined(_BIT_FIELDS_HTOL) 590 uint16_t res2 : 1; 591 uint16_t bsinrxn : 1; 592 uint16_t bsinrxp : 1; 593 uint16_t loopback : 2; 594 uint16_t res1 : 3; 595 uint16_t enoc : 1; 596 uint16_t eq : 4; 597 uint16_t cdr : 3; 598 #elif defined(_BIT_FIELDS_LTOH) 599 uint16_t cdr : 3; 600 uint16_t eq : 4; 601 uint16_t enoc : 1; 602 uint16_t res1 : 3; 603 uint16_t loopback : 2; 604 uint16_t bsinrxp : 1; 605 uint16_t bsinrxn : 1; 606 uint16_t res2 : 1; 607 #endif 608 } bits; 609 } k_esr_ti_cfgrx_h_t; 610 611 /* Receive Configurations (TBD) */ 612 #define K_CFGRX_ENABLE_RX 0x1 613 614 #define K_CFGRX_BUSWIDTH_10BIT 0 615 #define K_CFGRX_BUSWIDTH_8BIT 1 616 #define K_CFGRX_RATE_FULL 0 617 #define K_CFGRX_RATE_HALF 1 618 #define K_CFGRX_RATE_QUAD 2 619 #define K_CFGRX_TERM_VDDT 0 620 #define K_CFGRX_TERM_0P8VDDT 1 621 #define K_CFGRX_TERM_FLOAT 3 622 #define K_CFGRX_ALIGN_DIS 0x0 623 #define K_CFGRX_ALIGN_EN 0x1 624 #define K_CFGRX_ALIGN_JOG 0x2 625 #define K_CFGRX_LOS_DIS 0x0 626 #define K_CFGRX_LOS_ENABLE 0x2 627 #define K_CFGRX_CDR_1ST_ORDER 0 628 #define K_CFGRX_CDR_2ND_ORDER_HP 1 629 #define K_CFGRX_CDR_2ND_ORDER_MP 2 630 #define K_CFGRX_CDR_2ND_ORDER_LP 3 631 #define K_CFGRX_CDR_1ST_ORDER_FAST_LOCK 4 632 #define K_CFGRX_CDR_2ND_ORDER_HP_FAST_LOCK 5 633 #define K_CFGRX_CDR_2ND_ORDER_MP_FAST_LOCK 6 634 #define K_CFGRX_CDR_2ND_ORDER_LP_FAST_LOCK 7 635 #define K_CFGRX_EQ_MAX_LF_ZF 0 636 #define K_CFGRX_EQ_ADAPTIVE 0x1 637 #define K_CFGRX_EQ_ADAPTIVE_LF_365MHZ_ZF 0x8 638 #define K_CFGRX_EQ_ADAPTIVE_LF_275MHZ_ZF 0x9 639 #define K_CFGRX_EQ_ADAPTIVE_LP_195MHZ_ZF 0xa 640 #define K_CFGRX_EQ_ADAPTIVE_LP_140MHZ_ZF 0xb 641 #define K_CFGRX_EQ_ADAPTIVE_LP_105MHZ_ZF 0xc 642 #define K_CFGRX_EQ_ADAPTIVE_LP_75MHZ_ZF 0xd 643 #define K_CFGRX_EQ_ADAPTIVE_LP_55MHZ_ZF 0xe 644 #define K_CFGRX_EQ_ADAPTIVE_LP_50HZ_ZF 0xf 645 646 /* Rx Status Low 16-bit word */ 647 648 typedef union _k_esr_ti_stsrx_l { 649 uint16_t value; 650 651 struct { 652 #if defined(_BIT_FIELDS_HTOL) 653 uint16_t res2 : 10; 654 uint16_t bsrxn : 1; 655 uint16_t bsrxp : 1; 656 uint16_t losdtct : 1; 657 uint16_t res1 : 1; 658 uint16_t sync : 1; 659 uint16_t testfail : 1; 660 #elif defined(_BIT_FIELDS_LTOH) 661 uint16_t testfail : 1; 662 uint16_t sync : 1; 663 uint16_t res1 : 1; 664 uint16_t losdtct : 1; 665 uint16_t bsrxp : 1; 666 uint16_t bsrxn : 1; 667 uint16_t res : 10; 668 #endif 669 } bits; 670 } k_esr_ti_stsrx_l_t; 671 672 #define K_TESTCFG_INNER_CML_EN_LOOOPBACK 0x3 673 674 /* 675 * struct for Serdes properties 676 */ 677 typedef struct _nxge_serdes_prop_t { 678 uint16_t tx_cfg_l; 679 uint16_t tx_cfg_h; 680 uint16_t rx_cfg_l; 681 uint16_t rx_cfg_h; 682 uint16_t pll_cfg_l; 683 uint16_t prop_set; 684 } nxge_serdes_prop_t, *p_nxge_serdes_prop_t; 685 686 /* Bit array with 1 bit for every serdes property set */ 687 #define NXGE_SRDS_TXCFGL 0x1 688 #define NXGE_SRDS_TXCFGH 0x2 689 #define NXGE_SRDS_RXCFGL 0x4 690 #define NXGE_SRDS_RXCFGH 0x8 691 #define NXGE_SRDS_PLLCFGL 0x10 692 693 #ifdef __cplusplus 694 } 695 #endif 696 697 #endif /* _SYS_NXGE_NXGE_N2_ESR_HW_H */ 698