1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2003-2008 Joseph Koshy
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/types.h>
30 #include <sys/param.h>
31 #include <sys/module.h>
32 #include <sys/pmc.h>
33 #include <sys/syscall.h>
34
35 #if defined(__amd64__) || defined(__i386__)
36 #include <machine/cpufunc.h>
37 #endif
38
39 #include <ctype.h>
40 #include <errno.h>
41 #include <err.h>
42 #include <fcntl.h>
43 #include <pmc.h>
44 #include <stdio.h>
45 #include <stdlib.h>
46 #include <string.h>
47 #include <strings.h>
48 #include <sysexits.h>
49 #include <unistd.h>
50
51 #include "libpmcinternal.h"
52
53 /* Function prototypes */
54 #if defined(__amd64__) || defined(__i386__)
55 static int k8_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
56 struct pmc_op_pmcallocate *_pmc_config);
57 static int ibs_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
58 struct pmc_op_pmcallocate *_pmc_config);
59 static int tsc_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
60 struct pmc_op_pmcallocate *_pmc_config);
61 #endif
62 #if defined(__arm__)
63 static int armv7_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
64 struct pmc_op_pmcallocate *_pmc_config);
65 #endif
66 #if defined(__aarch64__)
67 static int arm64_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
68 struct pmc_op_pmcallocate *_pmc_config);
69 static int cmn600_pmu_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
70 struct pmc_op_pmcallocate *_pmc_config);
71 static int dmc620_pmu_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
72 struct pmc_op_pmcallocate *_pmc_config);
73 #endif
74 static int soft_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
75 struct pmc_op_pmcallocate *_pmc_config);
76
77 #if defined(__powerpc__)
78 static int powerpc_allocate_pmc(enum pmc_event _pe, char* ctrspec,
79 struct pmc_op_pmcallocate *_pmc_config);
80 #endif /* __powerpc__ */
81
82 #define PMC_CALL(op, params) syscall(pmc_syscall, (op), (params))
83
84 /*
85 * Event aliases provide a way for the user to ask for generic events
86 * like "cache-misses", or "instructions-retired". These aliases are
87 * mapped to the appropriate canonical event descriptions using a
88 * lookup table.
89 */
90 struct pmc_event_alias {
91 const char *pm_alias;
92 const char *pm_spec;
93 };
94
95 static const struct pmc_event_alias *pmc_mdep_event_aliases;
96
97 /*
98 * The pmc_event_descr structure maps symbolic names known to the user
99 * to integer codes used by the PMC KLD.
100 */
101 struct pmc_event_descr {
102 const char *pm_ev_name;
103 enum pmc_event pm_ev_code;
104 };
105
106 /*
107 * The pmc_class_descr structure maps class name prefixes for
108 * event names to event tables and other PMC class data.
109 */
110 struct pmc_class_descr {
111 const char *pm_evc_name;
112 size_t pm_evc_name_size;
113 enum pmc_class pm_evc_class;
114 const struct pmc_event_descr *pm_evc_event_table;
115 size_t pm_evc_event_table_size;
116 int (*pm_evc_allocate_pmc)(enum pmc_event _pe,
117 char *_ctrspec, struct pmc_op_pmcallocate *_pa);
118 };
119
120 #define PMC_TABLE_SIZE(N) (sizeof(N)/sizeof(N[0]))
121 #define PMC_EVENT_TABLE_SIZE(N) PMC_TABLE_SIZE(N##_event_table)
122
123 #undef __PMC_EV
124 #define __PMC_EV(C,N) { #N, PMC_EV_ ## C ## _ ## N },
125
126 /*
127 * PMC_CLASSDEP_TABLE(NAME, CLASS)
128 *
129 * Define a table mapping event names and aliases to HWPMC event IDs.
130 */
131 #define PMC_CLASSDEP_TABLE(N, C) \
132 static const struct pmc_event_descr N##_event_table[] = \
133 { \
134 __PMC_EV_##C() \
135 }
136
137 PMC_CLASSDEP_TABLE(iaf, IAF);
138 PMC_CLASSDEP_TABLE(k8, K8);
139 PMC_CLASSDEP_TABLE(ibs, IBS);
140 PMC_CLASSDEP_TABLE(armv7, ARMV7);
141 PMC_CLASSDEP_TABLE(armv8, ARMV8);
142 PMC_CLASSDEP_TABLE(cmn600_pmu, CMN600_PMU);
143 PMC_CLASSDEP_TABLE(dmc620_pmu_cd2, DMC620_PMU_CD2);
144 PMC_CLASSDEP_TABLE(dmc620_pmu_c, DMC620_PMU_C);
145 PMC_CLASSDEP_TABLE(ppc7450, PPC7450);
146 PMC_CLASSDEP_TABLE(ppc970, PPC970);
147 PMC_CLASSDEP_TABLE(e500, E500);
148
149 static struct pmc_event_descr soft_event_table[PMC_EV_DYN_COUNT];
150
151 #undef __PMC_EV_ALIAS
152 #define __PMC_EV_ALIAS(N,CODE) { N, PMC_EV_##CODE },
153
154 /*
155 * TODO: Factor out the __PMC_EV_ARMV7/8 list into a single separate table
156 * rather than duplicating for each core.
157 */
158
159 static const struct pmc_event_descr cortex_a8_event_table[] =
160 {
161 __PMC_EV_ALIAS_ARMV7_CORTEX_A8()
162 __PMC_EV_ARMV7()
163 };
164
165 static const struct pmc_event_descr cortex_a9_event_table[] =
166 {
167 __PMC_EV_ALIAS_ARMV7_CORTEX_A9()
168 __PMC_EV_ARMV7()
169 };
170
171 static const struct pmc_event_descr cortex_a53_event_table[] =
172 {
173 __PMC_EV_ALIAS_ARMV8_CORTEX_A53()
174 __PMC_EV_ARMV8()
175 };
176
177 static const struct pmc_event_descr cortex_a57_event_table[] =
178 {
179 __PMC_EV_ALIAS_ARMV8_CORTEX_A57()
180 __PMC_EV_ARMV8()
181 };
182
183 static const struct pmc_event_descr cortex_a76_event_table[] =
184 {
185 __PMC_EV_ALIAS_ARMV8_CORTEX_A76()
186 __PMC_EV_ARMV8()
187 };
188
189 static const struct pmc_event_descr tsc_event_table[] =
190 {
191 __PMC_EV_ALIAS_TSC()
192 };
193
194 #undef PMC_CLASS_TABLE_DESC
195 #define PMC_CLASS_TABLE_DESC(NAME, CLASS, EVENTS, ALLOCATOR) \
196 static const struct pmc_class_descr NAME##_class_table_descr = \
197 { \
198 .pm_evc_name = #CLASS "-", \
199 .pm_evc_name_size = sizeof(#CLASS "-") - 1, \
200 .pm_evc_class = PMC_CLASS_##CLASS , \
201 .pm_evc_event_table = EVENTS##_event_table , \
202 .pm_evc_event_table_size = \
203 PMC_EVENT_TABLE_SIZE(EVENTS), \
204 .pm_evc_allocate_pmc = ALLOCATOR##_allocate_pmc \
205 }
206
207 #if defined(__i386__) || defined(__amd64__)
208 PMC_CLASS_TABLE_DESC(k8, K8, k8, k8);
209 PMC_CLASS_TABLE_DESC(ibs, IBS, ibs, ibs);
210 PMC_CLASS_TABLE_DESC(tsc, TSC, tsc, tsc);
211 #endif
212 #if defined(__arm__)
213 PMC_CLASS_TABLE_DESC(cortex_a8, ARMV7, cortex_a8, armv7);
214 PMC_CLASS_TABLE_DESC(cortex_a9, ARMV7, cortex_a9, armv7);
215 #endif
216 #if defined(__aarch64__)
217 PMC_CLASS_TABLE_DESC(cortex_a53, ARMV8, cortex_a53, arm64);
218 PMC_CLASS_TABLE_DESC(cortex_a57, ARMV8, cortex_a57, arm64);
219 PMC_CLASS_TABLE_DESC(cortex_a76, ARMV8, cortex_a76, arm64);
220 PMC_CLASS_TABLE_DESC(cmn600_pmu, CMN600_PMU, cmn600_pmu, cmn600_pmu);
221 PMC_CLASS_TABLE_DESC(dmc620_pmu_cd2, DMC620_PMU_CD2, dmc620_pmu_cd2, dmc620_pmu);
222 PMC_CLASS_TABLE_DESC(dmc620_pmu_c, DMC620_PMU_C, dmc620_pmu_c, dmc620_pmu);
223 #endif
224 #if defined(__powerpc__)
225 PMC_CLASS_TABLE_DESC(ppc7450, PPC7450, ppc7450, powerpc);
226 PMC_CLASS_TABLE_DESC(ppc970, PPC970, ppc970, powerpc);
227 PMC_CLASS_TABLE_DESC(e500, E500, e500, powerpc);
228 #endif
229
230 static struct pmc_class_descr soft_class_table_descr =
231 {
232 .pm_evc_name = "SOFT-",
233 .pm_evc_name_size = sizeof("SOFT-") - 1,
234 .pm_evc_class = PMC_CLASS_SOFT,
235 .pm_evc_event_table = NULL,
236 .pm_evc_event_table_size = 0,
237 .pm_evc_allocate_pmc = soft_allocate_pmc
238 };
239
240 #undef PMC_CLASS_TABLE_DESC
241
242 static const struct pmc_class_descr **pmc_class_table;
243 #define PMC_CLASS_TABLE_SIZE cpu_info.pm_nclass
244
245 /*
246 * Mapping tables, mapping enumeration values to human readable
247 * strings.
248 */
249
250 static const char * pmc_capability_names[] = {
251 #undef __PMC_CAP
252 #define __PMC_CAP(N,V,D) #N ,
253 __PMC_CAPS()
254 };
255
256 struct pmc_class_map {
257 enum pmc_class pm_class;
258 const char *pm_name;
259 };
260
261 static const struct pmc_class_map pmc_class_names[] = {
262 #undef __PMC_CLASS
263 #define __PMC_CLASS(S,V,D) { .pm_class = PMC_CLASS_##S, .pm_name = #S } ,
264 __PMC_CLASSES()
265 };
266
267 struct pmc_cputype_map {
268 enum pmc_cputype pm_cputype;
269 const char *pm_name;
270 };
271
272 static const struct pmc_cputype_map pmc_cputype_names[] = {
273 #undef __PMC_CPU
274 #define __PMC_CPU(S, V, D) { .pm_cputype = PMC_CPU_##S, .pm_name = #S } ,
275 __PMC_CPUS()
276 };
277
278 static const char * pmc_disposition_names[] = {
279 #undef __PMC_DISP
280 #define __PMC_DISP(D) #D ,
281 __PMC_DISPOSITIONS()
282 };
283
284 static const char * pmc_mode_names[] = {
285 #undef __PMC_MODE
286 #define __PMC_MODE(M,N) #M ,
287 __PMC_MODES()
288 };
289
290 static const char * pmc_state_names[] = {
291 #undef __PMC_STATE
292 #define __PMC_STATE(S) #S ,
293 __PMC_STATES()
294 };
295
296 /*
297 * Filled in by pmc_init().
298 */
299 static int pmc_syscall = -1;
300 static struct pmc_cpuinfo cpu_info;
301 static struct pmc_op_getdyneventinfo soft_event_info;
302
303 /* Event masks for events */
304 struct pmc_masks {
305 const char *pm_name;
306 const uint64_t pm_value;
307 };
308 #define PMCMASK(N,V) { .pm_name = #N, .pm_value = (V) }
309 #define NULLMASK { .pm_name = NULL }
310
311 #if defined(__amd64__) || defined(__i386__)
312 static int
pmc_parse_mask(const struct pmc_masks * pmask,char * p,uint64_t * evmask)313 pmc_parse_mask(const struct pmc_masks *pmask, char *p, uint64_t *evmask)
314 {
315 const struct pmc_masks *pm;
316 char *q, *r;
317 int c;
318
319 if (pmask == NULL) /* no mask keywords */
320 return (-1);
321 q = strchr(p, '='); /* skip '=' */
322 if (*++q == '\0') /* no more data */
323 return (-1);
324 c = 0; /* count of mask keywords seen */
325 while ((r = strsep(&q, "+")) != NULL) {
326 for (pm = pmask; pm->pm_name && strcasecmp(r, pm->pm_name);
327 pm++)
328 ;
329 if (pm->pm_name == NULL) /* not found */
330 return (-1);
331 *evmask |= pm->pm_value;
332 c++;
333 }
334 return (c);
335 }
336 #endif
337
338 #define KWMATCH(p,kw) (strcasecmp((p), (kw)) == 0)
339 #define KWPREFIXMATCH(p,kw) (strncasecmp((p), (kw), sizeof((kw)) - 1) == 0)
340 #define EV_ALIAS(N,S) { .pm_alias = N, .pm_spec = S }
341
342 #if defined(__amd64__) || defined(__i386__)
343 /*
344 * AMD K8 PMCs.
345 *
346 */
347
348 static struct pmc_event_alias k8_aliases[] = {
349 EV_ALIAS("branches", "k8-fr-retired-taken-branches"),
350 EV_ALIAS("branch-mispredicts",
351 "k8-fr-retired-taken-branches-mispredicted"),
352 EV_ALIAS("cycles", "tsc"),
353 EV_ALIAS("dc-misses", "k8-dc-miss"),
354 EV_ALIAS("ic-misses", "k8-ic-miss"),
355 EV_ALIAS("instructions", "k8-fr-retired-x86-instructions"),
356 EV_ALIAS("interrupts", "k8-fr-taken-hardware-interrupts"),
357 EV_ALIAS("unhalted-cycles", "k8-bu-cpu-clk-unhalted"),
358 EV_ALIAS(NULL, NULL)
359 };
360
361 #define __K8MASK(N,V) PMCMASK(N,(1 << (V)))
362
363 /*
364 * Parsing tables
365 */
366
367 /* fp dispatched fpu ops */
368 static const struct pmc_masks k8_mask_fdfo[] = {
369 __K8MASK(add-pipe-excluding-junk-ops, 0),
370 __K8MASK(multiply-pipe-excluding-junk-ops, 1),
371 __K8MASK(store-pipe-excluding-junk-ops, 2),
372 __K8MASK(add-pipe-junk-ops, 3),
373 __K8MASK(multiply-pipe-junk-ops, 4),
374 __K8MASK(store-pipe-junk-ops, 5),
375 NULLMASK
376 };
377
378 /* ls segment register loads */
379 static const struct pmc_masks k8_mask_lsrl[] = {
380 __K8MASK(es, 0),
381 __K8MASK(cs, 1),
382 __K8MASK(ss, 2),
383 __K8MASK(ds, 3),
384 __K8MASK(fs, 4),
385 __K8MASK(gs, 5),
386 __K8MASK(hs, 6),
387 NULLMASK
388 };
389
390 /* ls locked operation */
391 static const struct pmc_masks k8_mask_llo[] = {
392 __K8MASK(locked-instructions, 0),
393 __K8MASK(cycles-in-request, 1),
394 __K8MASK(cycles-to-complete, 2),
395 NULLMASK
396 };
397
398 /* dc refill from {l2,system} and dc copyback */
399 static const struct pmc_masks k8_mask_dc[] = {
400 __K8MASK(invalid, 0),
401 __K8MASK(shared, 1),
402 __K8MASK(exclusive, 2),
403 __K8MASK(owner, 3),
404 __K8MASK(modified, 4),
405 NULLMASK
406 };
407
408 /* dc one bit ecc error */
409 static const struct pmc_masks k8_mask_dobee[] = {
410 __K8MASK(scrubber, 0),
411 __K8MASK(piggyback, 1),
412 NULLMASK
413 };
414
415 /* dc dispatched prefetch instructions */
416 static const struct pmc_masks k8_mask_ddpi[] = {
417 __K8MASK(load, 0),
418 __K8MASK(store, 1),
419 __K8MASK(nta, 2),
420 NULLMASK
421 };
422
423 /* dc dcache accesses by locks */
424 static const struct pmc_masks k8_mask_dabl[] = {
425 __K8MASK(accesses, 0),
426 __K8MASK(misses, 1),
427 NULLMASK
428 };
429
430 /* bu internal l2 request */
431 static const struct pmc_masks k8_mask_bilr[] = {
432 __K8MASK(ic-fill, 0),
433 __K8MASK(dc-fill, 1),
434 __K8MASK(tlb-reload, 2),
435 __K8MASK(tag-snoop, 3),
436 __K8MASK(cancelled, 4),
437 NULLMASK
438 };
439
440 /* bu fill request l2 miss */
441 static const struct pmc_masks k8_mask_bfrlm[] = {
442 __K8MASK(ic-fill, 0),
443 __K8MASK(dc-fill, 1),
444 __K8MASK(tlb-reload, 2),
445 NULLMASK
446 };
447
448 /* bu fill into l2 */
449 static const struct pmc_masks k8_mask_bfil[] = {
450 __K8MASK(dirty-l2-victim, 0),
451 __K8MASK(victim-from-l2, 1),
452 NULLMASK
453 };
454
455 /* fr retired fpu instructions */
456 static const struct pmc_masks k8_mask_frfi[] = {
457 __K8MASK(x87, 0),
458 __K8MASK(mmx-3dnow, 1),
459 __K8MASK(packed-sse-sse2, 2),
460 __K8MASK(scalar-sse-sse2, 3),
461 NULLMASK
462 };
463
464 /* fr retired fastpath double op instructions */
465 static const struct pmc_masks k8_mask_frfdoi[] = {
466 __K8MASK(low-op-pos-0, 0),
467 __K8MASK(low-op-pos-1, 1),
468 __K8MASK(low-op-pos-2, 2),
469 NULLMASK
470 };
471
472 /* fr fpu exceptions */
473 static const struct pmc_masks k8_mask_ffe[] = {
474 __K8MASK(x87-reclass-microfaults, 0),
475 __K8MASK(sse-retype-microfaults, 1),
476 __K8MASK(sse-reclass-microfaults, 2),
477 __K8MASK(sse-and-x87-microtraps, 3),
478 NULLMASK
479 };
480
481 /* nb memory controller page access event */
482 static const struct pmc_masks k8_mask_nmcpae[] = {
483 __K8MASK(page-hit, 0),
484 __K8MASK(page-miss, 1),
485 __K8MASK(page-conflict, 2),
486 NULLMASK
487 };
488
489 /* nb memory controller turnaround */
490 static const struct pmc_masks k8_mask_nmct[] = {
491 __K8MASK(dimm-turnaround, 0),
492 __K8MASK(read-to-write-turnaround, 1),
493 __K8MASK(write-to-read-turnaround, 2),
494 NULLMASK
495 };
496
497 /* nb memory controller bypass saturation */
498 static const struct pmc_masks k8_mask_nmcbs[] = {
499 __K8MASK(memory-controller-hi-pri-bypass, 0),
500 __K8MASK(memory-controller-lo-pri-bypass, 1),
501 __K8MASK(dram-controller-interface-bypass, 2),
502 __K8MASK(dram-controller-queue-bypass, 3),
503 NULLMASK
504 };
505
506 /* nb sized commands */
507 static const struct pmc_masks k8_mask_nsc[] = {
508 __K8MASK(nonpostwrszbyte, 0),
509 __K8MASK(nonpostwrszdword, 1),
510 __K8MASK(postwrszbyte, 2),
511 __K8MASK(postwrszdword, 3),
512 __K8MASK(rdszbyte, 4),
513 __K8MASK(rdszdword, 5),
514 __K8MASK(rdmodwr, 6),
515 NULLMASK
516 };
517
518 /* nb probe result */
519 static const struct pmc_masks k8_mask_npr[] = {
520 __K8MASK(probe-miss, 0),
521 __K8MASK(probe-hit, 1),
522 __K8MASK(probe-hit-dirty-no-memory-cancel, 2),
523 __K8MASK(probe-hit-dirty-with-memory-cancel, 3),
524 NULLMASK
525 };
526
527 /* nb hypertransport bus bandwidth */
528 static const struct pmc_masks k8_mask_nhbb[] = { /* HT bus bandwidth */
529 __K8MASK(command, 0),
530 __K8MASK(data, 1),
531 __K8MASK(buffer-release, 2),
532 __K8MASK(nop, 3),
533 NULLMASK
534 };
535
536 #undef __K8MASK
537
538 #define K8_KW_COUNT "count"
539 #define K8_KW_EDGE "edge"
540 #define K8_KW_INV "inv"
541 #define K8_KW_MASK "mask"
542 #define K8_KW_OS "os"
543 #define K8_KW_USR "usr"
544
545 static int
k8_allocate_pmc(enum pmc_event pe,char * ctrspec,struct pmc_op_pmcallocate * pmc_config)546 k8_allocate_pmc(enum pmc_event pe, char *ctrspec,
547 struct pmc_op_pmcallocate *pmc_config)
548 {
549 char *e, *p, *q;
550 int n;
551 uint32_t count;
552 uint64_t evmask;
553 const struct pmc_masks *pm, *pmask;
554
555 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
556 pmc_config->pm_md.pm_amd.pm_amd_config = 0;
557
558 pmask = NULL;
559 evmask = 0;
560
561 #define __K8SETMASK(M) pmask = k8_mask_##M
562
563 /* setup parsing tables */
564 switch (pe) {
565 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS:
566 __K8SETMASK(fdfo);
567 break;
568 case PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD:
569 __K8SETMASK(lsrl);
570 break;
571 case PMC_EV_K8_LS_LOCKED_OPERATION:
572 __K8SETMASK(llo);
573 break;
574 case PMC_EV_K8_DC_REFILL_FROM_L2:
575 case PMC_EV_K8_DC_REFILL_FROM_SYSTEM:
576 case PMC_EV_K8_DC_COPYBACK:
577 __K8SETMASK(dc);
578 break;
579 case PMC_EV_K8_DC_ONE_BIT_ECC_ERROR:
580 __K8SETMASK(dobee);
581 break;
582 case PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS:
583 __K8SETMASK(ddpi);
584 break;
585 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS:
586 __K8SETMASK(dabl);
587 break;
588 case PMC_EV_K8_BU_INTERNAL_L2_REQUEST:
589 __K8SETMASK(bilr);
590 break;
591 case PMC_EV_K8_BU_FILL_REQUEST_L2_MISS:
592 __K8SETMASK(bfrlm);
593 break;
594 case PMC_EV_K8_BU_FILL_INTO_L2:
595 __K8SETMASK(bfil);
596 break;
597 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS:
598 __K8SETMASK(frfi);
599 break;
600 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS:
601 __K8SETMASK(frfdoi);
602 break;
603 case PMC_EV_K8_FR_FPU_EXCEPTIONS:
604 __K8SETMASK(ffe);
605 break;
606 case PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT:
607 __K8SETMASK(nmcpae);
608 break;
609 case PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND:
610 __K8SETMASK(nmct);
611 break;
612 case PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION:
613 __K8SETMASK(nmcbs);
614 break;
615 case PMC_EV_K8_NB_SIZED_COMMANDS:
616 __K8SETMASK(nsc);
617 break;
618 case PMC_EV_K8_NB_PROBE_RESULT:
619 __K8SETMASK(npr);
620 break;
621 case PMC_EV_K8_NB_HT_BUS0_BANDWIDTH:
622 case PMC_EV_K8_NB_HT_BUS1_BANDWIDTH:
623 case PMC_EV_K8_NB_HT_BUS2_BANDWIDTH:
624 __K8SETMASK(nhbb);
625 break;
626
627 default:
628 break; /* no options defined */
629 }
630
631 while ((p = strsep(&ctrspec, ",")) != NULL) {
632 if (KWPREFIXMATCH(p, K8_KW_COUNT "=")) {
633 q = strchr(p, '=');
634 if (*++q == '\0') /* skip '=' */
635 return (-1);
636
637 count = strtol(q, &e, 0);
638 if (e == q || *e != '\0')
639 return (-1);
640
641 pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
642 pmc_config->pm_md.pm_amd.pm_amd_config |=
643 AMD_PMC_TO_COUNTER(count);
644
645 } else if (KWMATCH(p, K8_KW_EDGE)) {
646 pmc_config->pm_caps |= PMC_CAP_EDGE;
647 } else if (KWMATCH(p, K8_KW_INV)) {
648 pmc_config->pm_caps |= PMC_CAP_INVERT;
649 } else if (KWPREFIXMATCH(p, K8_KW_MASK "=")) {
650 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0)
651 return (-1);
652 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
653 } else if (KWMATCH(p, K8_KW_OS)) {
654 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
655 } else if (KWMATCH(p, K8_KW_USR)) {
656 pmc_config->pm_caps |= PMC_CAP_USER;
657 } else
658 return (-1);
659 }
660
661 /* other post processing */
662 switch (pe) {
663 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS:
664 case PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED:
665 case PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS:
666 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS:
667 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS:
668 case PMC_EV_K8_FR_FPU_EXCEPTIONS:
669 /* XXX only available in rev B and later */
670 break;
671 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS:
672 /* XXX only available in rev C and later */
673 break;
674 case PMC_EV_K8_LS_LOCKED_OPERATION:
675 /* XXX CPU Rev A,B evmask is to be zero */
676 if (evmask & (evmask - 1)) /* > 1 bit set */
677 return (-1);
678 if (evmask == 0) {
679 evmask = 0x01; /* Rev C and later: #instrs */
680 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
681 }
682 break;
683 default:
684 if (evmask == 0 && pmask != NULL) {
685 for (pm = pmask; pm->pm_name; pm++)
686 evmask |= pm->pm_value;
687 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
688 }
689 }
690
691 if (pmc_config->pm_caps & PMC_CAP_QUALIFIER)
692 pmc_config->pm_md.pm_amd.pm_amd_config =
693 AMD_PMC_TO_UNITMASK(evmask);
694
695 return (0);
696 }
697
698 static int
ibs_allocate_pmc(enum pmc_event pe,char * ctrspec,struct pmc_op_pmcallocate * pmc_config)699 ibs_allocate_pmc(enum pmc_event pe, char *ctrspec,
700 struct pmc_op_pmcallocate *pmc_config)
701 {
702 char *e, *p, *q;
703 uint64_t ctl, ldlat;
704 u_int ibs_features;
705 u_int regs[4];
706
707 pmc_config->pm_caps |=
708 (PMC_CAP_SYSTEM | PMC_CAP_EDGE | PMC_CAP_PRECISE);
709 pmc_config->pm_md.pm_ibs.ibs_ctl = 0;
710
711 /* setup parsing tables */
712 switch (pe) {
713 case PMC_EV_IBS_FETCH:
714 pmc_config->pm_md.pm_ibs.ibs_type = IBS_PMC_FETCH;
715 break;
716 case PMC_EV_IBS_OP:
717 pmc_config->pm_md.pm_ibs.ibs_type = IBS_PMC_OP;
718 break;
719 default:
720 return (-1);
721 }
722
723 /* IBS only supports sampling mode */
724 if (!PMC_IS_SAMPLING_MODE(pmc_config->pm_mode)) {
725 return (-1);
726 }
727
728 /* Read the ibs feature flags */
729 ibs_features = 0;
730 do_cpuid(0x80000000, regs);
731 if (regs[0] >= CPUID_IBSID) {
732 do_cpuid(CPUID_IBSID, regs);
733 ibs_features = regs[0];
734 }
735
736 /* parse parameters */
737 ctl = 0;
738 if (pe == PMC_EV_IBS_FETCH) {
739 while ((p = strsep(&ctrspec, ",")) != NULL) {
740 if (KWMATCH(p, "l3miss")) {
741 if ((ibs_features & CPUID_IBSID_ZEN4IBSEXTENSIONS) == 0)
742 return (-1);
743
744 ctl |= IBS_FETCH_CTL_L3MISSONLY;
745 } else if (KWMATCH(p, "randomize")) {
746 ctl |= IBS_FETCH_CTL_RANDOMIZE;
747 } else {
748 return (-1);
749 }
750 }
751
752 if (pmc_config->pm_count < IBS_FETCH_MIN_RATE ||
753 pmc_config->pm_count > IBS_FETCH_MAX_RATE)
754 return (-1);
755
756 ctl |= IBS_FETCH_INTERVAL_TO_CTL(pmc_config->pm_count);
757 } else {
758 while ((p = strsep(&ctrspec, ",")) != NULL) {
759 if (KWMATCH(p, "l3miss")) {
760 ctl |= IBS_OP_CTL_L3MISSONLY;
761 } else if (KWPREFIXMATCH(p, "ldlat=")) {
762 if ((ibs_features & CPUID_IBSID_IBSLOADLATENCYFILT) == 0)
763 return (-1);
764
765 q = strchr(p, '=');
766 if (*++q == '\0') /* skip '=' */
767 return (-1);
768
769 ldlat = strtoull(q, &e, 0);
770 if (e == q || *e != '\0')
771 return (-1);
772
773 /*
774 * IBS load latency filtering requires the
775 * latency to be a multiple of 128 and between
776 * 128 and 2048. The latency is stored in the
777 * IbsOpLatThrsh field, which only contains
778 * four bits so the processor computes
779 * (IbsOpLatThrsh+1)*128 as the value.
780 *
781 * AMD PPR Vol 1 for AMD Family 1Ah Model 02h
782 * C1 (57238) 2026-03-06 Revision 0.49.
783 */
784 if (ldlat < 128 || ldlat > 2048)
785 return (-1);
786 ctl |= IBS_OP_CTL_LDLAT_TO_CTL(ldlat);
787 ctl |= IBS_OP_CTL_L3MISSONLY | IBS_OP_CTL_LATFLTEN;
788 } else if (KWMATCH(p, "opcount")) {
789 if ((ibs_features & CPUID_IBSID_OPCNT) == 0)
790 return (-1);
791
792 ctl |= IBS_OP_CTL_COUNTERCONTROL;
793 } else {
794 return (-1);
795 }
796 }
797
798 if (pmc_config->pm_count < IBS_OP_MIN_RATE ||
799 pmc_config->pm_count > IBS_OP_MAX_RATE)
800 return (-1);
801
802 if (((ibs_features & CPUID_IBSID_OPCNTEXT) == 0) &&
803 (pmc_config->pm_count > IBS_OP_MAX_RATE_PREEXT))
804 return (-1);
805
806 ctl |= IBS_OP_INTERVAL_TO_CTL(pmc_config->pm_count);
807 }
808
809
810 pmc_config->pm_md.pm_ibs.ibs_ctl |= ctl;
811
812 return (0);
813 }
814
815 static int
tsc_allocate_pmc(enum pmc_event pe,char * ctrspec,struct pmc_op_pmcallocate * pmc_config)816 tsc_allocate_pmc(enum pmc_event pe, char *ctrspec,
817 struct pmc_op_pmcallocate *pmc_config)
818 {
819 if (pe != PMC_EV_TSC_TSC)
820 return (-1);
821
822 /* TSC events must be unqualified. */
823 if (ctrspec && *ctrspec != '\0')
824 return (-1);
825
826 pmc_config->pm_md.pm_amd.pm_amd_config = 0;
827 pmc_config->pm_caps |= PMC_CAP_READ;
828
829 return (0);
830 }
831 #endif
832
833 static struct pmc_event_alias generic_aliases[] = {
834 EV_ALIAS("instructions", "SOFT-CLOCK.HARD"),
835 EV_ALIAS(NULL, NULL)
836 };
837
838 static int
soft_allocate_pmc(enum pmc_event pe,char * ctrspec,struct pmc_op_pmcallocate * pmc_config)839 soft_allocate_pmc(enum pmc_event pe, char *ctrspec,
840 struct pmc_op_pmcallocate *pmc_config)
841 {
842 (void)ctrspec;
843 (void)pmc_config;
844
845 if ((int)pe < PMC_EV_SOFT_FIRST || (int)pe > PMC_EV_SOFT_LAST)
846 return (-1);
847
848 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
849 return (0);
850 }
851
852 #if defined(__arm__)
853 static struct pmc_event_alias cortex_a8_aliases[] = {
854 EV_ALIAS("dc-misses", "L1_DCACHE_REFILL"),
855 EV_ALIAS("ic-misses", "L1_ICACHE_REFILL"),
856 EV_ALIAS("instructions", "INSTR_EXECUTED"),
857 EV_ALIAS(NULL, NULL)
858 };
859
860 static struct pmc_event_alias cortex_a9_aliases[] = {
861 EV_ALIAS("dc-misses", "L1_DCACHE_REFILL"),
862 EV_ALIAS("ic-misses", "L1_ICACHE_REFILL"),
863 EV_ALIAS("instructions", "INSTR_EXECUTED"),
864 EV_ALIAS(NULL, NULL)
865 };
866
867 static int
armv7_allocate_pmc(enum pmc_event pe,char * ctrspec __unused,struct pmc_op_pmcallocate * pmc_config __unused)868 armv7_allocate_pmc(enum pmc_event pe, char *ctrspec __unused,
869 struct pmc_op_pmcallocate *pmc_config __unused)
870 {
871 switch (pe) {
872 default:
873 break;
874 }
875
876 return (0);
877 }
878 #endif
879
880 #if defined(__aarch64__)
881 static struct pmc_event_alias cortex_a53_aliases[] = {
882 EV_ALIAS(NULL, NULL)
883 };
884 static struct pmc_event_alias cortex_a57_aliases[] = {
885 EV_ALIAS(NULL, NULL)
886 };
887 static struct pmc_event_alias cortex_a76_aliases[] = {
888 EV_ALIAS(NULL, NULL)
889 };
890
891 static int
arm64_allocate_pmc(enum pmc_event pe,char * ctrspec,struct pmc_op_pmcallocate * pmc_config)892 arm64_allocate_pmc(enum pmc_event pe, char *ctrspec,
893 struct pmc_op_pmcallocate *pmc_config)
894 {
895 char *p;
896
897 while ((p = strsep(&ctrspec, ",")) != NULL) {
898 if (KWMATCH(p, "os"))
899 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
900 else if (KWMATCH(p, "usr"))
901 pmc_config->pm_caps |= PMC_CAP_USER;
902 else
903 return (-1);
904 }
905
906 return (0);
907 }
908
909 static int
cmn600_pmu_allocate_pmc(enum pmc_event pe,char * ctrspec,struct pmc_op_pmcallocate * pmc_config)910 cmn600_pmu_allocate_pmc(enum pmc_event pe, char *ctrspec,
911 struct pmc_op_pmcallocate *pmc_config)
912 {
913 uint32_t nodeid, occupancy, xpport, xpchannel;
914 char *e, *p, *q;
915 unsigned int i;
916 char *xpport_names[] = { "East", "West", "North", "South", "devport0",
917 "devport1" };
918 char *xpchannel_names[] = { "REQ", "RSP", "SNP", "DAT" };
919
920 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
921 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
922 pmc_config->pm_md.pm_cmn600.pma_cmn600_config = 0;
923 /*
924 * CMN600 extra fields:
925 * * nodeid - node coordinates x[2-3],y[2-3],p[1],s[2]
926 * width of x and y fields depend on matrix size.
927 * * occupancy - numeric value to select desired filter.
928 * * xpport - East, West, North, South, devport0, devport1 (or 0, 1, ..., 5)
929 * * xpchannel - REQ, RSP, SNP, DAT (or 0, 1, 2, 3)
930 */
931
932 while ((p = strsep(&ctrspec, ",")) != NULL) {
933 if (KWPREFIXMATCH(p, "nodeid=")) {
934 q = strchr(p, '=');
935 if (*++q == '\0') /* skip '=' */
936 return (-1);
937
938 nodeid = strtol(q, &e, 0);
939 if (e == q || *e != '\0')
940 return (-1);
941
942 pmc_config->pm_md.pm_cmn600.pma_cmn600_nodeid |= nodeid;
943
944 } else if (KWPREFIXMATCH(p, "occupancy=")) {
945 q = strchr(p, '=');
946 if (*++q == '\0') /* skip '=' */
947 return (-1);
948
949 occupancy = strtol(q, &e, 0);
950 if (e == q || *e != '\0')
951 return (-1);
952
953 pmc_config->pm_md.pm_cmn600.pma_cmn600_occupancy = occupancy;
954 } else if (KWPREFIXMATCH(p, "xpport=")) {
955 q = strchr(p, '=');
956 if (*++q == '\0') /* skip '=' */
957 return (-1);
958
959 xpport = strtol(q, &e, 0);
960 if (e == q || *e != '\0') {
961 for (i = 0; i < nitems(xpport_names); i++) {
962 if (strcasecmp(xpport_names[i], q) == 0) {
963 xpport = i;
964 break;
965 }
966 }
967 if (i == nitems(xpport_names))
968 return (-1);
969 }
970
971 pmc_config->pm_md.pm_cmn600.pma_cmn600_config |= xpport << 2;
972 } else if (KWPREFIXMATCH(p, "xpchannel=")) {
973 q = strchr(p, '=');
974 if (*++q == '\0') /* skip '=' */
975 return (-1);
976
977 xpchannel = strtol(q, &e, 0);
978 if (e == q || *e != '\0') {
979 for (i = 0; i < nitems(xpchannel_names); i++) {
980 if (strcasecmp(xpchannel_names[i], q) == 0) {
981 xpchannel = i;
982 break;
983 }
984 }
985 if (i == nitems(xpchannel_names))
986 return (-1);
987 }
988
989 pmc_config->pm_md.pm_cmn600.pma_cmn600_config |= xpchannel << 5;
990 } else
991 return (-1);
992 }
993
994 return (0);
995 }
996
997 static int
dmc620_pmu_allocate_pmc(enum pmc_event pe,char * ctrspec,struct pmc_op_pmcallocate * pmc_config)998 dmc620_pmu_allocate_pmc(enum pmc_event pe, char *ctrspec,
999 struct pmc_op_pmcallocate *pmc_config)
1000 {
1001 char *e, *p, *q;
1002 uint64_t match, mask;
1003 uint32_t count;
1004
1005 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
1006 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
1007 pmc_config->pm_md.pm_dmc620.pm_dmc620_config = 0;
1008
1009 while ((p = strsep(&ctrspec, ",")) != NULL) {
1010 if (KWPREFIXMATCH(p, "count=")) {
1011 q = strchr(p, '=');
1012 if (*++q == '\0') /* skip '=' */
1013 return (-1);
1014
1015 count = strtol(q, &e, 0);
1016 if (e == q || *e != '\0')
1017 return (-1);
1018
1019 pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
1020 pmc_config->pm_md.pm_dmc620.pm_dmc620_config |= count;
1021
1022 } else if (KWMATCH(p, "inv")) {
1023 pmc_config->pm_caps |= PMC_CAP_INVERT;
1024 } else if (KWPREFIXMATCH(p, "match=")) {
1025 match = strtol(q, &e, 0);
1026 if (e == q || *e != '\0')
1027 return (-1);
1028
1029 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1030 pmc_config->pm_md.pm_dmc620.pm_dmc620_match = match;
1031 } else if (KWPREFIXMATCH(p, "mask=")) {
1032 q = strchr(p, '=');
1033 if (*++q == '\0') /* skip '=' */
1034 return (-1);
1035
1036 mask = strtol(q, &e, 0);
1037 if (e == q || *e != '\0')
1038 return (-1);
1039
1040 pmc_config->pm_md.pm_dmc620.pm_dmc620_mask = mask;
1041 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1042 } else
1043 return (-1);
1044 }
1045
1046 return (0);
1047 }
1048 #endif
1049
1050 #if defined(__powerpc__)
1051
1052 static struct pmc_event_alias ppc7450_aliases[] = {
1053 EV_ALIAS("instructions", "INSTR_COMPLETED"),
1054 EV_ALIAS("branches", "BRANCHES_COMPLETED"),
1055 EV_ALIAS("branch-mispredicts", "MISPREDICTED_BRANCHES"),
1056 EV_ALIAS(NULL, NULL)
1057 };
1058
1059 static struct pmc_event_alias ppc970_aliases[] = {
1060 EV_ALIAS("instructions", "INSTR_COMPLETED"),
1061 EV_ALIAS("cycles", "CYCLES"),
1062 EV_ALIAS(NULL, NULL)
1063 };
1064
1065 static struct pmc_event_alias e500_aliases[] = {
1066 EV_ALIAS("instructions", "INSTR_COMPLETED"),
1067 EV_ALIAS("cycles", "CYCLES"),
1068 EV_ALIAS(NULL, NULL)
1069 };
1070
1071 #define POWERPC_KW_OS "os"
1072 #define POWERPC_KW_USR "usr"
1073 #define POWERPC_KW_ANYTHREAD "anythread"
1074
1075 static int
powerpc_allocate_pmc(enum pmc_event pe,char * ctrspec __unused,struct pmc_op_pmcallocate * pmc_config __unused)1076 powerpc_allocate_pmc(enum pmc_event pe, char *ctrspec __unused,
1077 struct pmc_op_pmcallocate *pmc_config __unused)
1078 {
1079 char *p;
1080
1081 (void) pe;
1082
1083 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
1084
1085 while ((p = strsep(&ctrspec, ",")) != NULL) {
1086 if (KWMATCH(p, POWERPC_KW_OS))
1087 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
1088 else if (KWMATCH(p, POWERPC_KW_USR))
1089 pmc_config->pm_caps |= PMC_CAP_USER;
1090 else if (KWMATCH(p, POWERPC_KW_ANYTHREAD))
1091 pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM);
1092 else
1093 return (-1);
1094 }
1095
1096 return (0);
1097 }
1098
1099 #endif /* __powerpc__ */
1100
1101
1102 /*
1103 * Match an event name `name' with its canonical form.
1104 *
1105 * Matches are case insensitive and spaces, periods, underscores and
1106 * hyphen characters are considered to match each other.
1107 *
1108 * Returns 1 for a match, 0 otherwise.
1109 */
1110
1111 static int
pmc_match_event_name(const char * name,const char * canonicalname)1112 pmc_match_event_name(const char *name, const char *canonicalname)
1113 {
1114 int cc, nc;
1115 const unsigned char *c, *n;
1116
1117 c = (const unsigned char *) canonicalname;
1118 n = (const unsigned char *) name;
1119
1120 for (; (nc = *n) && (cc = *c); n++, c++) {
1121
1122 if ((nc == ' ' || nc == '_' || nc == '-' || nc == '.') &&
1123 (cc == ' ' || cc == '_' || cc == '-' || cc == '.'))
1124 continue;
1125
1126 if (toupper(nc) == toupper(cc))
1127 continue;
1128
1129
1130 return (0);
1131 }
1132
1133 if (*n == '\0' && *c == '\0')
1134 return (1);
1135
1136 return (0);
1137 }
1138
1139 /*
1140 * Match an event name against all the event named supported by a
1141 * PMC class.
1142 *
1143 * Returns an event descriptor pointer on match or NULL otherwise.
1144 */
1145 static const struct pmc_event_descr *
pmc_match_event_class(const char * name,const struct pmc_class_descr * pcd)1146 pmc_match_event_class(const char *name,
1147 const struct pmc_class_descr *pcd)
1148 {
1149 size_t n;
1150 const struct pmc_event_descr *ev;
1151
1152 ev = pcd->pm_evc_event_table;
1153 for (n = 0; n < pcd->pm_evc_event_table_size; n++, ev++)
1154 if (pmc_match_event_name(name, ev->pm_ev_name))
1155 return (ev);
1156
1157 return (NULL);
1158 }
1159
1160 /*
1161 * API entry points
1162 */
1163
1164 int
pmc_allocate(const char * ctrspec,enum pmc_mode mode,uint32_t flags,int cpu,pmc_id_t * pmcid,uint64_t count)1165 pmc_allocate(const char *ctrspec, enum pmc_mode mode,
1166 uint32_t flags, int cpu, pmc_id_t *pmcid,
1167 uint64_t count)
1168 {
1169 size_t n;
1170 int retval;
1171 char *r, *spec_copy;
1172 const char *ctrname;
1173 const struct pmc_event_descr *ev;
1174 const struct pmc_event_alias *alias;
1175 struct pmc_op_pmcallocate pmc_config;
1176 const struct pmc_class_descr *pcd;
1177
1178 spec_copy = NULL;
1179 retval = -1;
1180
1181 if (mode != PMC_MODE_SS && mode != PMC_MODE_TS &&
1182 mode != PMC_MODE_SC && mode != PMC_MODE_TC) {
1183 errno = EINVAL;
1184 goto out;
1185 }
1186 bzero(&pmc_config, sizeof(pmc_config));
1187 pmc_config.pm_cpu = cpu;
1188 pmc_config.pm_mode = mode;
1189 pmc_config.pm_flags = flags;
1190 pmc_config.pm_count = count;
1191 if (PMC_IS_SAMPLING_MODE(mode))
1192 pmc_config.pm_caps |= PMC_CAP_INTERRUPT;
1193
1194 /*
1195 * Try to pull the raw event ID directly from the pmu-events table. If
1196 * this is unsupported on the platform, or the event is not found,
1197 * continue with searching the regular event tables.
1198 */
1199 r = spec_copy = strdup(ctrspec);
1200 ctrname = strsep(&r, ",");
1201 if (pmc_pmu_enabled()) {
1202 errno = pmc_pmu_pmcallocate(ctrname, &pmc_config);
1203 if (errno == 0)
1204 goto found;
1205 if (errno == EOPNOTSUPP)
1206 goto out;
1207 }
1208 free(spec_copy);
1209 spec_copy = NULL;
1210
1211 /* replace an event alias with the canonical event specifier */
1212 if (pmc_mdep_event_aliases)
1213 for (alias = pmc_mdep_event_aliases; alias->pm_alias; alias++)
1214 if (!strcasecmp(ctrspec, alias->pm_alias)) {
1215 spec_copy = strdup(alias->pm_spec);
1216 break;
1217 }
1218
1219 if (spec_copy == NULL)
1220 spec_copy = strdup(ctrspec);
1221
1222 r = spec_copy;
1223 ctrname = strsep(&r, ",");
1224
1225 /*
1226 * If a explicit class prefix was given by the user, restrict the
1227 * search for the event to the specified PMC class.
1228 */
1229 ev = NULL;
1230 for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) {
1231 pcd = pmc_class_table[n];
1232 if (pcd != NULL && strncasecmp(ctrname, pcd->pm_evc_name,
1233 pcd->pm_evc_name_size) == 0) {
1234 if ((ev = pmc_match_event_class(ctrname +
1235 pcd->pm_evc_name_size, pcd)) == NULL) {
1236 errno = EINVAL;
1237 goto out;
1238 }
1239 break;
1240 }
1241 }
1242
1243 /*
1244 * Otherwise, search for this event in all compatible PMC
1245 * classes.
1246 */
1247 for (n = 0; ev == NULL && n < PMC_CLASS_TABLE_SIZE; n++) {
1248 pcd = pmc_class_table[n];
1249 if (pcd != NULL)
1250 ev = pmc_match_event_class(ctrname, pcd);
1251 }
1252
1253 if (ev == NULL) {
1254 errno = EINVAL;
1255 goto out;
1256 }
1257
1258 pmc_config.pm_ev = ev->pm_ev_code;
1259 pmc_config.pm_class = pcd->pm_evc_class;
1260
1261 if (pcd->pm_evc_allocate_pmc(ev->pm_ev_code, r, &pmc_config) < 0) {
1262 errno = EINVAL;
1263 goto out;
1264 }
1265
1266 found:
1267 if (PMC_CALL(PMC_OP_PMCALLOCATE, &pmc_config) == 0) {
1268 *pmcid = pmc_config.pm_pmcid;
1269 retval = 0;
1270 }
1271 out:
1272 if (spec_copy)
1273 free(spec_copy);
1274
1275 return (retval);
1276 }
1277
1278 int
pmc_attach(pmc_id_t pmc,pid_t pid)1279 pmc_attach(pmc_id_t pmc, pid_t pid)
1280 {
1281 struct pmc_op_pmcattach pmc_attach_args;
1282
1283 pmc_attach_args.pm_pmc = pmc;
1284 pmc_attach_args.pm_pid = pid;
1285
1286 return (PMC_CALL(PMC_OP_PMCATTACH, &pmc_attach_args));
1287 }
1288
1289 int
pmc_capabilities(pmc_id_t pmcid,uint32_t * caps)1290 pmc_capabilities(pmc_id_t pmcid, uint32_t *caps)
1291 {
1292 struct pmc_op_caps args;
1293 int status;
1294
1295 args.pm_pmcid = pmcid;
1296 args.pm_caps = 0;
1297
1298 status = PMC_CALL(PMC_OP_GETCAPS, &args);
1299 *caps = args.pm_caps;
1300
1301 return (status);
1302 }
1303
1304 int
pmc_configure_logfile(int fd)1305 pmc_configure_logfile(int fd)
1306 {
1307 struct pmc_op_configurelog cla;
1308
1309 cla.pm_flags = 0;
1310 cla.pm_logfd = fd;
1311 if (PMC_CALL(PMC_OP_CONFIGURELOG, &cla) < 0)
1312 return (-1);
1313 return (0);
1314 }
1315
1316 int
pmc_cpuinfo(const struct pmc_cpuinfo ** pci)1317 pmc_cpuinfo(const struct pmc_cpuinfo **pci)
1318 {
1319 if (pmc_syscall == -1) {
1320 errno = ENXIO;
1321 return (-1);
1322 }
1323
1324 *pci = &cpu_info;
1325 return (0);
1326 }
1327
1328 int
pmc_detach(pmc_id_t pmc,pid_t pid)1329 pmc_detach(pmc_id_t pmc, pid_t pid)
1330 {
1331 struct pmc_op_pmcattach pmc_detach_args;
1332
1333 pmc_detach_args.pm_pmc = pmc;
1334 pmc_detach_args.pm_pid = pid;
1335 return (PMC_CALL(PMC_OP_PMCDETACH, &pmc_detach_args));
1336 }
1337
1338 int
pmc_disable(int cpu,int pmc)1339 pmc_disable(int cpu, int pmc)
1340 {
1341 struct pmc_op_pmcadmin ssa;
1342
1343 ssa.pm_cpu = cpu;
1344 ssa.pm_pmc = pmc;
1345 ssa.pm_state = PMC_STATE_DISABLED;
1346 return (PMC_CALL(PMC_OP_PMCADMIN, &ssa));
1347 }
1348
1349 int
pmc_enable(int cpu,int pmc)1350 pmc_enable(int cpu, int pmc)
1351 {
1352 struct pmc_op_pmcadmin ssa;
1353
1354 ssa.pm_cpu = cpu;
1355 ssa.pm_pmc = pmc;
1356 ssa.pm_state = PMC_STATE_FREE;
1357 return (PMC_CALL(PMC_OP_PMCADMIN, &ssa));
1358 }
1359
1360 /*
1361 * Return a list of events known to a given PMC class. 'cl' is the
1362 * PMC class identifier, 'eventnames' is the returned list of 'const
1363 * char *' pointers pointing to the names of the events. 'nevents' is
1364 * the number of event name pointers returned.
1365 *
1366 * The space for 'eventnames' is allocated using malloc(3). The caller
1367 * is responsible for freeing this space when done.
1368 */
1369 int
pmc_event_names_of_class(enum pmc_class cl,const char *** eventnames,int * nevents)1370 pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames,
1371 int *nevents)
1372 {
1373 int count;
1374 const char **names;
1375 const struct pmc_event_descr *ev;
1376
1377 switch (cl)
1378 {
1379 case PMC_CLASS_IAF:
1380 ev = iaf_event_table;
1381 count = PMC_EVENT_TABLE_SIZE(iaf);
1382 break;
1383 case PMC_CLASS_TSC:
1384 ev = tsc_event_table;
1385 count = PMC_EVENT_TABLE_SIZE(tsc);
1386 break;
1387 case PMC_CLASS_K8:
1388 ev = k8_event_table;
1389 count = PMC_EVENT_TABLE_SIZE(k8);
1390 break;
1391 case PMC_CLASS_IBS:
1392 ev = ibs_event_table;
1393 count = PMC_EVENT_TABLE_SIZE(ibs);
1394 break;
1395 case PMC_CLASS_ARMV7:
1396 switch (cpu_info.pm_cputype) {
1397 default:
1398 case PMC_CPU_ARMV7_CORTEX_A8:
1399 ev = cortex_a8_event_table;
1400 count = PMC_EVENT_TABLE_SIZE(cortex_a8);
1401 break;
1402 case PMC_CPU_ARMV7_CORTEX_A9:
1403 ev = cortex_a9_event_table;
1404 count = PMC_EVENT_TABLE_SIZE(cortex_a9);
1405 break;
1406 }
1407 break;
1408 case PMC_CLASS_ARMV8:
1409 switch (cpu_info.pm_cputype) {
1410 default:
1411 case PMC_CPU_ARMV8_CORTEX_A53:
1412 ev = cortex_a53_event_table;
1413 count = PMC_EVENT_TABLE_SIZE(cortex_a53);
1414 break;
1415 case PMC_CPU_ARMV8_CORTEX_A57:
1416 ev = cortex_a57_event_table;
1417 count = PMC_EVENT_TABLE_SIZE(cortex_a57);
1418 break;
1419 case PMC_CPU_ARMV8_CORTEX_A76:
1420 ev = cortex_a76_event_table;
1421 count = PMC_EVENT_TABLE_SIZE(cortex_a76);
1422 break;
1423 }
1424 break;
1425 case PMC_CLASS_CMN600_PMU:
1426 ev = cmn600_pmu_event_table;
1427 count = PMC_EVENT_TABLE_SIZE(cmn600_pmu);
1428 break;
1429 case PMC_CLASS_DMC620_PMU_CD2:
1430 ev = dmc620_pmu_cd2_event_table;
1431 count = PMC_EVENT_TABLE_SIZE(dmc620_pmu_cd2);
1432 break;
1433 case PMC_CLASS_DMC620_PMU_C:
1434 ev = dmc620_pmu_c_event_table;
1435 count = PMC_EVENT_TABLE_SIZE(dmc620_pmu_c);
1436 break;
1437 case PMC_CLASS_PPC7450:
1438 ev = ppc7450_event_table;
1439 count = PMC_EVENT_TABLE_SIZE(ppc7450);
1440 break;
1441 case PMC_CLASS_PPC970:
1442 ev = ppc970_event_table;
1443 count = PMC_EVENT_TABLE_SIZE(ppc970);
1444 break;
1445 case PMC_CLASS_E500:
1446 ev = e500_event_table;
1447 count = PMC_EVENT_TABLE_SIZE(e500);
1448 break;
1449 case PMC_CLASS_SOFT:
1450 ev = soft_event_table;
1451 count = soft_event_info.pm_nevent;
1452 break;
1453 default:
1454 errno = EINVAL;
1455 return (-1);
1456 }
1457
1458 if ((names = malloc(count * sizeof(const char *))) == NULL)
1459 return (-1);
1460
1461 *eventnames = names;
1462 *nevents = count;
1463
1464 for (;count--; ev++, names++)
1465 *names = ev->pm_ev_name;
1466
1467 return (0);
1468 }
1469
1470 int
pmc_flush_logfile(void)1471 pmc_flush_logfile(void)
1472 {
1473 return (PMC_CALL(PMC_OP_FLUSHLOG, 0));
1474 }
1475
1476 int
pmc_close_logfile(void)1477 pmc_close_logfile(void)
1478 {
1479 return (PMC_CALL(PMC_OP_CLOSELOG, 0));
1480 }
1481
1482 int
pmc_get_driver_stats(struct pmc_driverstats * ds)1483 pmc_get_driver_stats(struct pmc_driverstats *ds)
1484 {
1485 struct pmc_op_getdriverstats gms;
1486
1487 if (PMC_CALL(PMC_OP_GETDRIVERSTATS, &gms) < 0)
1488 return (-1);
1489
1490 /* copy out fields in the current userland<->library interface */
1491 ds->pm_intr_ignored = gms.pm_intr_ignored;
1492 ds->pm_intr_processed = gms.pm_intr_processed;
1493 ds->pm_intr_bufferfull = gms.pm_intr_bufferfull;
1494 ds->pm_syscalls = gms.pm_syscalls;
1495 ds->pm_syscall_errors = gms.pm_syscall_errors;
1496 ds->pm_buffer_requests = gms.pm_buffer_requests;
1497 ds->pm_buffer_requests_failed = gms.pm_buffer_requests_failed;
1498 ds->pm_log_sweeps = gms.pm_log_sweeps;
1499 return (0);
1500 }
1501
1502 int
pmc_get_msr(pmc_id_t pmc,uint32_t * msr)1503 pmc_get_msr(pmc_id_t pmc, uint32_t *msr)
1504 {
1505 struct pmc_op_getmsr gm;
1506
1507 gm.pm_pmcid = pmc;
1508 if (PMC_CALL(PMC_OP_PMCGETMSR, &gm) < 0)
1509 return (-1);
1510 *msr = gm.pm_msr;
1511 return (0);
1512 }
1513
1514 int
pmc_init(void)1515 pmc_init(void)
1516 {
1517 int error, pmc_mod_id;
1518 unsigned int n;
1519 uint32_t abi_version;
1520 struct module_stat pmc_modstat;
1521 struct pmc_op_getcpuinfo op_cpu_info;
1522
1523 if (pmc_syscall != -1) /* already inited */
1524 return (0);
1525
1526 /* retrieve the system call number from the KLD */
1527 if ((pmc_mod_id = modfind(PMC_MODULE_NAME)) < 0)
1528 return (-1);
1529
1530 pmc_modstat.version = sizeof(struct module_stat);
1531 if ((error = modstat(pmc_mod_id, &pmc_modstat)) < 0)
1532 return (-1);
1533
1534 pmc_syscall = pmc_modstat.data.intval;
1535
1536 /* check the kernel module's ABI against our compiled-in version */
1537 abi_version = PMC_VERSION;
1538 if (PMC_CALL(PMC_OP_GETMODULEVERSION, &abi_version) < 0)
1539 return (pmc_syscall = -1);
1540
1541 /* ignore patch & minor numbers for the comparison */
1542 if ((abi_version & 0xFF000000) != (PMC_VERSION & 0xFF000000)) {
1543 errno = EPROGMISMATCH;
1544 return (pmc_syscall = -1);
1545 }
1546
1547 bzero(&op_cpu_info, sizeof(op_cpu_info));
1548 if (PMC_CALL(PMC_OP_GETCPUINFO, &op_cpu_info) < 0)
1549 return (pmc_syscall = -1);
1550
1551 cpu_info.pm_cputype = op_cpu_info.pm_cputype;
1552 cpu_info.pm_ncpu = op_cpu_info.pm_ncpu;
1553 cpu_info.pm_npmc = op_cpu_info.pm_npmc;
1554 cpu_info.pm_nclass = op_cpu_info.pm_nclass;
1555 for (n = 0; n < op_cpu_info.pm_nclass; n++)
1556 memcpy(&cpu_info.pm_classes[n], &op_cpu_info.pm_classes[n],
1557 sizeof(cpu_info.pm_classes[n]));
1558
1559 pmc_class_table = calloc(PMC_CLASS_TABLE_SIZE,
1560 sizeof(struct pmc_class_descr *));
1561
1562 if (pmc_class_table == NULL)
1563 return (-1);
1564
1565 /*
1566 * Get soft events list.
1567 */
1568 soft_event_info.pm_class = PMC_CLASS_SOFT;
1569 if (PMC_CALL(PMC_OP_GETDYNEVENTINFO, &soft_event_info) < 0)
1570 return (pmc_syscall = -1);
1571
1572 /* Map soft events to static list. */
1573 for (n = 0; n < soft_event_info.pm_nevent; n++) {
1574 soft_event_table[n].pm_ev_name =
1575 soft_event_info.pm_events[n].pm_ev_name;
1576 soft_event_table[n].pm_ev_code =
1577 soft_event_info.pm_events[n].pm_ev_code;
1578 }
1579 soft_class_table_descr.pm_evc_event_table_size = \
1580 soft_event_info.pm_nevent;
1581 soft_class_table_descr.pm_evc_event_table = \
1582 soft_event_table;
1583
1584 /*
1585 * Fill in the class table.
1586 */
1587 n = 0;
1588 for (unsigned i = 0; i < PMC_CLASS_TABLE_SIZE; i++) {
1589 switch (cpu_info.pm_classes[i].pm_class) {
1590 #if defined(__amd64__) || defined(__i386__)
1591 case PMC_CLASS_TSC:
1592 pmc_class_table[n++] = &tsc_class_table_descr;
1593 break;
1594
1595 case PMC_CLASS_K8:
1596 pmc_class_table[n++] = &k8_class_table_descr;
1597 break;
1598
1599 case PMC_CLASS_IBS:
1600 pmc_class_table[n++] = &ibs_class_table_descr;
1601 break;
1602 #endif
1603
1604 case PMC_CLASS_SOFT:
1605 pmc_class_table[n++] = &soft_class_table_descr;
1606 break;
1607
1608 #if defined(__arm__)
1609 case PMC_CLASS_ARMV7:
1610 switch (cpu_info.pm_cputype) {
1611 case PMC_CPU_ARMV7_CORTEX_A8:
1612 pmc_class_table[n++] =
1613 &cortex_a8_class_table_descr;
1614 break;
1615 case PMC_CPU_ARMV7_CORTEX_A9:
1616 pmc_class_table[n++] =
1617 &cortex_a9_class_table_descr;
1618 break;
1619 default:
1620 errno = ENXIO;
1621 return (pmc_syscall = -1);
1622 }
1623 break;
1624 #endif
1625
1626 #if defined(__aarch64__)
1627 case PMC_CLASS_ARMV8:
1628 switch (cpu_info.pm_cputype) {
1629 case PMC_CPU_ARMV8_CORTEX_A53:
1630 pmc_class_table[n++] =
1631 &cortex_a53_class_table_descr;
1632 break;
1633 case PMC_CPU_ARMV8_CORTEX_A57:
1634 pmc_class_table[n++] =
1635 &cortex_a57_class_table_descr;
1636 break;
1637 case PMC_CPU_ARMV8_CORTEX_A76:
1638 pmc_class_table[n++] =
1639 &cortex_a76_class_table_descr;
1640 break;
1641 default:
1642 errno = ENXIO;
1643 return (pmc_syscall = -1);
1644 }
1645 break;
1646
1647 case PMC_CLASS_DMC620_PMU_CD2:
1648 pmc_class_table[n++] =
1649 &dmc620_pmu_cd2_class_table_descr;
1650 break;
1651
1652 case PMC_CLASS_DMC620_PMU_C:
1653 pmc_class_table[n++] = &dmc620_pmu_c_class_table_descr;
1654 break;
1655
1656 case PMC_CLASS_CMN600_PMU:
1657 pmc_class_table[n++] = &cmn600_pmu_class_table_descr;
1658 break;
1659 #endif
1660
1661 #if defined(__powerpc__)
1662 case PMC_CLASS_PPC7450:
1663 pmc_class_table[n++] = &ppc7450_class_table_descr;
1664 break;
1665
1666 case PMC_CLASS_PPC970:
1667 pmc_class_table[n++] = &ppc970_class_table_descr;
1668 break;
1669
1670 case PMC_CLASS_E500:
1671 pmc_class_table[n++] = &e500_class_table_descr;
1672 break;
1673 #endif
1674
1675 default:
1676 #if defined(DEBUG)
1677 printf("pm_class: 0x%x\n",
1678 cpu_info.pm_classes[i].pm_class);
1679 #endif
1680 break;
1681 }
1682 }
1683
1684 #define PMC_MDEP_INIT(C) pmc_mdep_event_aliases = C##_aliases
1685
1686 /* Configure the event name parser. */
1687 switch (cpu_info.pm_cputype) {
1688 #if defined(__amd64__) || defined(__i386__)
1689 case PMC_CPU_AMD_K8:
1690 PMC_MDEP_INIT(k8);
1691 break;
1692 #endif
1693 case PMC_CPU_GENERIC:
1694 PMC_MDEP_INIT(generic);
1695 break;
1696 #if defined(__arm__)
1697 case PMC_CPU_ARMV7_CORTEX_A8:
1698 PMC_MDEP_INIT(cortex_a8);
1699 break;
1700 case PMC_CPU_ARMV7_CORTEX_A9:
1701 PMC_MDEP_INIT(cortex_a9);
1702 break;
1703 #endif
1704 #if defined(__aarch64__)
1705 case PMC_CPU_ARMV8_CORTEX_A53:
1706 PMC_MDEP_INIT(cortex_a53);
1707 break;
1708 case PMC_CPU_ARMV8_CORTEX_A57:
1709 PMC_MDEP_INIT(cortex_a57);
1710 break;
1711 case PMC_CPU_ARMV8_CORTEX_A76:
1712 PMC_MDEP_INIT(cortex_a76);
1713 break;
1714 #endif
1715 #if defined(__powerpc__)
1716 case PMC_CPU_PPC_7450:
1717 PMC_MDEP_INIT(ppc7450);
1718 break;
1719 case PMC_CPU_PPC_970:
1720 PMC_MDEP_INIT(ppc970);
1721 break;
1722 case PMC_CPU_PPC_E500:
1723 PMC_MDEP_INIT(e500);
1724 break;
1725 #endif
1726 default:
1727 /*
1728 * Some kind of CPU this version of the library knows nothing
1729 * about. This shouldn't happen since the abi version check
1730 * should have caught this.
1731 */
1732 #if defined(__amd64__) || defined(__i386__) || defined(__powerpc64__)
1733 break;
1734 #endif
1735 errno = ENXIO;
1736 return (pmc_syscall = -1);
1737 }
1738
1739 return (0);
1740 }
1741
1742 const char *
pmc_name_of_capability(enum pmc_caps cap)1743 pmc_name_of_capability(enum pmc_caps cap)
1744 {
1745 int i;
1746
1747 /*
1748 * 'cap' should have a single bit set and should be in
1749 * range.
1750 */
1751 if ((cap & (cap - 1)) || cap < PMC_CAP_FIRST ||
1752 cap > PMC_CAP_LAST) {
1753 errno = EINVAL;
1754 return (NULL);
1755 }
1756
1757 i = ffs(cap);
1758 return (pmc_capability_names[i - 1]);
1759 }
1760
1761 const char *
pmc_name_of_class(enum pmc_class pc)1762 pmc_name_of_class(enum pmc_class pc)
1763 {
1764 size_t n;
1765
1766 for (n = 0; n < PMC_TABLE_SIZE(pmc_class_names); n++)
1767 if (pc == pmc_class_names[n].pm_class)
1768 return (pmc_class_names[n].pm_name);
1769
1770 errno = EINVAL;
1771 return (NULL);
1772 }
1773
1774 const char *
pmc_name_of_cputype(enum pmc_cputype cp)1775 pmc_name_of_cputype(enum pmc_cputype cp)
1776 {
1777 size_t n;
1778
1779 for (n = 0; n < PMC_TABLE_SIZE(pmc_cputype_names); n++)
1780 if (cp == pmc_cputype_names[n].pm_cputype)
1781 return (pmc_cputype_names[n].pm_name);
1782
1783 errno = EINVAL;
1784 return (NULL);
1785 }
1786
1787 const char *
pmc_name_of_disposition(enum pmc_disp pd)1788 pmc_name_of_disposition(enum pmc_disp pd)
1789 {
1790 if ((int) pd >= PMC_DISP_FIRST &&
1791 pd <= PMC_DISP_LAST)
1792 return (pmc_disposition_names[pd]);
1793
1794 errno = EINVAL;
1795 return (NULL);
1796 }
1797
1798 const char *
_pmc_name_of_event(enum pmc_event pe,enum pmc_cputype cpu)1799 _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu)
1800 {
1801 const struct pmc_event_descr *ev, *evfence;
1802
1803 ev = evfence = NULL;
1804 if (pe >= PMC_EV_K8_FIRST && pe <= PMC_EV_K8_LAST) {
1805 ev = k8_event_table;
1806 evfence = k8_event_table + PMC_EVENT_TABLE_SIZE(k8);
1807 } else if (pe >= PMC_EV_IBS_FIRST && pe <= PMC_EV_IBS_LAST) {
1808 ev = ibs_event_table;
1809 evfence = ibs_event_table + PMC_EVENT_TABLE_SIZE(ibs);
1810 } else if (pe >= PMC_EV_ARMV7_FIRST && pe <= PMC_EV_ARMV7_LAST) {
1811 switch (cpu) {
1812 case PMC_CPU_ARMV7_CORTEX_A8:
1813 ev = cortex_a8_event_table;
1814 evfence = cortex_a8_event_table + PMC_EVENT_TABLE_SIZE(cortex_a8);
1815 break;
1816 case PMC_CPU_ARMV7_CORTEX_A9:
1817 ev = cortex_a9_event_table;
1818 evfence = cortex_a9_event_table + PMC_EVENT_TABLE_SIZE(cortex_a9);
1819 break;
1820 default: /* Unknown CPU type. */
1821 break;
1822 }
1823 } else if (pe >= PMC_EV_ARMV8_FIRST && pe <= PMC_EV_ARMV8_LAST) {
1824 switch (cpu) {
1825 case PMC_CPU_ARMV8_CORTEX_A53:
1826 ev = cortex_a53_event_table;
1827 evfence = cortex_a53_event_table + PMC_EVENT_TABLE_SIZE(cortex_a53);
1828 break;
1829 case PMC_CPU_ARMV8_CORTEX_A57:
1830 ev = cortex_a57_event_table;
1831 evfence = cortex_a57_event_table + PMC_EVENT_TABLE_SIZE(cortex_a57);
1832 break;
1833 case PMC_CPU_ARMV8_CORTEX_A76:
1834 ev = cortex_a76_event_table;
1835 evfence = cortex_a76_event_table + PMC_EVENT_TABLE_SIZE(cortex_a76);
1836 break;
1837 default: /* Unknown CPU type. */
1838 break;
1839 }
1840 } else if (pe >= PMC_EV_CMN600_PMU_FIRST &&
1841 pe <= PMC_EV_CMN600_PMU_LAST) {
1842 ev = cmn600_pmu_event_table;
1843 evfence = cmn600_pmu_event_table +
1844 PMC_EVENT_TABLE_SIZE(cmn600_pmu);
1845 } else if (pe >= PMC_EV_DMC620_PMU_CD2_FIRST &&
1846 pe <= PMC_EV_DMC620_PMU_CD2_LAST) {
1847 ev = dmc620_pmu_cd2_event_table;
1848 evfence = dmc620_pmu_cd2_event_table +
1849 PMC_EVENT_TABLE_SIZE(dmc620_pmu_cd2);
1850 } else if (pe >= PMC_EV_DMC620_PMU_C_FIRST &&
1851 pe <= PMC_EV_DMC620_PMU_C_LAST) {
1852 ev = dmc620_pmu_c_event_table;
1853 evfence = dmc620_pmu_c_event_table +
1854 PMC_EVENT_TABLE_SIZE(dmc620_pmu_c);
1855 } else if (pe >= PMC_EV_PPC7450_FIRST && pe <= PMC_EV_PPC7450_LAST) {
1856 ev = ppc7450_event_table;
1857 evfence = ppc7450_event_table + PMC_EVENT_TABLE_SIZE(ppc7450);
1858 } else if (pe >= PMC_EV_PPC970_FIRST && pe <= PMC_EV_PPC970_LAST) {
1859 ev = ppc970_event_table;
1860 evfence = ppc970_event_table + PMC_EVENT_TABLE_SIZE(ppc970);
1861 } else if (pe >= PMC_EV_E500_FIRST && pe <= PMC_EV_E500_LAST) {
1862 ev = e500_event_table;
1863 evfence = e500_event_table + PMC_EVENT_TABLE_SIZE(e500);
1864 } else if (pe == PMC_EV_TSC_TSC) {
1865 ev = tsc_event_table;
1866 evfence = tsc_event_table + PMC_EVENT_TABLE_SIZE(tsc);
1867 } else if ((int)pe >= PMC_EV_SOFT_FIRST && (int)pe <= PMC_EV_SOFT_LAST) {
1868 ev = soft_event_table;
1869 evfence = soft_event_table + soft_event_info.pm_nevent;
1870 }
1871
1872 for (; ev != evfence; ev++)
1873 if (pe == ev->pm_ev_code)
1874 return (ev->pm_ev_name);
1875
1876 return (NULL);
1877 }
1878
1879 const char *
pmc_name_of_event(enum pmc_event pe)1880 pmc_name_of_event(enum pmc_event pe)
1881 {
1882 const char *n;
1883
1884 if ((n = _pmc_name_of_event(pe, cpu_info.pm_cputype)) != NULL)
1885 return (n);
1886
1887 errno = EINVAL;
1888 return (NULL);
1889 }
1890
1891 const char *
pmc_name_of_mode(enum pmc_mode pm)1892 pmc_name_of_mode(enum pmc_mode pm)
1893 {
1894 if ((int) pm >= PMC_MODE_FIRST &&
1895 pm <= PMC_MODE_LAST)
1896 return (pmc_mode_names[pm]);
1897
1898 errno = EINVAL;
1899 return (NULL);
1900 }
1901
1902 const char *
pmc_name_of_state(enum pmc_state ps)1903 pmc_name_of_state(enum pmc_state ps)
1904 {
1905 if ((int) ps >= PMC_STATE_FIRST &&
1906 ps <= PMC_STATE_LAST)
1907 return (pmc_state_names[ps]);
1908
1909 errno = EINVAL;
1910 return (NULL);
1911 }
1912
1913 int
pmc_ncpu(void)1914 pmc_ncpu(void)
1915 {
1916 if (pmc_syscall == -1) {
1917 errno = ENXIO;
1918 return (-1);
1919 }
1920
1921 return (cpu_info.pm_ncpu);
1922 }
1923
1924 int
pmc_npmc(int cpu)1925 pmc_npmc(int cpu)
1926 {
1927 if (pmc_syscall == -1) {
1928 errno = ENXIO;
1929 return (-1);
1930 }
1931
1932 if (cpu < 0 || cpu >= (int) cpu_info.pm_ncpu) {
1933 errno = EINVAL;
1934 return (-1);
1935 }
1936
1937 return (cpu_info.pm_npmc);
1938 }
1939
1940 int
pmc_pmcinfo(int cpu,struct pmc_pmcinfo ** ppmci)1941 pmc_pmcinfo(int cpu, struct pmc_pmcinfo **ppmci)
1942 {
1943 int nbytes, npmc;
1944 struct pmc_op_getpmcinfo *pmci;
1945
1946 if ((npmc = pmc_npmc(cpu)) < 0)
1947 return (-1);
1948
1949 nbytes = sizeof(struct pmc_op_getpmcinfo) +
1950 npmc * sizeof(struct pmc_info);
1951
1952 if ((pmci = calloc(1, nbytes)) == NULL)
1953 return (-1);
1954
1955 pmci->pm_cpu = cpu;
1956
1957 if (PMC_CALL(PMC_OP_GETPMCINFO, pmci) < 0) {
1958 free(pmci);
1959 return (-1);
1960 }
1961
1962 /* kernel<->library, library<->userland interfaces are identical */
1963 *ppmci = (struct pmc_pmcinfo *) pmci;
1964 return (0);
1965 }
1966
1967 int
pmc_read(pmc_id_t pmc,pmc_value_t * value)1968 pmc_read(pmc_id_t pmc, pmc_value_t *value)
1969 {
1970 struct pmc_op_pmcrw pmc_read_op;
1971
1972 pmc_read_op.pm_pmcid = pmc;
1973 pmc_read_op.pm_flags = PMC_F_OLDVALUE;
1974 pmc_read_op.pm_value = -1;
1975
1976 if (PMC_CALL(PMC_OP_PMCRW, &pmc_read_op) < 0)
1977 return (-1);
1978
1979 *value = pmc_read_op.pm_value;
1980 return (0);
1981 }
1982
1983 int
pmc_release(pmc_id_t pmc)1984 pmc_release(pmc_id_t pmc)
1985 {
1986 struct pmc_op_simple pmc_release_args;
1987
1988 pmc_release_args.pm_pmcid = pmc;
1989 return (PMC_CALL(PMC_OP_PMCRELEASE, &pmc_release_args));
1990 }
1991
1992 int
pmc_rw(pmc_id_t pmc,pmc_value_t newvalue,pmc_value_t * oldvaluep)1993 pmc_rw(pmc_id_t pmc, pmc_value_t newvalue, pmc_value_t *oldvaluep)
1994 {
1995 struct pmc_op_pmcrw pmc_rw_op;
1996
1997 pmc_rw_op.pm_pmcid = pmc;
1998 pmc_rw_op.pm_flags = PMC_F_NEWVALUE | PMC_F_OLDVALUE;
1999 pmc_rw_op.pm_value = newvalue;
2000
2001 if (PMC_CALL(PMC_OP_PMCRW, &pmc_rw_op) < 0)
2002 return (-1);
2003
2004 *oldvaluep = pmc_rw_op.pm_value;
2005 return (0);
2006 }
2007
2008 int
pmc_set(pmc_id_t pmc,pmc_value_t value)2009 pmc_set(pmc_id_t pmc, pmc_value_t value)
2010 {
2011 struct pmc_op_pmcsetcount sc;
2012
2013 sc.pm_pmcid = pmc;
2014 sc.pm_count = value;
2015
2016 if (PMC_CALL(PMC_OP_PMCSETCOUNT, &sc) < 0)
2017 return (-1);
2018 return (0);
2019 }
2020
2021 int
pmc_start(pmc_id_t pmc)2022 pmc_start(pmc_id_t pmc)
2023 {
2024 struct pmc_op_simple pmc_start_args;
2025
2026 pmc_start_args.pm_pmcid = pmc;
2027 return (PMC_CALL(PMC_OP_PMCSTART, &pmc_start_args));
2028 }
2029
2030 int
pmc_stop(pmc_id_t pmc)2031 pmc_stop(pmc_id_t pmc)
2032 {
2033 struct pmc_op_simple pmc_stop_args;
2034
2035 pmc_stop_args.pm_pmcid = pmc;
2036 return (PMC_CALL(PMC_OP_PMCSTOP, &pmc_stop_args));
2037 }
2038
2039 int
pmc_width(pmc_id_t pmcid,uint32_t * width)2040 pmc_width(pmc_id_t pmcid, uint32_t *width)
2041 {
2042 unsigned int i;
2043 enum pmc_class cl;
2044
2045 cl = PMC_ID_TO_CLASS(pmcid);
2046 for (i = 0; i < cpu_info.pm_nclass; i++)
2047 if (cpu_info.pm_classes[i].pm_class == cl) {
2048 *width = cpu_info.pm_classes[i].pm_width;
2049 return (0);
2050 }
2051 errno = EINVAL;
2052 return (-1);
2053 }
2054
2055 int
pmc_write(pmc_id_t pmc,pmc_value_t value)2056 pmc_write(pmc_id_t pmc, pmc_value_t value)
2057 {
2058 struct pmc_op_pmcrw pmc_write_op;
2059
2060 pmc_write_op.pm_pmcid = pmc;
2061 pmc_write_op.pm_flags = PMC_F_NEWVALUE;
2062 pmc_write_op.pm_value = value;
2063 return (PMC_CALL(PMC_OP_PMCRW, &pmc_write_op));
2064 }
2065
2066 int
pmc_writelog(uint32_t userdata)2067 pmc_writelog(uint32_t userdata)
2068 {
2069 struct pmc_op_writelog wl;
2070
2071 wl.pm_userdata = userdata;
2072 return (PMC_CALL(PMC_OP_WRITELOG, &wl));
2073 }
2074