1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2003-2008 Joseph Koshy 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/types.h> 30 #include <sys/param.h> 31 #include <sys/module.h> 32 #include <sys/pmc.h> 33 #include <sys/syscall.h> 34 35 #if defined(__amd64__) || defined(__i386__) 36 #include <machine/cpufunc.h> 37 #endif 38 39 #include <ctype.h> 40 #include <errno.h> 41 #include <err.h> 42 #include <fcntl.h> 43 #include <pmc.h> 44 #include <stdio.h> 45 #include <stdlib.h> 46 #include <string.h> 47 #include <strings.h> 48 #include <sysexits.h> 49 #include <unistd.h> 50 51 #include "libpmcinternal.h" 52 53 /* Function prototypes */ 54 #if defined(__amd64__) || defined(__i386__) 55 static int k8_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 56 struct pmc_op_pmcallocate *_pmc_config); 57 static int ibs_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 58 struct pmc_op_pmcallocate *_pmc_config); 59 static int tsc_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 60 struct pmc_op_pmcallocate *_pmc_config); 61 #endif 62 #if defined(__arm__) 63 static int armv7_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 64 struct pmc_op_pmcallocate *_pmc_config); 65 #endif 66 #if defined(__aarch64__) 67 static int arm64_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 68 struct pmc_op_pmcallocate *_pmc_config); 69 static int cmn600_pmu_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 70 struct pmc_op_pmcallocate *_pmc_config); 71 static int dmc620_pmu_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 72 struct pmc_op_pmcallocate *_pmc_config); 73 #endif 74 static int soft_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 75 struct pmc_op_pmcallocate *_pmc_config); 76 77 #if defined(__powerpc__) 78 static int powerpc_allocate_pmc(enum pmc_event _pe, char* ctrspec, 79 struct pmc_op_pmcallocate *_pmc_config); 80 #endif /* __powerpc__ */ 81 82 #define PMC_CALL(op, params) syscall(pmc_syscall, (op), (params)) 83 84 /* 85 * Event aliases provide a way for the user to ask for generic events 86 * like "cache-misses", or "instructions-retired". These aliases are 87 * mapped to the appropriate canonical event descriptions using a 88 * lookup table. 89 */ 90 struct pmc_event_alias { 91 const char *pm_alias; 92 const char *pm_spec; 93 }; 94 95 static const struct pmc_event_alias *pmc_mdep_event_aliases; 96 97 /* 98 * The pmc_event_descr structure maps symbolic names known to the user 99 * to integer codes used by the PMC KLD. 100 */ 101 struct pmc_event_descr { 102 const char *pm_ev_name; 103 enum pmc_event pm_ev_code; 104 }; 105 106 /* 107 * The pmc_class_descr structure maps class name prefixes for 108 * event names to event tables and other PMC class data. 109 */ 110 struct pmc_class_descr { 111 const char *pm_evc_name; 112 size_t pm_evc_name_size; 113 enum pmc_class pm_evc_class; 114 const struct pmc_event_descr *pm_evc_event_table; 115 size_t pm_evc_event_table_size; 116 int (*pm_evc_allocate_pmc)(enum pmc_event _pe, 117 char *_ctrspec, struct pmc_op_pmcallocate *_pa); 118 }; 119 120 #define PMC_TABLE_SIZE(N) (sizeof(N)/sizeof(N[0])) 121 #define PMC_EVENT_TABLE_SIZE(N) PMC_TABLE_SIZE(N##_event_table) 122 123 #undef __PMC_EV 124 #define __PMC_EV(C,N) { #N, PMC_EV_ ## C ## _ ## N }, 125 126 /* 127 * PMC_CLASSDEP_TABLE(NAME, CLASS) 128 * 129 * Define a table mapping event names and aliases to HWPMC event IDs. 130 */ 131 #define PMC_CLASSDEP_TABLE(N, C) \ 132 static const struct pmc_event_descr N##_event_table[] = \ 133 { \ 134 __PMC_EV_##C() \ 135 } 136 137 PMC_CLASSDEP_TABLE(iaf, IAF); 138 PMC_CLASSDEP_TABLE(k8, K8); 139 PMC_CLASSDEP_TABLE(ibs, IBS); 140 PMC_CLASSDEP_TABLE(armv7, ARMV7); 141 PMC_CLASSDEP_TABLE(armv8, ARMV8); 142 PMC_CLASSDEP_TABLE(cmn600_pmu, CMN600_PMU); 143 PMC_CLASSDEP_TABLE(dmc620_pmu_cd2, DMC620_PMU_CD2); 144 PMC_CLASSDEP_TABLE(dmc620_pmu_c, DMC620_PMU_C); 145 PMC_CLASSDEP_TABLE(ppc7450, PPC7450); 146 PMC_CLASSDEP_TABLE(ppc970, PPC970); 147 PMC_CLASSDEP_TABLE(e500, E500); 148 149 static struct pmc_event_descr soft_event_table[PMC_EV_DYN_COUNT]; 150 151 #undef __PMC_EV_ALIAS 152 #define __PMC_EV_ALIAS(N,CODE) { N, PMC_EV_##CODE }, 153 154 /* 155 * TODO: Factor out the __PMC_EV_ARMV7/8 list into a single separate table 156 * rather than duplicating for each core. 157 */ 158 159 static const struct pmc_event_descr cortex_a8_event_table[] = 160 { 161 __PMC_EV_ALIAS_ARMV7_CORTEX_A8() 162 __PMC_EV_ARMV7() 163 }; 164 165 static const struct pmc_event_descr cortex_a9_event_table[] = 166 { 167 __PMC_EV_ALIAS_ARMV7_CORTEX_A9() 168 __PMC_EV_ARMV7() 169 }; 170 171 static const struct pmc_event_descr cortex_a53_event_table[] = 172 { 173 __PMC_EV_ALIAS_ARMV8_CORTEX_A53() 174 __PMC_EV_ARMV8() 175 }; 176 177 static const struct pmc_event_descr cortex_a57_event_table[] = 178 { 179 __PMC_EV_ALIAS_ARMV8_CORTEX_A57() 180 __PMC_EV_ARMV8() 181 }; 182 183 static const struct pmc_event_descr cortex_a76_event_table[] = 184 { 185 __PMC_EV_ALIAS_ARMV8_CORTEX_A76() 186 __PMC_EV_ARMV8() 187 }; 188 189 static const struct pmc_event_descr tsc_event_table[] = 190 { 191 __PMC_EV_ALIAS_TSC() 192 }; 193 194 #undef PMC_CLASS_TABLE_DESC 195 #define PMC_CLASS_TABLE_DESC(NAME, CLASS, EVENTS, ALLOCATOR) \ 196 static const struct pmc_class_descr NAME##_class_table_descr = \ 197 { \ 198 .pm_evc_name = #CLASS "-", \ 199 .pm_evc_name_size = sizeof(#CLASS "-") - 1, \ 200 .pm_evc_class = PMC_CLASS_##CLASS , \ 201 .pm_evc_event_table = EVENTS##_event_table , \ 202 .pm_evc_event_table_size = \ 203 PMC_EVENT_TABLE_SIZE(EVENTS), \ 204 .pm_evc_allocate_pmc = ALLOCATOR##_allocate_pmc \ 205 } 206 207 #if defined(__i386__) || defined(__amd64__) 208 PMC_CLASS_TABLE_DESC(k8, K8, k8, k8); 209 PMC_CLASS_TABLE_DESC(ibs, IBS, ibs, ibs); 210 PMC_CLASS_TABLE_DESC(tsc, TSC, tsc, tsc); 211 #endif 212 #if defined(__arm__) 213 PMC_CLASS_TABLE_DESC(cortex_a8, ARMV7, cortex_a8, armv7); 214 PMC_CLASS_TABLE_DESC(cortex_a9, ARMV7, cortex_a9, armv7); 215 #endif 216 #if defined(__aarch64__) 217 PMC_CLASS_TABLE_DESC(cortex_a53, ARMV8, cortex_a53, arm64); 218 PMC_CLASS_TABLE_DESC(cortex_a57, ARMV8, cortex_a57, arm64); 219 PMC_CLASS_TABLE_DESC(cortex_a76, ARMV8, cortex_a76, arm64); 220 PMC_CLASS_TABLE_DESC(cmn600_pmu, CMN600_PMU, cmn600_pmu, cmn600_pmu); 221 PMC_CLASS_TABLE_DESC(dmc620_pmu_cd2, DMC620_PMU_CD2, dmc620_pmu_cd2, dmc620_pmu); 222 PMC_CLASS_TABLE_DESC(dmc620_pmu_c, DMC620_PMU_C, dmc620_pmu_c, dmc620_pmu); 223 #endif 224 #if defined(__powerpc__) 225 PMC_CLASS_TABLE_DESC(ppc7450, PPC7450, ppc7450, powerpc); 226 PMC_CLASS_TABLE_DESC(ppc970, PPC970, ppc970, powerpc); 227 PMC_CLASS_TABLE_DESC(e500, E500, e500, powerpc); 228 #endif 229 230 static struct pmc_class_descr soft_class_table_descr = 231 { 232 .pm_evc_name = "SOFT-", 233 .pm_evc_name_size = sizeof("SOFT-") - 1, 234 .pm_evc_class = PMC_CLASS_SOFT, 235 .pm_evc_event_table = NULL, 236 .pm_evc_event_table_size = 0, 237 .pm_evc_allocate_pmc = soft_allocate_pmc 238 }; 239 240 #undef PMC_CLASS_TABLE_DESC 241 242 static const struct pmc_class_descr **pmc_class_table; 243 #define PMC_CLASS_TABLE_SIZE cpu_info.pm_nclass 244 245 /* 246 * Mapping tables, mapping enumeration values to human readable 247 * strings. 248 */ 249 250 static const char * pmc_capability_names[] = { 251 #undef __PMC_CAP 252 #define __PMC_CAP(N,V,D) #N , 253 __PMC_CAPS() 254 }; 255 256 struct pmc_class_map { 257 enum pmc_class pm_class; 258 const char *pm_name; 259 }; 260 261 static const struct pmc_class_map pmc_class_names[] = { 262 #undef __PMC_CLASS 263 #define __PMC_CLASS(S,V,D) { .pm_class = PMC_CLASS_##S, .pm_name = #S } , 264 __PMC_CLASSES() 265 }; 266 267 struct pmc_cputype_map { 268 enum pmc_cputype pm_cputype; 269 const char *pm_name; 270 }; 271 272 static const struct pmc_cputype_map pmc_cputype_names[] = { 273 #undef __PMC_CPU 274 #define __PMC_CPU(S, V, D) { .pm_cputype = PMC_CPU_##S, .pm_name = #S } , 275 __PMC_CPUS() 276 }; 277 278 static const char * pmc_disposition_names[] = { 279 #undef __PMC_DISP 280 #define __PMC_DISP(D) #D , 281 __PMC_DISPOSITIONS() 282 }; 283 284 static const char * pmc_mode_names[] = { 285 #undef __PMC_MODE 286 #define __PMC_MODE(M,N) #M , 287 __PMC_MODES() 288 }; 289 290 static const char * pmc_state_names[] = { 291 #undef __PMC_STATE 292 #define __PMC_STATE(S) #S , 293 __PMC_STATES() 294 }; 295 296 /* 297 * Filled in by pmc_init(). 298 */ 299 static int pmc_syscall = -1; 300 static struct pmc_cpuinfo cpu_info; 301 static struct pmc_op_getdyneventinfo soft_event_info; 302 303 /* Event masks for events */ 304 struct pmc_masks { 305 const char *pm_name; 306 const uint64_t pm_value; 307 }; 308 #define PMCMASK(N,V) { .pm_name = #N, .pm_value = (V) } 309 #define NULLMASK { .pm_name = NULL } 310 311 #if defined(__amd64__) || defined(__i386__) 312 static int 313 pmc_parse_mask(const struct pmc_masks *pmask, char *p, uint64_t *evmask) 314 { 315 const struct pmc_masks *pm; 316 char *q, *r; 317 int c; 318 319 if (pmask == NULL) /* no mask keywords */ 320 return (-1); 321 q = strchr(p, '='); /* skip '=' */ 322 if (*++q == '\0') /* no more data */ 323 return (-1); 324 c = 0; /* count of mask keywords seen */ 325 while ((r = strsep(&q, "+")) != NULL) { 326 for (pm = pmask; pm->pm_name && strcasecmp(r, pm->pm_name); 327 pm++) 328 ; 329 if (pm->pm_name == NULL) /* not found */ 330 return (-1); 331 *evmask |= pm->pm_value; 332 c++; 333 } 334 return (c); 335 } 336 #endif 337 338 #define KWMATCH(p,kw) (strcasecmp((p), (kw)) == 0) 339 #define KWPREFIXMATCH(p,kw) (strncasecmp((p), (kw), sizeof((kw)) - 1) == 0) 340 #define EV_ALIAS(N,S) { .pm_alias = N, .pm_spec = S } 341 342 #if defined(__amd64__) || defined(__i386__) 343 /* 344 * AMD K8 PMCs. 345 * 346 */ 347 348 static struct pmc_event_alias k8_aliases[] = { 349 EV_ALIAS("branches", "k8-fr-retired-taken-branches"), 350 EV_ALIAS("branch-mispredicts", 351 "k8-fr-retired-taken-branches-mispredicted"), 352 EV_ALIAS("cycles", "tsc"), 353 EV_ALIAS("dc-misses", "k8-dc-miss"), 354 EV_ALIAS("ic-misses", "k8-ic-miss"), 355 EV_ALIAS("instructions", "k8-fr-retired-x86-instructions"), 356 EV_ALIAS("interrupts", "k8-fr-taken-hardware-interrupts"), 357 EV_ALIAS("unhalted-cycles", "k8-bu-cpu-clk-unhalted"), 358 EV_ALIAS(NULL, NULL) 359 }; 360 361 #define __K8MASK(N,V) PMCMASK(N,(1 << (V))) 362 363 /* 364 * Parsing tables 365 */ 366 367 /* fp dispatched fpu ops */ 368 static const struct pmc_masks k8_mask_fdfo[] = { 369 __K8MASK(add-pipe-excluding-junk-ops, 0), 370 __K8MASK(multiply-pipe-excluding-junk-ops, 1), 371 __K8MASK(store-pipe-excluding-junk-ops, 2), 372 __K8MASK(add-pipe-junk-ops, 3), 373 __K8MASK(multiply-pipe-junk-ops, 4), 374 __K8MASK(store-pipe-junk-ops, 5), 375 NULLMASK 376 }; 377 378 /* ls segment register loads */ 379 static const struct pmc_masks k8_mask_lsrl[] = { 380 __K8MASK(es, 0), 381 __K8MASK(cs, 1), 382 __K8MASK(ss, 2), 383 __K8MASK(ds, 3), 384 __K8MASK(fs, 4), 385 __K8MASK(gs, 5), 386 __K8MASK(hs, 6), 387 NULLMASK 388 }; 389 390 /* ls locked operation */ 391 static const struct pmc_masks k8_mask_llo[] = { 392 __K8MASK(locked-instructions, 0), 393 __K8MASK(cycles-in-request, 1), 394 __K8MASK(cycles-to-complete, 2), 395 NULLMASK 396 }; 397 398 /* dc refill from {l2,system} and dc copyback */ 399 static const struct pmc_masks k8_mask_dc[] = { 400 __K8MASK(invalid, 0), 401 __K8MASK(shared, 1), 402 __K8MASK(exclusive, 2), 403 __K8MASK(owner, 3), 404 __K8MASK(modified, 4), 405 NULLMASK 406 }; 407 408 /* dc one bit ecc error */ 409 static const struct pmc_masks k8_mask_dobee[] = { 410 __K8MASK(scrubber, 0), 411 __K8MASK(piggyback, 1), 412 NULLMASK 413 }; 414 415 /* dc dispatched prefetch instructions */ 416 static const struct pmc_masks k8_mask_ddpi[] = { 417 __K8MASK(load, 0), 418 __K8MASK(store, 1), 419 __K8MASK(nta, 2), 420 NULLMASK 421 }; 422 423 /* dc dcache accesses by locks */ 424 static const struct pmc_masks k8_mask_dabl[] = { 425 __K8MASK(accesses, 0), 426 __K8MASK(misses, 1), 427 NULLMASK 428 }; 429 430 /* bu internal l2 request */ 431 static const struct pmc_masks k8_mask_bilr[] = { 432 __K8MASK(ic-fill, 0), 433 __K8MASK(dc-fill, 1), 434 __K8MASK(tlb-reload, 2), 435 __K8MASK(tag-snoop, 3), 436 __K8MASK(cancelled, 4), 437 NULLMASK 438 }; 439 440 /* bu fill request l2 miss */ 441 static const struct pmc_masks k8_mask_bfrlm[] = { 442 __K8MASK(ic-fill, 0), 443 __K8MASK(dc-fill, 1), 444 __K8MASK(tlb-reload, 2), 445 NULLMASK 446 }; 447 448 /* bu fill into l2 */ 449 static const struct pmc_masks k8_mask_bfil[] = { 450 __K8MASK(dirty-l2-victim, 0), 451 __K8MASK(victim-from-l2, 1), 452 NULLMASK 453 }; 454 455 /* fr retired fpu instructions */ 456 static const struct pmc_masks k8_mask_frfi[] = { 457 __K8MASK(x87, 0), 458 __K8MASK(mmx-3dnow, 1), 459 __K8MASK(packed-sse-sse2, 2), 460 __K8MASK(scalar-sse-sse2, 3), 461 NULLMASK 462 }; 463 464 /* fr retired fastpath double op instructions */ 465 static const struct pmc_masks k8_mask_frfdoi[] = { 466 __K8MASK(low-op-pos-0, 0), 467 __K8MASK(low-op-pos-1, 1), 468 __K8MASK(low-op-pos-2, 2), 469 NULLMASK 470 }; 471 472 /* fr fpu exceptions */ 473 static const struct pmc_masks k8_mask_ffe[] = { 474 __K8MASK(x87-reclass-microfaults, 0), 475 __K8MASK(sse-retype-microfaults, 1), 476 __K8MASK(sse-reclass-microfaults, 2), 477 __K8MASK(sse-and-x87-microtraps, 3), 478 NULLMASK 479 }; 480 481 /* nb memory controller page access event */ 482 static const struct pmc_masks k8_mask_nmcpae[] = { 483 __K8MASK(page-hit, 0), 484 __K8MASK(page-miss, 1), 485 __K8MASK(page-conflict, 2), 486 NULLMASK 487 }; 488 489 /* nb memory controller turnaround */ 490 static const struct pmc_masks k8_mask_nmct[] = { 491 __K8MASK(dimm-turnaround, 0), 492 __K8MASK(read-to-write-turnaround, 1), 493 __K8MASK(write-to-read-turnaround, 2), 494 NULLMASK 495 }; 496 497 /* nb memory controller bypass saturation */ 498 static const struct pmc_masks k8_mask_nmcbs[] = { 499 __K8MASK(memory-controller-hi-pri-bypass, 0), 500 __K8MASK(memory-controller-lo-pri-bypass, 1), 501 __K8MASK(dram-controller-interface-bypass, 2), 502 __K8MASK(dram-controller-queue-bypass, 3), 503 NULLMASK 504 }; 505 506 /* nb sized commands */ 507 static const struct pmc_masks k8_mask_nsc[] = { 508 __K8MASK(nonpostwrszbyte, 0), 509 __K8MASK(nonpostwrszdword, 1), 510 __K8MASK(postwrszbyte, 2), 511 __K8MASK(postwrszdword, 3), 512 __K8MASK(rdszbyte, 4), 513 __K8MASK(rdszdword, 5), 514 __K8MASK(rdmodwr, 6), 515 NULLMASK 516 }; 517 518 /* nb probe result */ 519 static const struct pmc_masks k8_mask_npr[] = { 520 __K8MASK(probe-miss, 0), 521 __K8MASK(probe-hit, 1), 522 __K8MASK(probe-hit-dirty-no-memory-cancel, 2), 523 __K8MASK(probe-hit-dirty-with-memory-cancel, 3), 524 NULLMASK 525 }; 526 527 /* nb hypertransport bus bandwidth */ 528 static const struct pmc_masks k8_mask_nhbb[] = { /* HT bus bandwidth */ 529 __K8MASK(command, 0), 530 __K8MASK(data, 1), 531 __K8MASK(buffer-release, 2), 532 __K8MASK(nop, 3), 533 NULLMASK 534 }; 535 536 #undef __K8MASK 537 538 #define K8_KW_COUNT "count" 539 #define K8_KW_EDGE "edge" 540 #define K8_KW_INV "inv" 541 #define K8_KW_MASK "mask" 542 #define K8_KW_OS "os" 543 #define K8_KW_USR "usr" 544 545 static int 546 k8_allocate_pmc(enum pmc_event pe, char *ctrspec, 547 struct pmc_op_pmcallocate *pmc_config) 548 { 549 char *e, *p, *q; 550 int n; 551 uint32_t count; 552 uint64_t evmask; 553 const struct pmc_masks *pm, *pmask; 554 555 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 556 pmc_config->pm_md.pm_amd.pm_amd_config = 0; 557 558 pmask = NULL; 559 evmask = 0; 560 561 #define __K8SETMASK(M) pmask = k8_mask_##M 562 563 /* setup parsing tables */ 564 switch (pe) { 565 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS: 566 __K8SETMASK(fdfo); 567 break; 568 case PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD: 569 __K8SETMASK(lsrl); 570 break; 571 case PMC_EV_K8_LS_LOCKED_OPERATION: 572 __K8SETMASK(llo); 573 break; 574 case PMC_EV_K8_DC_REFILL_FROM_L2: 575 case PMC_EV_K8_DC_REFILL_FROM_SYSTEM: 576 case PMC_EV_K8_DC_COPYBACK: 577 __K8SETMASK(dc); 578 break; 579 case PMC_EV_K8_DC_ONE_BIT_ECC_ERROR: 580 __K8SETMASK(dobee); 581 break; 582 case PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS: 583 __K8SETMASK(ddpi); 584 break; 585 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS: 586 __K8SETMASK(dabl); 587 break; 588 case PMC_EV_K8_BU_INTERNAL_L2_REQUEST: 589 __K8SETMASK(bilr); 590 break; 591 case PMC_EV_K8_BU_FILL_REQUEST_L2_MISS: 592 __K8SETMASK(bfrlm); 593 break; 594 case PMC_EV_K8_BU_FILL_INTO_L2: 595 __K8SETMASK(bfil); 596 break; 597 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS: 598 __K8SETMASK(frfi); 599 break; 600 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS: 601 __K8SETMASK(frfdoi); 602 break; 603 case PMC_EV_K8_FR_FPU_EXCEPTIONS: 604 __K8SETMASK(ffe); 605 break; 606 case PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT: 607 __K8SETMASK(nmcpae); 608 break; 609 case PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND: 610 __K8SETMASK(nmct); 611 break; 612 case PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION: 613 __K8SETMASK(nmcbs); 614 break; 615 case PMC_EV_K8_NB_SIZED_COMMANDS: 616 __K8SETMASK(nsc); 617 break; 618 case PMC_EV_K8_NB_PROBE_RESULT: 619 __K8SETMASK(npr); 620 break; 621 case PMC_EV_K8_NB_HT_BUS0_BANDWIDTH: 622 case PMC_EV_K8_NB_HT_BUS1_BANDWIDTH: 623 case PMC_EV_K8_NB_HT_BUS2_BANDWIDTH: 624 __K8SETMASK(nhbb); 625 break; 626 627 default: 628 break; /* no options defined */ 629 } 630 631 while ((p = strsep(&ctrspec, ",")) != NULL) { 632 if (KWPREFIXMATCH(p, K8_KW_COUNT "=")) { 633 q = strchr(p, '='); 634 if (*++q == '\0') /* skip '=' */ 635 return (-1); 636 637 count = strtol(q, &e, 0); 638 if (e == q || *e != '\0') 639 return (-1); 640 641 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 642 pmc_config->pm_md.pm_amd.pm_amd_config |= 643 AMD_PMC_TO_COUNTER(count); 644 645 } else if (KWMATCH(p, K8_KW_EDGE)) { 646 pmc_config->pm_caps |= PMC_CAP_EDGE; 647 } else if (KWMATCH(p, K8_KW_INV)) { 648 pmc_config->pm_caps |= PMC_CAP_INVERT; 649 } else if (KWPREFIXMATCH(p, K8_KW_MASK "=")) { 650 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) 651 return (-1); 652 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 653 } else if (KWMATCH(p, K8_KW_OS)) { 654 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 655 } else if (KWMATCH(p, K8_KW_USR)) { 656 pmc_config->pm_caps |= PMC_CAP_USER; 657 } else 658 return (-1); 659 } 660 661 /* other post processing */ 662 switch (pe) { 663 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS: 664 case PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED: 665 case PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS: 666 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS: 667 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS: 668 case PMC_EV_K8_FR_FPU_EXCEPTIONS: 669 /* XXX only available in rev B and later */ 670 break; 671 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS: 672 /* XXX only available in rev C and later */ 673 break; 674 case PMC_EV_K8_LS_LOCKED_OPERATION: 675 /* XXX CPU Rev A,B evmask is to be zero */ 676 if (evmask & (evmask - 1)) /* > 1 bit set */ 677 return (-1); 678 if (evmask == 0) { 679 evmask = 0x01; /* Rev C and later: #instrs */ 680 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 681 } 682 break; 683 default: 684 if (evmask == 0 && pmask != NULL) { 685 for (pm = pmask; pm->pm_name; pm++) 686 evmask |= pm->pm_value; 687 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 688 } 689 } 690 691 if (pmc_config->pm_caps & PMC_CAP_QUALIFIER) 692 pmc_config->pm_md.pm_amd.pm_amd_config = 693 AMD_PMC_TO_UNITMASK(evmask); 694 695 return (0); 696 } 697 698 static int 699 ibs_allocate_pmc(enum pmc_event pe, char *ctrspec, 700 struct pmc_op_pmcallocate *pmc_config) 701 { 702 char *e, *p, *q; 703 uint64_t ctl, ctl2, ldlat, fetchlat; 704 u_int ibs_features; 705 u_int regs[4]; 706 707 pmc_config->pm_caps |= 708 (PMC_CAP_SYSTEM | PMC_CAP_EDGE | PMC_CAP_PRECISE); 709 pmc_config->pm_md.pm_ibs.ibs_ctl = 0; 710 pmc_config->pm_md.pm_ibs.ibs_ctl2 = 0; 711 712 /* setup parsing tables */ 713 switch (pe) { 714 case PMC_EV_IBS_FETCH: 715 pmc_config->pm_md.pm_ibs.ibs_type = IBS_PMC_FETCH; 716 break; 717 case PMC_EV_IBS_OP: 718 pmc_config->pm_md.pm_ibs.ibs_type = IBS_PMC_OP; 719 break; 720 default: 721 return (-1); 722 } 723 724 /* IBS only supports sampling mode */ 725 if (!PMC_IS_SAMPLING_MODE(pmc_config->pm_mode)) { 726 return (-1); 727 } 728 729 /* Read the ibs feature flags */ 730 ibs_features = 0; 731 do_cpuid(0x80000000, regs); 732 if (regs[0] >= CPUID_IBSID) { 733 do_cpuid(CPUID_IBSID, regs); 734 ibs_features = regs[0]; 735 } 736 737 /* parse parameters */ 738 ctl = 0; 739 ctl2 = 0; 740 if (pe == PMC_EV_IBS_FETCH) { 741 while ((p = strsep(&ctrspec, ",")) != NULL) { 742 if (KWMATCH(p, "l3miss")) { 743 if ((ibs_features & CPUID_IBSID_ZEN4IBSEXTENSIONS) == 0) 744 return (-1); 745 746 ctl |= IBS_FETCH_CTL_L3MISSONLY; 747 } else if (KWMATCH(p, "randomize")) { 748 ctl |= IBS_FETCH_CTL_RANDOMIZE; 749 } else if (KWPREFIXMATCH(p, "fetchlat=")) { 750 if ((ibs_features & CPUID_IBSID_FETCHLATFILTERING) == 0) 751 return (-1); 752 753 q = strchr(p, '='); 754 if (*++q == '\0') 755 return (-1); 756 757 fetchlat = strtoull(q, &e, 0); 758 if (e == q || *e != '\0') 759 return (-1); 760 761 if (fetchlat < IBS_FETCH_CTL2_LAT_MIN || 762 fetchlat > IBS_FETCH_CTL2_LAT_MAX) 763 return (-1); 764 if ((fetchlat % IBS_FETCH_CTL2_LAT_STEP) != 0) 765 return (-1); 766 767 /* clear prior threshold */ 768 ctl2 &= ~IBS_FETCH_CTL2_LATFILTERMASK; 769 ctl2 |= IBS_FETCH_CTL2_LAT_TO_CTL(fetchlat); 770 } else if (KWMATCH(p, "usr")) { 771 if ((ibs_features & CPUID_IBSID_ADDRBIT63FILTERING) == 0) 772 return (-1); 773 774 pmc_config->pm_caps |= PMC_CAP_USER; 775 } else if (KWMATCH(p, "os")) { 776 if ((ibs_features & CPUID_IBSID_ADDRBIT63FILTERING) == 0) 777 return (-1); 778 779 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 780 } else { 781 return (-1); 782 } 783 } 784 785 if (pmc_config->pm_count < IBS_FETCH_MIN_RATE || 786 pmc_config->pm_count > IBS_FETCH_MAX_RATE) 787 return (-1); 788 789 ctl |= IBS_FETCH_INTERVAL_TO_CTL(pmc_config->pm_count); 790 } else { 791 while ((p = strsep(&ctrspec, ",")) != NULL) { 792 if (KWMATCH(p, "l3miss")) { 793 ctl |= IBS_OP_CTL_L3MISSONLY; 794 } else if (KWPREFIXMATCH(p, "ldlat=")) { 795 if ((ibs_features & CPUID_IBSID_IBSLOADLATENCYFILT) == 0) 796 return (-1); 797 798 q = strchr(p, '='); 799 if (*++q == '\0') /* skip '=' */ 800 return (-1); 801 802 ldlat = strtoull(q, &e, 0); 803 if (e == q || *e != '\0') 804 return (-1); 805 806 /* 807 * IBS load latency filtering requires the 808 * latency to be a multiple of 128 and between 809 * 128 and 2048. The latency is stored in the 810 * IbsOpLatThrsh field, which only contains 811 * four bits so the processor computes 812 * (IbsOpLatThrsh+1)*128 as the value. 813 * 814 * AMD PPR Vol 1 for AMD Family 1Ah Model 02h 815 * C1 (57238) 2026-03-06 Revision 0.49. 816 */ 817 if (ldlat < 128 || ldlat > 2048) 818 return (-1); 819 820 /* clear prior ldlat threshold */ 821 ctl &= ~IBS_OP_CTL_LDLATTRSHMASK; 822 ctl |= IBS_OP_CTL_LDLAT_TO_CTL(ldlat); 823 ctl |= IBS_OP_CTL_L3MISSONLY | IBS_OP_CTL_LATFLTEN; 824 } else if (KWMATCH(p, "opcount")) { 825 if ((ibs_features & CPUID_IBSID_OPCNT) == 0) 826 return (-1); 827 828 ctl |= IBS_OP_CTL_COUNTERCONTROL; 829 } else if (KWMATCH(p, "usr")) { 830 if ((ibs_features & CPUID_IBSID_ADDRBIT63FILTERING) == 0) 831 return (-1); 832 833 pmc_config->pm_caps |= PMC_CAP_USER; 834 } else if (KWMATCH(p, "os")) { 835 if ((ibs_features & CPUID_IBSID_ADDRBIT63FILTERING) == 0) 836 return (-1); 837 838 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 839 } else if (KWMATCH(p, "streamstore")) { 840 if ((ibs_features & CPUID_IBSID_STRMSTANDRMTSOCKET) == 0) 841 return (-1); 842 843 ctl2 |= IBS_OP_CTL2_STRMSTFILTER; 844 } else { 845 return (-1); 846 } 847 } 848 849 if (pmc_config->pm_count < IBS_OP_MIN_RATE || 850 pmc_config->pm_count > IBS_OP_MAX_RATE) 851 return (-1); 852 853 if (((ibs_features & CPUID_IBSID_OPCNTEXT) == 0) && 854 (pmc_config->pm_count > IBS_OP_MAX_RATE_PREEXT)) 855 return (-1); 856 857 ctl |= IBS_OP_INTERVAL_TO_CTL(pmc_config->pm_count); 858 } 859 860 pmc_config->pm_md.pm_ibs.ibs_ctl |= ctl; 861 pmc_config->pm_md.pm_ibs.ibs_ctl2 |= ctl2; 862 863 return (0); 864 } 865 866 static int 867 tsc_allocate_pmc(enum pmc_event pe, char *ctrspec, 868 struct pmc_op_pmcallocate *pmc_config) 869 { 870 if (pe != PMC_EV_TSC_TSC) 871 return (-1); 872 873 /* TSC events must be unqualified. */ 874 if (ctrspec && *ctrspec != '\0') 875 return (-1); 876 877 pmc_config->pm_md.pm_amd.pm_amd_config = 0; 878 pmc_config->pm_caps |= PMC_CAP_READ; 879 880 return (0); 881 } 882 #endif 883 884 static struct pmc_event_alias generic_aliases[] = { 885 EV_ALIAS("instructions", "SOFT-CLOCK.HARD"), 886 EV_ALIAS(NULL, NULL) 887 }; 888 889 static int 890 soft_allocate_pmc(enum pmc_event pe, char *ctrspec, 891 struct pmc_op_pmcallocate *pmc_config) 892 { 893 (void)ctrspec; 894 (void)pmc_config; 895 896 if ((int)pe < PMC_EV_SOFT_FIRST || (int)pe > PMC_EV_SOFT_LAST) 897 return (-1); 898 899 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 900 return (0); 901 } 902 903 #if defined(__arm__) 904 static struct pmc_event_alias cortex_a8_aliases[] = { 905 EV_ALIAS("dc-misses", "L1_DCACHE_REFILL"), 906 EV_ALIAS("ic-misses", "L1_ICACHE_REFILL"), 907 EV_ALIAS("instructions", "INSTR_EXECUTED"), 908 EV_ALIAS(NULL, NULL) 909 }; 910 911 static struct pmc_event_alias cortex_a9_aliases[] = { 912 EV_ALIAS("dc-misses", "L1_DCACHE_REFILL"), 913 EV_ALIAS("ic-misses", "L1_ICACHE_REFILL"), 914 EV_ALIAS("instructions", "INSTR_EXECUTED"), 915 EV_ALIAS(NULL, NULL) 916 }; 917 918 static int 919 armv7_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 920 struct pmc_op_pmcallocate *pmc_config __unused) 921 { 922 switch (pe) { 923 default: 924 break; 925 } 926 927 return (0); 928 } 929 #endif 930 931 #if defined(__aarch64__) 932 static struct pmc_event_alias cortex_a53_aliases[] = { 933 EV_ALIAS(NULL, NULL) 934 }; 935 static struct pmc_event_alias cortex_a57_aliases[] = { 936 EV_ALIAS(NULL, NULL) 937 }; 938 static struct pmc_event_alias cortex_a76_aliases[] = { 939 EV_ALIAS(NULL, NULL) 940 }; 941 942 static int 943 arm64_allocate_pmc(enum pmc_event pe, char *ctrspec, 944 struct pmc_op_pmcallocate *pmc_config) 945 { 946 char *p; 947 948 while ((p = strsep(&ctrspec, ",")) != NULL) { 949 if (KWMATCH(p, "os")) 950 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 951 else if (KWMATCH(p, "usr")) 952 pmc_config->pm_caps |= PMC_CAP_USER; 953 else 954 return (-1); 955 } 956 957 return (0); 958 } 959 960 static int 961 cmn600_pmu_allocate_pmc(enum pmc_event pe, char *ctrspec, 962 struct pmc_op_pmcallocate *pmc_config) 963 { 964 uint32_t nodeid, occupancy, xpport, xpchannel; 965 char *e, *p, *q; 966 unsigned int i; 967 char *xpport_names[] = { "East", "West", "North", "South", "devport0", 968 "devport1" }; 969 char *xpchannel_names[] = { "REQ", "RSP", "SNP", "DAT" }; 970 971 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 972 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 973 pmc_config->pm_md.pm_cmn600.pma_cmn600_config = 0; 974 /* 975 * CMN600 extra fields: 976 * * nodeid - node coordinates x[2-3],y[2-3],p[1],s[2] 977 * width of x and y fields depend on matrix size. 978 * * occupancy - numeric value to select desired filter. 979 * * xpport - East, West, North, South, devport0, devport1 (or 0, 1, ..., 5) 980 * * xpchannel - REQ, RSP, SNP, DAT (or 0, 1, 2, 3) 981 */ 982 983 while ((p = strsep(&ctrspec, ",")) != NULL) { 984 if (KWPREFIXMATCH(p, "nodeid=")) { 985 q = strchr(p, '='); 986 if (*++q == '\0') /* skip '=' */ 987 return (-1); 988 989 nodeid = strtol(q, &e, 0); 990 if (e == q || *e != '\0') 991 return (-1); 992 993 pmc_config->pm_md.pm_cmn600.pma_cmn600_nodeid |= nodeid; 994 995 } else if (KWPREFIXMATCH(p, "occupancy=")) { 996 q = strchr(p, '='); 997 if (*++q == '\0') /* skip '=' */ 998 return (-1); 999 1000 occupancy = strtol(q, &e, 0); 1001 if (e == q || *e != '\0') 1002 return (-1); 1003 1004 pmc_config->pm_md.pm_cmn600.pma_cmn600_occupancy = occupancy; 1005 } else if (KWPREFIXMATCH(p, "xpport=")) { 1006 q = strchr(p, '='); 1007 if (*++q == '\0') /* skip '=' */ 1008 return (-1); 1009 1010 xpport = strtol(q, &e, 0); 1011 if (e == q || *e != '\0') { 1012 for (i = 0; i < nitems(xpport_names); i++) { 1013 if (strcasecmp(xpport_names[i], q) == 0) { 1014 xpport = i; 1015 break; 1016 } 1017 } 1018 if (i == nitems(xpport_names)) 1019 return (-1); 1020 } 1021 1022 pmc_config->pm_md.pm_cmn600.pma_cmn600_config |= xpport << 2; 1023 } else if (KWPREFIXMATCH(p, "xpchannel=")) { 1024 q = strchr(p, '='); 1025 if (*++q == '\0') /* skip '=' */ 1026 return (-1); 1027 1028 xpchannel = strtol(q, &e, 0); 1029 if (e == q || *e != '\0') { 1030 for (i = 0; i < nitems(xpchannel_names); i++) { 1031 if (strcasecmp(xpchannel_names[i], q) == 0) { 1032 xpchannel = i; 1033 break; 1034 } 1035 } 1036 if (i == nitems(xpchannel_names)) 1037 return (-1); 1038 } 1039 1040 pmc_config->pm_md.pm_cmn600.pma_cmn600_config |= xpchannel << 5; 1041 } else 1042 return (-1); 1043 } 1044 1045 return (0); 1046 } 1047 1048 static int 1049 dmc620_pmu_allocate_pmc(enum pmc_event pe, char *ctrspec, 1050 struct pmc_op_pmcallocate *pmc_config) 1051 { 1052 char *e, *p, *q; 1053 uint64_t match, mask; 1054 uint32_t count; 1055 1056 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 1057 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 1058 pmc_config->pm_md.pm_dmc620.pm_dmc620_config = 0; 1059 1060 while ((p = strsep(&ctrspec, ",")) != NULL) { 1061 if (KWPREFIXMATCH(p, "count=")) { 1062 q = strchr(p, '='); 1063 if (*++q == '\0') /* skip '=' */ 1064 return (-1); 1065 1066 count = strtol(q, &e, 0); 1067 if (e == q || *e != '\0') 1068 return (-1); 1069 1070 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 1071 pmc_config->pm_md.pm_dmc620.pm_dmc620_config |= count; 1072 1073 } else if (KWMATCH(p, "inv")) { 1074 pmc_config->pm_caps |= PMC_CAP_INVERT; 1075 } else if (KWPREFIXMATCH(p, "match=")) { 1076 match = strtol(q, &e, 0); 1077 if (e == q || *e != '\0') 1078 return (-1); 1079 1080 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1081 pmc_config->pm_md.pm_dmc620.pm_dmc620_match = match; 1082 } else if (KWPREFIXMATCH(p, "mask=")) { 1083 q = strchr(p, '='); 1084 if (*++q == '\0') /* skip '=' */ 1085 return (-1); 1086 1087 mask = strtol(q, &e, 0); 1088 if (e == q || *e != '\0') 1089 return (-1); 1090 1091 pmc_config->pm_md.pm_dmc620.pm_dmc620_mask = mask; 1092 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1093 } else 1094 return (-1); 1095 } 1096 1097 return (0); 1098 } 1099 #endif 1100 1101 #if defined(__powerpc__) 1102 1103 static struct pmc_event_alias ppc7450_aliases[] = { 1104 EV_ALIAS("instructions", "INSTR_COMPLETED"), 1105 EV_ALIAS("branches", "BRANCHES_COMPLETED"), 1106 EV_ALIAS("branch-mispredicts", "MISPREDICTED_BRANCHES"), 1107 EV_ALIAS(NULL, NULL) 1108 }; 1109 1110 static struct pmc_event_alias ppc970_aliases[] = { 1111 EV_ALIAS("instructions", "INSTR_COMPLETED"), 1112 EV_ALIAS("cycles", "CYCLES"), 1113 EV_ALIAS(NULL, NULL) 1114 }; 1115 1116 static struct pmc_event_alias e500_aliases[] = { 1117 EV_ALIAS("instructions", "INSTR_COMPLETED"), 1118 EV_ALIAS("cycles", "CYCLES"), 1119 EV_ALIAS(NULL, NULL) 1120 }; 1121 1122 #define POWERPC_KW_OS "os" 1123 #define POWERPC_KW_USR "usr" 1124 #define POWERPC_KW_ANYTHREAD "anythread" 1125 1126 static int 1127 powerpc_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 1128 struct pmc_op_pmcallocate *pmc_config __unused) 1129 { 1130 char *p; 1131 1132 (void) pe; 1133 1134 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 1135 1136 while ((p = strsep(&ctrspec, ",")) != NULL) { 1137 if (KWMATCH(p, POWERPC_KW_OS)) 1138 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 1139 else if (KWMATCH(p, POWERPC_KW_USR)) 1140 pmc_config->pm_caps |= PMC_CAP_USER; 1141 else if (KWMATCH(p, POWERPC_KW_ANYTHREAD)) 1142 pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM); 1143 else 1144 return (-1); 1145 } 1146 1147 return (0); 1148 } 1149 1150 #endif /* __powerpc__ */ 1151 1152 1153 /* 1154 * Match an event name `name' with its canonical form. 1155 * 1156 * Matches are case insensitive and spaces, periods, underscores and 1157 * hyphen characters are considered to match each other. 1158 * 1159 * Returns 1 for a match, 0 otherwise. 1160 */ 1161 1162 static int 1163 pmc_match_event_name(const char *name, const char *canonicalname) 1164 { 1165 int cc, nc; 1166 const unsigned char *c, *n; 1167 1168 c = (const unsigned char *) canonicalname; 1169 n = (const unsigned char *) name; 1170 1171 for (; (nc = *n) && (cc = *c); n++, c++) { 1172 1173 if ((nc == ' ' || nc == '_' || nc == '-' || nc == '.') && 1174 (cc == ' ' || cc == '_' || cc == '-' || cc == '.')) 1175 continue; 1176 1177 if (toupper(nc) == toupper(cc)) 1178 continue; 1179 1180 1181 return (0); 1182 } 1183 1184 if (*n == '\0' && *c == '\0') 1185 return (1); 1186 1187 return (0); 1188 } 1189 1190 /* 1191 * Match an event name against all the event named supported by a 1192 * PMC class. 1193 * 1194 * Returns an event descriptor pointer on match or NULL otherwise. 1195 */ 1196 static const struct pmc_event_descr * 1197 pmc_match_event_class(const char *name, 1198 const struct pmc_class_descr *pcd) 1199 { 1200 size_t n; 1201 const struct pmc_event_descr *ev; 1202 1203 ev = pcd->pm_evc_event_table; 1204 for (n = 0; n < pcd->pm_evc_event_table_size; n++, ev++) 1205 if (pmc_match_event_name(name, ev->pm_ev_name)) 1206 return (ev); 1207 1208 return (NULL); 1209 } 1210 1211 /* 1212 * API entry points 1213 */ 1214 1215 int 1216 pmc_allocate(const char *ctrspec, enum pmc_mode mode, 1217 uint32_t flags, int cpu, pmc_id_t *pmcid, 1218 uint64_t count) 1219 { 1220 size_t n; 1221 int retval; 1222 char *r, *spec_copy; 1223 const char *ctrname; 1224 const struct pmc_event_descr *ev; 1225 const struct pmc_event_alias *alias; 1226 struct pmc_op_pmcallocate pmc_config; 1227 const struct pmc_class_descr *pcd; 1228 1229 spec_copy = NULL; 1230 retval = -1; 1231 1232 if (mode != PMC_MODE_SS && mode != PMC_MODE_TS && 1233 mode != PMC_MODE_SC && mode != PMC_MODE_TC) { 1234 errno = EINVAL; 1235 goto out; 1236 } 1237 bzero(&pmc_config, sizeof(pmc_config)); 1238 pmc_config.pm_cpu = cpu; 1239 pmc_config.pm_mode = mode; 1240 pmc_config.pm_flags = flags; 1241 pmc_config.pm_count = count; 1242 if (PMC_IS_SAMPLING_MODE(mode)) 1243 pmc_config.pm_caps |= PMC_CAP_INTERRUPT; 1244 1245 /* 1246 * Try to pull the raw event ID directly from the pmu-events table. If 1247 * this is unsupported on the platform, or the event is not found, 1248 * continue with searching the regular event tables. 1249 */ 1250 r = spec_copy = strdup(ctrspec); 1251 ctrname = strsep(&r, ","); 1252 if (pmc_pmu_enabled()) { 1253 errno = pmc_pmu_pmcallocate(ctrname, &pmc_config); 1254 if (errno == 0) 1255 goto found; 1256 if (errno == EOPNOTSUPP) 1257 goto out; 1258 } 1259 free(spec_copy); 1260 spec_copy = NULL; 1261 1262 /* replace an event alias with the canonical event specifier */ 1263 if (pmc_mdep_event_aliases) 1264 for (alias = pmc_mdep_event_aliases; alias->pm_alias; alias++) 1265 if (!strcasecmp(ctrspec, alias->pm_alias)) { 1266 spec_copy = strdup(alias->pm_spec); 1267 break; 1268 } 1269 1270 if (spec_copy == NULL) 1271 spec_copy = strdup(ctrspec); 1272 1273 r = spec_copy; 1274 ctrname = strsep(&r, ","); 1275 1276 /* 1277 * If a explicit class prefix was given by the user, restrict the 1278 * search for the event to the specified PMC class. 1279 */ 1280 ev = NULL; 1281 for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) { 1282 pcd = pmc_class_table[n]; 1283 if (pcd != NULL && strncasecmp(ctrname, pcd->pm_evc_name, 1284 pcd->pm_evc_name_size) == 0) { 1285 if ((ev = pmc_match_event_class(ctrname + 1286 pcd->pm_evc_name_size, pcd)) == NULL) { 1287 errno = EINVAL; 1288 goto out; 1289 } 1290 break; 1291 } 1292 } 1293 1294 /* 1295 * Otherwise, search for this event in all compatible PMC 1296 * classes. 1297 */ 1298 for (n = 0; ev == NULL && n < PMC_CLASS_TABLE_SIZE; n++) { 1299 pcd = pmc_class_table[n]; 1300 if (pcd != NULL) 1301 ev = pmc_match_event_class(ctrname, pcd); 1302 } 1303 1304 if (ev == NULL) { 1305 errno = EINVAL; 1306 goto out; 1307 } 1308 1309 pmc_config.pm_ev = ev->pm_ev_code; 1310 pmc_config.pm_class = pcd->pm_evc_class; 1311 1312 if (pcd->pm_evc_allocate_pmc(ev->pm_ev_code, r, &pmc_config) < 0) { 1313 errno = EINVAL; 1314 goto out; 1315 } 1316 1317 found: 1318 if (PMC_CALL(PMC_OP_PMCALLOCATE, &pmc_config) == 0) { 1319 *pmcid = pmc_config.pm_pmcid; 1320 retval = 0; 1321 } 1322 out: 1323 if (spec_copy) 1324 free(spec_copy); 1325 1326 return (retval); 1327 } 1328 1329 int 1330 pmc_attach(pmc_id_t pmc, pid_t pid) 1331 { 1332 struct pmc_op_pmcattach pmc_attach_args; 1333 1334 pmc_attach_args.pm_pmc = pmc; 1335 pmc_attach_args.pm_pid = pid; 1336 1337 return (PMC_CALL(PMC_OP_PMCATTACH, &pmc_attach_args)); 1338 } 1339 1340 int 1341 pmc_capabilities(pmc_id_t pmcid, uint32_t *caps) 1342 { 1343 struct pmc_op_caps args; 1344 int status; 1345 1346 args.pm_pmcid = pmcid; 1347 args.pm_caps = 0; 1348 1349 status = PMC_CALL(PMC_OP_GETCAPS, &args); 1350 *caps = args.pm_caps; 1351 1352 return (status); 1353 } 1354 1355 int 1356 pmc_configure_logfile(int fd) 1357 { 1358 struct pmc_op_configurelog cla; 1359 1360 cla.pm_flags = 0; 1361 cla.pm_logfd = fd; 1362 if (PMC_CALL(PMC_OP_CONFIGURELOG, &cla) < 0) 1363 return (-1); 1364 return (0); 1365 } 1366 1367 int 1368 pmc_cpuinfo(const struct pmc_cpuinfo **pci) 1369 { 1370 if (pmc_syscall == -1) { 1371 errno = ENXIO; 1372 return (-1); 1373 } 1374 1375 *pci = &cpu_info; 1376 return (0); 1377 } 1378 1379 int 1380 pmc_detach(pmc_id_t pmc, pid_t pid) 1381 { 1382 struct pmc_op_pmcattach pmc_detach_args; 1383 1384 pmc_detach_args.pm_pmc = pmc; 1385 pmc_detach_args.pm_pid = pid; 1386 return (PMC_CALL(PMC_OP_PMCDETACH, &pmc_detach_args)); 1387 } 1388 1389 int 1390 pmc_disable(int cpu, int pmc) 1391 { 1392 struct pmc_op_pmcadmin ssa; 1393 1394 ssa.pm_cpu = cpu; 1395 ssa.pm_pmc = pmc; 1396 ssa.pm_state = PMC_STATE_DISABLED; 1397 return (PMC_CALL(PMC_OP_PMCADMIN, &ssa)); 1398 } 1399 1400 int 1401 pmc_enable(int cpu, int pmc) 1402 { 1403 struct pmc_op_pmcadmin ssa; 1404 1405 ssa.pm_cpu = cpu; 1406 ssa.pm_pmc = pmc; 1407 ssa.pm_state = PMC_STATE_FREE; 1408 return (PMC_CALL(PMC_OP_PMCADMIN, &ssa)); 1409 } 1410 1411 /* 1412 * Return a list of events known to a given PMC class. 'cl' is the 1413 * PMC class identifier, 'eventnames' is the returned list of 'const 1414 * char *' pointers pointing to the names of the events. 'nevents' is 1415 * the number of event name pointers returned. 1416 * 1417 * The space for 'eventnames' is allocated using malloc(3). The caller 1418 * is responsible for freeing this space when done. 1419 */ 1420 int 1421 pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames, 1422 int *nevents) 1423 { 1424 int count; 1425 const char **names; 1426 const struct pmc_event_descr *ev; 1427 1428 switch (cl) 1429 { 1430 case PMC_CLASS_IAF: 1431 ev = iaf_event_table; 1432 count = PMC_EVENT_TABLE_SIZE(iaf); 1433 break; 1434 case PMC_CLASS_TSC: 1435 ev = tsc_event_table; 1436 count = PMC_EVENT_TABLE_SIZE(tsc); 1437 break; 1438 case PMC_CLASS_K8: 1439 ev = k8_event_table; 1440 count = PMC_EVENT_TABLE_SIZE(k8); 1441 break; 1442 case PMC_CLASS_IBS: 1443 ev = ibs_event_table; 1444 count = PMC_EVENT_TABLE_SIZE(ibs); 1445 break; 1446 case PMC_CLASS_ARMV7: 1447 switch (cpu_info.pm_cputype) { 1448 default: 1449 case PMC_CPU_ARMV7_CORTEX_A8: 1450 ev = cortex_a8_event_table; 1451 count = PMC_EVENT_TABLE_SIZE(cortex_a8); 1452 break; 1453 case PMC_CPU_ARMV7_CORTEX_A9: 1454 ev = cortex_a9_event_table; 1455 count = PMC_EVENT_TABLE_SIZE(cortex_a9); 1456 break; 1457 } 1458 break; 1459 case PMC_CLASS_ARMV8: 1460 switch (cpu_info.pm_cputype) { 1461 default: 1462 case PMC_CPU_ARMV8_CORTEX_A53: 1463 ev = cortex_a53_event_table; 1464 count = PMC_EVENT_TABLE_SIZE(cortex_a53); 1465 break; 1466 case PMC_CPU_ARMV8_CORTEX_A57: 1467 ev = cortex_a57_event_table; 1468 count = PMC_EVENT_TABLE_SIZE(cortex_a57); 1469 break; 1470 case PMC_CPU_ARMV8_CORTEX_A76: 1471 ev = cortex_a76_event_table; 1472 count = PMC_EVENT_TABLE_SIZE(cortex_a76); 1473 break; 1474 } 1475 break; 1476 case PMC_CLASS_CMN600_PMU: 1477 ev = cmn600_pmu_event_table; 1478 count = PMC_EVENT_TABLE_SIZE(cmn600_pmu); 1479 break; 1480 case PMC_CLASS_DMC620_PMU_CD2: 1481 ev = dmc620_pmu_cd2_event_table; 1482 count = PMC_EVENT_TABLE_SIZE(dmc620_pmu_cd2); 1483 break; 1484 case PMC_CLASS_DMC620_PMU_C: 1485 ev = dmc620_pmu_c_event_table; 1486 count = PMC_EVENT_TABLE_SIZE(dmc620_pmu_c); 1487 break; 1488 case PMC_CLASS_PPC7450: 1489 ev = ppc7450_event_table; 1490 count = PMC_EVENT_TABLE_SIZE(ppc7450); 1491 break; 1492 case PMC_CLASS_PPC970: 1493 ev = ppc970_event_table; 1494 count = PMC_EVENT_TABLE_SIZE(ppc970); 1495 break; 1496 case PMC_CLASS_E500: 1497 ev = e500_event_table; 1498 count = PMC_EVENT_TABLE_SIZE(e500); 1499 break; 1500 case PMC_CLASS_SOFT: 1501 ev = soft_event_table; 1502 count = soft_event_info.pm_nevent; 1503 break; 1504 default: 1505 errno = EINVAL; 1506 return (-1); 1507 } 1508 1509 if ((names = malloc(count * sizeof(const char *))) == NULL) 1510 return (-1); 1511 1512 *eventnames = names; 1513 *nevents = count; 1514 1515 for (;count--; ev++, names++) 1516 *names = ev->pm_ev_name; 1517 1518 return (0); 1519 } 1520 1521 int 1522 pmc_flush_logfile(void) 1523 { 1524 return (PMC_CALL(PMC_OP_FLUSHLOG, 0)); 1525 } 1526 1527 int 1528 pmc_close_logfile(void) 1529 { 1530 return (PMC_CALL(PMC_OP_CLOSELOG, 0)); 1531 } 1532 1533 int 1534 pmc_get_driver_stats(struct pmc_driverstats *ds) 1535 { 1536 struct pmc_op_getdriverstats gms; 1537 1538 if (PMC_CALL(PMC_OP_GETDRIVERSTATS, &gms) < 0) 1539 return (-1); 1540 1541 /* copy out fields in the current userland<->library interface */ 1542 ds->pm_intr_ignored = gms.pm_intr_ignored; 1543 ds->pm_intr_processed = gms.pm_intr_processed; 1544 ds->pm_intr_bufferfull = gms.pm_intr_bufferfull; 1545 ds->pm_syscalls = gms.pm_syscalls; 1546 ds->pm_syscall_errors = gms.pm_syscall_errors; 1547 ds->pm_buffer_requests = gms.pm_buffer_requests; 1548 ds->pm_buffer_requests_failed = gms.pm_buffer_requests_failed; 1549 ds->pm_log_sweeps = gms.pm_log_sweeps; 1550 return (0); 1551 } 1552 1553 int 1554 pmc_get_msr(pmc_id_t pmc, uint32_t *msr) 1555 { 1556 struct pmc_op_getmsr gm; 1557 1558 gm.pm_pmcid = pmc; 1559 if (PMC_CALL(PMC_OP_PMCGETMSR, &gm) < 0) 1560 return (-1); 1561 *msr = gm.pm_msr; 1562 return (0); 1563 } 1564 1565 int 1566 pmc_init(void) 1567 { 1568 int error, pmc_mod_id; 1569 unsigned int n; 1570 uint32_t abi_version; 1571 struct module_stat pmc_modstat; 1572 struct pmc_op_getcpuinfo op_cpu_info; 1573 1574 if (pmc_syscall != -1) /* already inited */ 1575 return (0); 1576 1577 /* retrieve the system call number from the KLD */ 1578 if ((pmc_mod_id = modfind(PMC_MODULE_NAME)) < 0) 1579 return (-1); 1580 1581 pmc_modstat.version = sizeof(struct module_stat); 1582 if ((error = modstat(pmc_mod_id, &pmc_modstat)) < 0) 1583 return (-1); 1584 1585 pmc_syscall = pmc_modstat.data.intval; 1586 1587 /* check the kernel module's ABI against our compiled-in version */ 1588 abi_version = PMC_VERSION; 1589 if (PMC_CALL(PMC_OP_GETMODULEVERSION, &abi_version) < 0) 1590 return (pmc_syscall = -1); 1591 1592 /* ignore patch & minor numbers for the comparison */ 1593 if ((abi_version & 0xFF000000) != (PMC_VERSION & 0xFF000000)) { 1594 errno = EPROGMISMATCH; 1595 return (pmc_syscall = -1); 1596 } 1597 1598 bzero(&op_cpu_info, sizeof(op_cpu_info)); 1599 if (PMC_CALL(PMC_OP_GETCPUINFO, &op_cpu_info) < 0) 1600 return (pmc_syscall = -1); 1601 1602 cpu_info.pm_cputype = op_cpu_info.pm_cputype; 1603 cpu_info.pm_ncpu = op_cpu_info.pm_ncpu; 1604 cpu_info.pm_npmc = op_cpu_info.pm_npmc; 1605 cpu_info.pm_nclass = op_cpu_info.pm_nclass; 1606 for (n = 0; n < op_cpu_info.pm_nclass; n++) 1607 memcpy(&cpu_info.pm_classes[n], &op_cpu_info.pm_classes[n], 1608 sizeof(cpu_info.pm_classes[n])); 1609 1610 pmc_class_table = calloc(PMC_CLASS_TABLE_SIZE, 1611 sizeof(struct pmc_class_descr *)); 1612 1613 if (pmc_class_table == NULL) 1614 return (-1); 1615 1616 /* 1617 * Get soft events list. 1618 */ 1619 soft_event_info.pm_class = PMC_CLASS_SOFT; 1620 if (PMC_CALL(PMC_OP_GETDYNEVENTINFO, &soft_event_info) < 0) 1621 return (pmc_syscall = -1); 1622 1623 /* Map soft events to static list. */ 1624 for (n = 0; n < soft_event_info.pm_nevent; n++) { 1625 soft_event_table[n].pm_ev_name = 1626 soft_event_info.pm_events[n].pm_ev_name; 1627 soft_event_table[n].pm_ev_code = 1628 soft_event_info.pm_events[n].pm_ev_code; 1629 } 1630 soft_class_table_descr.pm_evc_event_table_size = \ 1631 soft_event_info.pm_nevent; 1632 soft_class_table_descr.pm_evc_event_table = \ 1633 soft_event_table; 1634 1635 /* 1636 * Fill in the class table. 1637 */ 1638 n = 0; 1639 for (unsigned i = 0; i < PMC_CLASS_TABLE_SIZE; i++) { 1640 switch (cpu_info.pm_classes[i].pm_class) { 1641 #if defined(__amd64__) || defined(__i386__) 1642 case PMC_CLASS_TSC: 1643 pmc_class_table[n++] = &tsc_class_table_descr; 1644 break; 1645 1646 case PMC_CLASS_K8: 1647 pmc_class_table[n++] = &k8_class_table_descr; 1648 break; 1649 1650 case PMC_CLASS_IBS: 1651 pmc_class_table[n++] = &ibs_class_table_descr; 1652 break; 1653 #endif 1654 1655 case PMC_CLASS_SOFT: 1656 pmc_class_table[n++] = &soft_class_table_descr; 1657 break; 1658 1659 #if defined(__arm__) 1660 case PMC_CLASS_ARMV7: 1661 switch (cpu_info.pm_cputype) { 1662 case PMC_CPU_ARMV7_CORTEX_A8: 1663 pmc_class_table[n++] = 1664 &cortex_a8_class_table_descr; 1665 break; 1666 case PMC_CPU_ARMV7_CORTEX_A9: 1667 pmc_class_table[n++] = 1668 &cortex_a9_class_table_descr; 1669 break; 1670 default: 1671 errno = ENXIO; 1672 return (pmc_syscall = -1); 1673 } 1674 break; 1675 #endif 1676 1677 #if defined(__aarch64__) 1678 case PMC_CLASS_ARMV8: 1679 switch (cpu_info.pm_cputype) { 1680 case PMC_CPU_ARMV8_CORTEX_A53: 1681 pmc_class_table[n++] = 1682 &cortex_a53_class_table_descr; 1683 break; 1684 case PMC_CPU_ARMV8_CORTEX_A57: 1685 pmc_class_table[n++] = 1686 &cortex_a57_class_table_descr; 1687 break; 1688 case PMC_CPU_ARMV8_CORTEX_A76: 1689 pmc_class_table[n++] = 1690 &cortex_a76_class_table_descr; 1691 break; 1692 default: 1693 errno = ENXIO; 1694 return (pmc_syscall = -1); 1695 } 1696 break; 1697 1698 case PMC_CLASS_DMC620_PMU_CD2: 1699 pmc_class_table[n++] = 1700 &dmc620_pmu_cd2_class_table_descr; 1701 break; 1702 1703 case PMC_CLASS_DMC620_PMU_C: 1704 pmc_class_table[n++] = &dmc620_pmu_c_class_table_descr; 1705 break; 1706 1707 case PMC_CLASS_CMN600_PMU: 1708 pmc_class_table[n++] = &cmn600_pmu_class_table_descr; 1709 break; 1710 #endif 1711 1712 #if defined(__powerpc__) 1713 case PMC_CLASS_PPC7450: 1714 pmc_class_table[n++] = &ppc7450_class_table_descr; 1715 break; 1716 1717 case PMC_CLASS_PPC970: 1718 pmc_class_table[n++] = &ppc970_class_table_descr; 1719 break; 1720 1721 case PMC_CLASS_E500: 1722 pmc_class_table[n++] = &e500_class_table_descr; 1723 break; 1724 #endif 1725 1726 default: 1727 #if defined(DEBUG) 1728 printf("pm_class: 0x%x\n", 1729 cpu_info.pm_classes[i].pm_class); 1730 #endif 1731 break; 1732 } 1733 } 1734 1735 #define PMC_MDEP_INIT(C) pmc_mdep_event_aliases = C##_aliases 1736 1737 /* Configure the event name parser. */ 1738 switch (cpu_info.pm_cputype) { 1739 #if defined(__amd64__) || defined(__i386__) 1740 case PMC_CPU_AMD_K8: 1741 PMC_MDEP_INIT(k8); 1742 break; 1743 #endif 1744 case PMC_CPU_GENERIC: 1745 PMC_MDEP_INIT(generic); 1746 break; 1747 #if defined(__arm__) 1748 case PMC_CPU_ARMV7_CORTEX_A8: 1749 PMC_MDEP_INIT(cortex_a8); 1750 break; 1751 case PMC_CPU_ARMV7_CORTEX_A9: 1752 PMC_MDEP_INIT(cortex_a9); 1753 break; 1754 #endif 1755 #if defined(__aarch64__) 1756 case PMC_CPU_ARMV8_CORTEX_A53: 1757 PMC_MDEP_INIT(cortex_a53); 1758 break; 1759 case PMC_CPU_ARMV8_CORTEX_A57: 1760 PMC_MDEP_INIT(cortex_a57); 1761 break; 1762 case PMC_CPU_ARMV8_CORTEX_A76: 1763 PMC_MDEP_INIT(cortex_a76); 1764 break; 1765 #endif 1766 #if defined(__powerpc__) 1767 case PMC_CPU_PPC_7450: 1768 PMC_MDEP_INIT(ppc7450); 1769 break; 1770 case PMC_CPU_PPC_970: 1771 PMC_MDEP_INIT(ppc970); 1772 break; 1773 case PMC_CPU_PPC_E500: 1774 PMC_MDEP_INIT(e500); 1775 break; 1776 #endif 1777 default: 1778 /* 1779 * Some kind of CPU this version of the library knows nothing 1780 * about. This shouldn't happen since the abi version check 1781 * should have caught this. 1782 */ 1783 #if defined(__amd64__) || defined(__i386__) || defined(__powerpc64__) 1784 break; 1785 #endif 1786 errno = ENXIO; 1787 return (pmc_syscall = -1); 1788 } 1789 1790 return (0); 1791 } 1792 1793 const char * 1794 pmc_name_of_capability(enum pmc_caps cap) 1795 { 1796 int i; 1797 1798 /* 1799 * 'cap' should have a single bit set and should be in 1800 * range. 1801 */ 1802 if ((cap & (cap - 1)) || cap < PMC_CAP_FIRST || 1803 cap > PMC_CAP_LAST) { 1804 errno = EINVAL; 1805 return (NULL); 1806 } 1807 1808 i = ffs(cap); 1809 return (pmc_capability_names[i - 1]); 1810 } 1811 1812 const char * 1813 pmc_name_of_class(enum pmc_class pc) 1814 { 1815 size_t n; 1816 1817 for (n = 0; n < PMC_TABLE_SIZE(pmc_class_names); n++) 1818 if (pc == pmc_class_names[n].pm_class) 1819 return (pmc_class_names[n].pm_name); 1820 1821 errno = EINVAL; 1822 return (NULL); 1823 } 1824 1825 const char * 1826 pmc_name_of_cputype(enum pmc_cputype cp) 1827 { 1828 size_t n; 1829 1830 for (n = 0; n < PMC_TABLE_SIZE(pmc_cputype_names); n++) 1831 if (cp == pmc_cputype_names[n].pm_cputype) 1832 return (pmc_cputype_names[n].pm_name); 1833 1834 errno = EINVAL; 1835 return (NULL); 1836 } 1837 1838 const char * 1839 pmc_name_of_disposition(enum pmc_disp pd) 1840 { 1841 if ((int) pd >= PMC_DISP_FIRST && 1842 pd <= PMC_DISP_LAST) 1843 return (pmc_disposition_names[pd]); 1844 1845 errno = EINVAL; 1846 return (NULL); 1847 } 1848 1849 const char * 1850 _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu) 1851 { 1852 const struct pmc_event_descr *ev, *evfence; 1853 1854 ev = evfence = NULL; 1855 if (pe >= PMC_EV_K8_FIRST && pe <= PMC_EV_K8_LAST) { 1856 ev = k8_event_table; 1857 evfence = k8_event_table + PMC_EVENT_TABLE_SIZE(k8); 1858 } else if (pe >= PMC_EV_IBS_FIRST && pe <= PMC_EV_IBS_LAST) { 1859 ev = ibs_event_table; 1860 evfence = ibs_event_table + PMC_EVENT_TABLE_SIZE(ibs); 1861 } else if (pe >= PMC_EV_ARMV7_FIRST && pe <= PMC_EV_ARMV7_LAST) { 1862 switch (cpu) { 1863 case PMC_CPU_ARMV7_CORTEX_A8: 1864 ev = cortex_a8_event_table; 1865 evfence = cortex_a8_event_table + PMC_EVENT_TABLE_SIZE(cortex_a8); 1866 break; 1867 case PMC_CPU_ARMV7_CORTEX_A9: 1868 ev = cortex_a9_event_table; 1869 evfence = cortex_a9_event_table + PMC_EVENT_TABLE_SIZE(cortex_a9); 1870 break; 1871 default: /* Unknown CPU type. */ 1872 break; 1873 } 1874 } else if (pe >= PMC_EV_ARMV8_FIRST && pe <= PMC_EV_ARMV8_LAST) { 1875 switch (cpu) { 1876 case PMC_CPU_ARMV8_CORTEX_A53: 1877 ev = cortex_a53_event_table; 1878 evfence = cortex_a53_event_table + PMC_EVENT_TABLE_SIZE(cortex_a53); 1879 break; 1880 case PMC_CPU_ARMV8_CORTEX_A57: 1881 ev = cortex_a57_event_table; 1882 evfence = cortex_a57_event_table + PMC_EVENT_TABLE_SIZE(cortex_a57); 1883 break; 1884 case PMC_CPU_ARMV8_CORTEX_A76: 1885 ev = cortex_a76_event_table; 1886 evfence = cortex_a76_event_table + PMC_EVENT_TABLE_SIZE(cortex_a76); 1887 break; 1888 default: /* Unknown CPU type. */ 1889 break; 1890 } 1891 } else if (pe >= PMC_EV_CMN600_PMU_FIRST && 1892 pe <= PMC_EV_CMN600_PMU_LAST) { 1893 ev = cmn600_pmu_event_table; 1894 evfence = cmn600_pmu_event_table + 1895 PMC_EVENT_TABLE_SIZE(cmn600_pmu); 1896 } else if (pe >= PMC_EV_DMC620_PMU_CD2_FIRST && 1897 pe <= PMC_EV_DMC620_PMU_CD2_LAST) { 1898 ev = dmc620_pmu_cd2_event_table; 1899 evfence = dmc620_pmu_cd2_event_table + 1900 PMC_EVENT_TABLE_SIZE(dmc620_pmu_cd2); 1901 } else if (pe >= PMC_EV_DMC620_PMU_C_FIRST && 1902 pe <= PMC_EV_DMC620_PMU_C_LAST) { 1903 ev = dmc620_pmu_c_event_table; 1904 evfence = dmc620_pmu_c_event_table + 1905 PMC_EVENT_TABLE_SIZE(dmc620_pmu_c); 1906 } else if (pe >= PMC_EV_PPC7450_FIRST && pe <= PMC_EV_PPC7450_LAST) { 1907 ev = ppc7450_event_table; 1908 evfence = ppc7450_event_table + PMC_EVENT_TABLE_SIZE(ppc7450); 1909 } else if (pe >= PMC_EV_PPC970_FIRST && pe <= PMC_EV_PPC970_LAST) { 1910 ev = ppc970_event_table; 1911 evfence = ppc970_event_table + PMC_EVENT_TABLE_SIZE(ppc970); 1912 } else if (pe >= PMC_EV_E500_FIRST && pe <= PMC_EV_E500_LAST) { 1913 ev = e500_event_table; 1914 evfence = e500_event_table + PMC_EVENT_TABLE_SIZE(e500); 1915 } else if (pe == PMC_EV_TSC_TSC) { 1916 ev = tsc_event_table; 1917 evfence = tsc_event_table + PMC_EVENT_TABLE_SIZE(tsc); 1918 } else if ((int)pe >= PMC_EV_SOFT_FIRST && (int)pe <= PMC_EV_SOFT_LAST) { 1919 ev = soft_event_table; 1920 evfence = soft_event_table + soft_event_info.pm_nevent; 1921 } 1922 1923 for (; ev != evfence; ev++) 1924 if (pe == ev->pm_ev_code) 1925 return (ev->pm_ev_name); 1926 1927 return (NULL); 1928 } 1929 1930 const char * 1931 pmc_name_of_event(enum pmc_event pe) 1932 { 1933 const char *n; 1934 1935 if ((n = _pmc_name_of_event(pe, cpu_info.pm_cputype)) != NULL) 1936 return (n); 1937 1938 errno = EINVAL; 1939 return (NULL); 1940 } 1941 1942 const char * 1943 pmc_name_of_mode(enum pmc_mode pm) 1944 { 1945 if ((int) pm >= PMC_MODE_FIRST && 1946 pm <= PMC_MODE_LAST) 1947 return (pmc_mode_names[pm]); 1948 1949 errno = EINVAL; 1950 return (NULL); 1951 } 1952 1953 const char * 1954 pmc_name_of_state(enum pmc_state ps) 1955 { 1956 if ((int) ps >= PMC_STATE_FIRST && 1957 ps <= PMC_STATE_LAST) 1958 return (pmc_state_names[ps]); 1959 1960 errno = EINVAL; 1961 return (NULL); 1962 } 1963 1964 int 1965 pmc_ncpu(void) 1966 { 1967 if (pmc_syscall == -1) { 1968 errno = ENXIO; 1969 return (-1); 1970 } 1971 1972 return (cpu_info.pm_ncpu); 1973 } 1974 1975 int 1976 pmc_npmc(int cpu) 1977 { 1978 if (pmc_syscall == -1) { 1979 errno = ENXIO; 1980 return (-1); 1981 } 1982 1983 if (cpu < 0 || cpu >= (int) cpu_info.pm_ncpu) { 1984 errno = EINVAL; 1985 return (-1); 1986 } 1987 1988 return (cpu_info.pm_npmc); 1989 } 1990 1991 int 1992 pmc_pmcinfo(int cpu, struct pmc_pmcinfo **ppmci) 1993 { 1994 int nbytes, npmc; 1995 struct pmc_op_getpmcinfo *pmci; 1996 1997 if ((npmc = pmc_npmc(cpu)) < 0) 1998 return (-1); 1999 2000 nbytes = sizeof(struct pmc_op_getpmcinfo) + 2001 npmc * sizeof(struct pmc_info); 2002 2003 if ((pmci = calloc(1, nbytes)) == NULL) 2004 return (-1); 2005 2006 pmci->pm_cpu = cpu; 2007 2008 if (PMC_CALL(PMC_OP_GETPMCINFO, pmci) < 0) { 2009 free(pmci); 2010 return (-1); 2011 } 2012 2013 /* kernel<->library, library<->userland interfaces are identical */ 2014 *ppmci = (struct pmc_pmcinfo *) pmci; 2015 return (0); 2016 } 2017 2018 int 2019 pmc_read(pmc_id_t pmc, pmc_value_t *value) 2020 { 2021 struct pmc_op_pmcrw pmc_read_op; 2022 2023 pmc_read_op.pm_pmcid = pmc; 2024 pmc_read_op.pm_flags = PMC_F_OLDVALUE; 2025 pmc_read_op.pm_value = -1; 2026 2027 if (PMC_CALL(PMC_OP_PMCRW, &pmc_read_op) < 0) 2028 return (-1); 2029 2030 *value = pmc_read_op.pm_value; 2031 return (0); 2032 } 2033 2034 int 2035 pmc_release(pmc_id_t pmc) 2036 { 2037 struct pmc_op_simple pmc_release_args; 2038 2039 pmc_release_args.pm_pmcid = pmc; 2040 return (PMC_CALL(PMC_OP_PMCRELEASE, &pmc_release_args)); 2041 } 2042 2043 int 2044 pmc_rw(pmc_id_t pmc, pmc_value_t newvalue, pmc_value_t *oldvaluep) 2045 { 2046 struct pmc_op_pmcrw pmc_rw_op; 2047 2048 pmc_rw_op.pm_pmcid = pmc; 2049 pmc_rw_op.pm_flags = PMC_F_NEWVALUE | PMC_F_OLDVALUE; 2050 pmc_rw_op.pm_value = newvalue; 2051 2052 if (PMC_CALL(PMC_OP_PMCRW, &pmc_rw_op) < 0) 2053 return (-1); 2054 2055 *oldvaluep = pmc_rw_op.pm_value; 2056 return (0); 2057 } 2058 2059 int 2060 pmc_set(pmc_id_t pmc, pmc_value_t value) 2061 { 2062 struct pmc_op_pmcsetcount sc; 2063 2064 sc.pm_pmcid = pmc; 2065 sc.pm_count = value; 2066 2067 if (PMC_CALL(PMC_OP_PMCSETCOUNT, &sc) < 0) 2068 return (-1); 2069 return (0); 2070 } 2071 2072 int 2073 pmc_start(pmc_id_t pmc) 2074 { 2075 struct pmc_op_simple pmc_start_args; 2076 2077 pmc_start_args.pm_pmcid = pmc; 2078 return (PMC_CALL(PMC_OP_PMCSTART, &pmc_start_args)); 2079 } 2080 2081 int 2082 pmc_stop(pmc_id_t pmc) 2083 { 2084 struct pmc_op_simple pmc_stop_args; 2085 2086 pmc_stop_args.pm_pmcid = pmc; 2087 return (PMC_CALL(PMC_OP_PMCSTOP, &pmc_stop_args)); 2088 } 2089 2090 int 2091 pmc_width(pmc_id_t pmcid, uint32_t *width) 2092 { 2093 unsigned int i; 2094 enum pmc_class cl; 2095 2096 cl = PMC_ID_TO_CLASS(pmcid); 2097 for (i = 0; i < cpu_info.pm_nclass; i++) 2098 if (cpu_info.pm_classes[i].pm_class == cl) { 2099 *width = cpu_info.pm_classes[i].pm_width; 2100 return (0); 2101 } 2102 errno = EINVAL; 2103 return (-1); 2104 } 2105 2106 int 2107 pmc_write(pmc_id_t pmc, pmc_value_t value) 2108 { 2109 struct pmc_op_pmcrw pmc_write_op; 2110 2111 pmc_write_op.pm_pmcid = pmc; 2112 pmc_write_op.pm_flags = PMC_F_NEWVALUE; 2113 pmc_write_op.pm_value = value; 2114 return (PMC_CALL(PMC_OP_PMCRW, &pmc_write_op)); 2115 } 2116 2117 int 2118 pmc_writelog(uint32_t userdata) 2119 { 2120 struct pmc_op_writelog wl; 2121 2122 wl.pm_userdata = userdata; 2123 return (PMC_CALL(PMC_OP_WRITELOG, &wl)); 2124 } 2125