1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2004 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _MDB_KREG_H 28 #define _MDB_KREG_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifndef _ASM 33 #include <sys/types.h> 34 #endif 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 #ifdef __sparcv9cpu 41 #define KREG_NGREG 52 42 #ifndef _ASM 43 typedef uint64_t kreg_t; 44 #endif /* _ASM */ 45 #else /* __sparcv9cpu */ 46 #define KREG_NGREG 38 47 #ifndef _ASM 48 typedef uint32_t kreg_t; 49 #endif /* _ASM */ 50 #endif /* __sparcv9cpu */ 51 52 /* 53 * mdb_tgt_gregset_t register indicies 54 */ 55 56 #define KREG_G0 0 57 #define KREG_G1 1 58 #define KREG_G2 2 59 #define KREG_G3 3 60 #define KREG_G4 4 61 #define KREG_G5 5 62 #define KREG_G6 6 63 #define KREG_G7 7 64 #define KREG_O0 8 65 #define KREG_O1 9 66 #define KREG_O2 10 67 #define KREG_O3 11 68 #define KREG_O4 12 69 #define KREG_O5 13 70 #define KREG_O6 14 71 #define KREG_O7 15 72 #define KREG_L0 16 73 #define KREG_L1 17 74 #define KREG_L2 18 75 #define KREG_L3 19 76 #define KREG_L4 20 77 #define KREG_L5 21 78 #define KREG_L6 22 79 #define KREG_L7 23 80 #define KREG_I0 24 81 #define KREG_I1 25 82 #define KREG_I2 26 83 #define KREG_I3 27 84 #define KREG_I4 28 85 #define KREG_I5 29 86 #define KREG_I6 30 87 #define KREG_I7 31 88 89 #define KREG_SP KREG_O6 90 #define KREG_FP KREG_I6 91 92 #ifdef __sparcv9cpu 93 #define KREG_CCR 32 94 #else 95 #define KREG_PSR 32 96 #endif 97 98 #define KREG_PC 33 99 #define KREG_NPC 34 100 #define KREG_Y 35 101 102 #ifdef __sparcv9cpu 103 104 #define KREG_ASI 36 105 #define KREG_FPRS 37 106 #define KREG_TICK 38 107 #define KREG_STICK 39 108 #define KREG_PSTATE 40 109 #define KREG_TL 41 110 #define KREG_PIL 42 111 #define KREG_TBA 43 112 #define KREG_VER 44 113 #define KREG_CWP 45 114 #define KREG_CANSAVE 46 115 #define KREG_CANRESTORE 47 116 #define KREG_OTHERWIN 48 117 #define KREG_WSTATE 49 118 #define KREG_CLEANWIN 50 119 #define KREG_TT 51 120 121 #else /* __sparcv9cpu */ 122 123 #define KREG_WIM 36 124 #define KREG_TBR 37 125 126 #endif /* __sparcv9cpu */ 127 128 #ifdef __sparcv9cpu 129 130 #define KREG_CCR_XCC_N_MASK 0x80 131 #define KREG_CCR_XCC_Z_MASK 0x40 132 #define KREG_CCR_XCC_V_MASK 0x20 133 #define KREG_CCR_XCC_C_MASK 0x10 134 135 #define KREG_CCR_ICC_N_MASK 0x08 136 #define KREG_CCR_ICC_Z_MASK 0x04 137 #define KREG_CCR_ICC_V_MASK 0x02 138 #define KREG_CCR_ICC_C_MASK 0x01 139 140 #define KREG_FPRS_FEF_MASK 0x4 141 #define KREG_FPRS_FEF_SHIFT 2 142 143 #define KREG_FPRS_DU_MASK 0x2 144 #define KREG_FPRS_DU_SHIFT 1 145 146 #define KREG_FPRS_DL_MASK 0x1 147 #define KREG_FPRS_DL_SHIFT 0 148 149 #define KREG_TICK_NPT_MASK 0x8000000000000000ULL 150 #define KREG_TICK_NPT_SHIFT 63 151 152 #define KREG_TICK_CNT_MASK 0x7fffffffffffffffULL 153 #define KREG_TICK_CNT_SHIFT 0 154 155 #define KREG_PSTATE_CLE_MASK 0x200 156 #define KREG_PSTATE_CLE_SHIFT 9 157 158 #define KREG_PSTATE_TLE_MASK 0x100 159 #define KREG_PSTATE_TLE_SHIFT 8 160 161 #define KREG_PSTATE_MM_MASK 0x0c0 162 #define KREG_PSTATE_MM_SHIFT 6 163 164 #define KREG_PSTATE_MM_TSO(x) (((x) & KREG_PSTATE_MM_MASK) == 0x000) 165 #define KREG_PSTATE_MM_PSO(x) (((x) & KREG_PSTATE_MM_MASK) == 0x040) 166 #define KREG_PSTATE_MM_RMO(x) (((x) & KREG_PSTATE_MM_MASK) == 0x080) 167 #define KREG_PSTATE_MM_UNDEF(x) (((x) & KREG_PSTATE_MM_MASK) == 0x0c0) 168 169 #define KREG_PSTATE_RED_MASK 0x020 170 #define KREG_PSTATE_RED_SHIFT 5 171 172 #define KREG_PSTATE_PEF_MASK 0x010 173 #define KREG_PSTATE_PEF_SHIFT 4 174 175 #define KREG_PSTATE_AM_MASK 0x008 176 #define KREG_PSTATE_AM_SHIFT 3 177 178 #define KREG_PSTATE_PRIV_MASK 0x004 179 #define KREG_PSTATE_PRIV_SHIFT 2 180 181 #define KREG_PSTATE_IE_MASK 0x002 182 #define KREG_PSTATE_IE_SHIFT 1 183 184 #define KREG_PSTATE_AG_MASK 0x001 185 #define KREG_PSTATE_AG_SHIFT 0 186 187 #define KREG_PSTATE_MASK 0xfff 188 189 #define KREG_TSTATE_CCR(x) (((x) >> 32) & 0xff) 190 #define KREG_TSTATE_ASI(x) (((x) >> 24) & 0xff) 191 #define KREG_TSTATE_PSTATE(x) (((x) >> 8) & 0xfff) 192 #define KREG_TSTATE_CWP(x) ((x) & 0x1f) 193 194 #define KREG_TSTATE_PSTATE_MASK 0x000000000000fff0ULL 195 #define KREG_TSTATE_PSTATE_SHIFT 8 196 197 #define KREG_TBA_TBA_MASK 0xffffffffffff8000ULL 198 #define KREG_TBA_TBA_SHIFT 0 199 200 #define KREG_TBA_TLG0_MASK 0x4000 201 #define KREG_TBA_TLG0_SHIFT 14 202 203 #define KREG_TBA_TT_MASK 0x3fd0 204 #define KREG_TBA_TT_SHIFT 5 205 206 #define KREG_VER_MANUF_MASK 0xffff000000000000ULL 207 #define KREG_VER_MANUF_SHIFT 48 208 209 #define KREG_VER_IMPL_MASK 0x0000ffff00000000ULL 210 #define KREG_VER_IMPL_SHIFT 32 211 212 #define KREG_VER_MASK_MASK 0xff000000 213 #define KREG_VER_MASK_SHIFT 24 214 215 #define KREG_VER_MAXTL_MASK 0x0000ff00 216 #define KREG_VER_MAXTL_SHIFT 8 217 218 #define KREG_VER_MAXWIN_MASK 0x0000000f 219 #define KREG_VER_MAXWIN_SHIFT 0 220 221 #else /* __sparcv9cpu */ 222 223 #define KREG_PSR_IMPL_MASK 0xf0000000 224 #define KREG_PSR_IMPL_SHIFT 28 225 226 #define KREG_PSR_VER_MASK 0x0f000000 227 #define KREG_PSR_VER_SHIFT 24 228 229 #define KREG_PSR_ICC_MASK 0x00f00000 230 #define KREG_PSR_ICC_N_MASK 0x00800000 231 #define KREG_PSR_ICC_Z_MASK 0x00400000 232 #define KREG_PSR_ICC_V_MASK 0x00200000 233 #define KREG_PSR_ICC_C_MASK 0x00100000 234 #define KREG_PSR_ICC_SHIFT 20 235 236 #define KREG_PSR_EC_MASK 0x00002000 237 #define KREG_PSR_EC_SHIFT 13 238 239 #define KREG_PSR_EF_MASK 0x00001000 240 #define KREG_PSR_EF_SHIFT 12 241 242 #define KREG_PSR_PIL_MASK 0x00000f00 243 #define KREG_PSR_PIL_SHIFT 8 244 245 #define KREG_PSR_S_MASK 0x00000080 246 #define KREG_PSR_S_SHIFT 7 247 248 #define KREG_PSR_PS_MASK 0x00000040 249 #define KREG_PSR_PS_SHIFT 6 250 251 #define KREG_PSR_ET_MASK 0x00000020 252 #define KREG_PSR_ET_SHIFT 5 253 254 #define KREG_PSR_CWP_MASK 0x0000001f 255 #define KREG_PSR_CWP_SHIFT 0 256 257 #define KREG_TBR_TBA_MASK 0xfffff000 258 #define KREG_TBR_TBA_SHIFT 0 259 260 #define KREG_TBR_TT_MASK 0x00000ff0 261 #define KREG_TBR_TT_SHIFT 4 262 263 #endif /* __sparcv9cpu */ 264 265 #ifdef __cplusplus 266 } 267 #endif 268 269 #endif /* _MDB_KREG_H */ 270