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Searched defs:ItinData (Results 1 – 10 of 10) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.h34 PPCDispatchGroupSBHazardRecognizer(const InstrItineraryData *ItinData, in PPCDispatchGroupSBHazardRecognizer()
H A DPPCInstrInfo.h342 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData, in getOperandLatency()
H A DPPCInstrInfo.cpp138 unsigned PPCInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency()
169 const InstrItineraryData *ItinData, const MachineInstr &DefMI, in getOperandLatency()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DScoreboardHazardRecognizer.h95 const InstrItineraryData *ItinData; variable
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetInstrInfo.cpp1442 TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, in getOperandLatency()
1458 unsigned TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency()
1473 unsigned TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, in getNumMicroOps()
1504 unsigned TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency()
1518 const InstrItineraryData *ItinData = SchedModel.getInstrItineraries(); in hasLowDefLatency() local
1644 const InstrItineraryData *ItinData, const MachineInstr &DefMI, in getOperandLatency()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp3461 static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData, in getNumMicroOpsSwiftLdSt()
3763 unsigned ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, in getNumMicroOps()
3877 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData, in getVLDMDefCycle()
3917 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData, in getLDMDefCycle()
3951 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData, in getVSTMUseCycle()
3990 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData, in getSTMUseCycle()
4018 const InstrItineraryData *ItinData, const MCInstrDesc &DefMCID, in getOperandLatency()
4364 const InstrItineraryData *ItinData, const MachineInstr &DefMI, in getOperandLatency()
4398 const InstrItineraryData *ItinData, const MachineInstr &DefMI, in getOperandLatencyImpl()
4458 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, in getOperandLatency()
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/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp354 Record *ItinData, in FormItineraryStageString()
400 Record *ItinData, std::string &ItinString, unsigned &NOperandCycles) { in FormItineraryOperandCycleString()
416 Record *ItinData, in FormItineraryBypassString()
516 Record *ItinData = ProcModel.ItinDefList[SchedClassIdx]; in EmitStageAndOperandCycleData() local
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp1970 unsigned HexagonInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency()
4308 const InstrItineraryData *ItinData, const MachineInstr &MI) const { in getInstrTimingClassLatency() argument
4328 const InstrItineraryData *ItinData, const MachineInstr &DefMI, in getOperandLatency()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600InstrInfo.cpp981 unsigned int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency()
H A DSIInstrInfo.cpp9534 unsigned SIInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency()