| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 158 bool IsStore = false; in emitInstruction() local
211 bool *IsStore) { in isBasePlusOffsetMemoryAccess()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCOptAddrMode.cpp | 405 bool IsStore = Ldst->mayStore(); in canHoistLoadStoreTo() local
454 bool IsStore = Ldst.mayStore(); in changeToAddrMode() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kCollapseMOVEMPass.cpp | 205 bool IsStore = false) { in ProcessMI()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86EncodingOptimization.cpp | 362 bool IsStore = MI.getOperand(0).isReg() && MI.getOperand(1).isReg(); in optimizeMOV() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 1226 bool IsStore = MI->mayStore(); in spillVGPRtoAGPR() local
1263 bool IsStore = MI->mayStore(); in buildMUBUFOffsetLoadStore() local
1295 bool IsStore = TII->get(LoadStoreOp).mayStore(); in getFlatScratchSpillOpcode() local
1342 bool IsStore = Desc->mayStore(); in buildSpillLoadStore() local
|
| H A D | AMDGPULegalizerInfo.cpp | 1426 const bool IsStore = Op == G_STORE; in AMDGPULegalizerInfo() local
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCVSXSwapRemoval.cpp | 75 unsigned int IsStore : 1; member
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCInstructionSelector.cpp | 156 const bool IsStore = GenericOpc == TargetOpcode::G_STORE; in selectLoadStoreOp() local
|
| /freebsd/contrib/llvm-project/clang/lib/Sema/ |
| H A D | SemaRISCV.cpp | 1312 bool IsStore = BuiltinID == RISCV::BI__builtin_riscv_ntl_store; in CheckBuiltinFunctionCall() local
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | Thumb2SizeReduction.cpp | 464 bool IsStore = Entry.WideOpc == ARM::t2STR_POST; in ReduceLoadStore() local
|
| H A D | ARMLoadStoreOptimizer.cpp | 502 bool IsStore = in UpdateBaseRegUses() local
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonExpandCondsets.cpp | 846 bool IsLoad = TheI.mayLoad(), IsStore = TheI.mayStore(); in canMoveMemTo() local
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| H A D | HexagonConstExtenders.cpp | 1148 bool IsStore = MI.mayStore(); in recordExtender() local
|
| /freebsd/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CGAtomic.cpp | 1225 bool IsStore = E->getOp() == AtomicExpr::AO__c11_atomic_store || in EmitAtomicExpr() local
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| H A D | AMDGPUInstPrinter.cpp | 217 bool IsStore = TID.mayStore(); in printTH() local
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 5063 bool IsStore = (Instruction::Store == Opcode); in getMaskedMemoryOpCost() local
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUBaseInfo.cpp | 1474 bool IsStore) { in getCombinedCountBitMask()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 2981 bool IsStore = isa<GStore>(I); in select() local
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 5003 bool IsStore = TID.mayStore(); in validateTHAndScopeBits() local
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 1446 bool IsStore = Opcode == TargetOpcode::G_STORE; in applyCombineIndexedLoadStore() local
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 1571 auto SetRVVLoadStoreInfo = [&](unsigned PtrOp, bool IsStore, in getTgtMemIntrinsic() argument
[all...] |
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 23214 bool IsStore = false; in performNEONPostLDSTCombine() local
|