| /freebsd/contrib/llvm-project/llvm/lib/ExecutionEngine/JITLink/ |
| H A D | ELF_aarch64.cpp | 198 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addSingleRelocation() local
207 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addSingleRelocation() local
224 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addSingleRelocation() local
235 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addSingleRelocation() local
246 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addSingleRelocation() local
257 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addSingleRelocation() local
268 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addSingleRelocation() local
279 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addSingleRelocation() local
290 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addSingleRelocation() local
301 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addSingleRelocation() local
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| H A D | MachO_arm64.cpp | 353 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addRelocations() local
397 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addRelocations() local
417 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addRelocations() local
431 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addRelocations() local
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| /freebsd/contrib/llvm-project/llvm/include/llvm/ExecutionEngine/JITLink/ |
| H A D | aarch64.h | 362 inline bool isLoadStoreImm12(uint32_t Instr) { in isLoadStoreImm12()
367 inline bool isTestAndBranchImm14(uint32_t Instr) { in isTestAndBranchImm14()
372 inline bool isCondBranchImm19(uint32_t Instr) { in isCondBranchImm19()
377 inline bool isCompAndBranchImm19(uint32_t Instr) { in isCompAndBranchImm19()
382 inline bool isADR(uint32_t Instr) { in isADR()
387 inline bool isLDRLiteral(uint32_t Instr) { in isLDRLiteral()
398 inline unsigned getPageOffset12Shift(uint32_t Instr) { in getPageOffset12Shift()
414 inline bool isMoveWideImm16(uint32_t Instr) { in isMoveWideImm16()
423 inline unsigned getMoveWide16Shift(uint32_t Instr) { in getMoveWide16Shift()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsInstructionSelector.cpp | 737 struct Instr { in select() struct
738 unsigned Opcode; in select()
739 Register Def, LHS, RHS; in select()
740 Instr(unsigned Opcode, Register Def, Register LHS, Register RHS) in select() function
743 bool hasImm() const { in select()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/ |
| H A D | VectorUtils.h | 476 InterleaveGroup(InstTy *Instr, int32_t Stride, Align Alignment) in InterleaveGroup()
495 bool insertMember(InstTy *Instr, int32_t Index, Align NewAlign) { in insertMember()
547 uint32_t getIndex(const InstTy *Instr) const { in getIndex()
649 bool isInterleaved(Instruction *Instr) const { in isInterleaved()
657 getInterleaveGroup(const Instruction *Instr) const { in getInterleaveGroup()
732 createInterleaveGroup(Instruction *Instr, int Stride, Align Alignment) { in createInterleaveGroup()
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/GlobalISel/ |
| H A D | GIMatchDagPredicate.cpp | |
| H A D | GIMatchDagPredicate.h | |
| H A D | GIMatchTree.cpp | |
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RemoveRedundantDebugValues.cpp | 138 for (auto &Instr : DbgValsToBeRemoved) { in reduceDbgValsForwardScan() local
193 for (auto &Instr : DbgValsToBeRemoved) { in reduceDbgValsBackwardScan() local
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| H A D | MachineUniformityAnalysis.cpp | 32 const MachineInstr &Instr) { in markDefsDivergent()
79 const MachineInstr &Instr) { in pushUsers()
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| H A D | MachineSSAContext.cpp | 76 if (auto *Instr = MRI->getUniqueVRegDef(Value)) { print() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMFeatures.h | 24 inline bool isV8EligibleForIT(const InstrType *Instr) { in isV8EligibleForIT()
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| H A D | MVETPAndVPTOptimisationsPass.cpp | 574 static ARMCC::CondCodes GetCondCode(MachineInstr &Instr) { in GetCondCode()
607 static bool IsWritingToVCCR(MachineInstr &Instr) { in IsWritingToVCCR()
630 MachineBasicBlock &MBB, MachineInstr &Instr, MachineOperand &User, in ReplaceRegisterUseWithVPNOT()
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| H A D | Thumb1InstrInfo.cpp | 180 unsigned Instr; in expandLoadStackGuard() local
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | UniformityAnalysis.cpp | 29 const Instruction &Instr) { in markDefsDivergent() argument
59 const Instruction &Instr) { in pushUsers() argument
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/Disassembler/ |
| H A D | LanaiDisassembler.cpp | 90 static void PostOperandDecodeAdjust(MCInst &Instr, uint32_t Insn) { in PostOperandDecodeAdjust()
132 LanaiDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, in getInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXProxyRegErasure.cpp | 107 void NVPTXProxyRegErasure::replaceRegisterUsage(MachineInstr &Instr, in replaceRegisterUsage()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | CorrelatedValuePropagation.cpp | 746 static bool narrowSDivOrSRem(BinaryOperator *Instr, const ConstantRange &LCR, in narrowSDivOrSRem()
792 static bool expandUDivOrURem(BinaryOperator *Instr, const ConstantRange &XCR, in expandUDivOrURem()
875 static bool narrowUDivOrURem(BinaryOperator *Instr, const ConstantRange &XCR, in narrowUDivOrURem()
912 static bool processUDivOrURem(BinaryOperator *Instr, LazyValueInfo *LVI) { in processUDivOrURem()
1042 static bool processSDivOrSRem(BinaryOperator *Instr, LazyValueInfo *LVI) { in processSDivOrSRem()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | DbgEntityHistoryCalculator.h | 78 Entry(const MachineInstr *Instr, EntryKind Kind) in Entry()
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| H A D | LiveIntervals.h | 232 bool isNotInMIMap(const MachineInstr &Instr) const { in isNotInMIMap()
237 SlotIndex getInstructionIndex(const MachineInstr &Instr) const { in getInstructionIndex()
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| /freebsd/contrib/llvm-project/llvm/lib/IR/ |
| H A D | SSAContext.cpp | 76 isConstantOrUndefValuePhi(const Instruction & Instr) isConstantOrUndefValuePhi() argument
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| H A D | FPEnv.cpp | 90 Intrinsic::ID getConstrainedIntrinsicID(const Instruction &Instr) { in getConstrainedIntrinsicID()
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/GlobalISel/ |
| H A D | PatternParser.cpp | 127 auto &Instr = CGT.getInstruction(IP->getOperatorAsDef(DiagLoc)); in parseInstructionPattern() local
134 const CodeGenInstruction &Instr = getInstrForIntrinsic(CGT, Intrin); in parseInstructionPattern() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreLowerThreadLocal.cpp | 97 } else if (Instruction *Instr = dyn_cast<Instruction>(WU)) { in replaceConstantExprOp() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUGlobalISelDivergenceLowering.cpp | 133 MachineInstr *Instr = MRI->getVRegDef(Reg); in buildRegCopyToLaneMask() local
|