1 //===-- Thumb2ITBlockPass.cpp - Insert Thumb-2 IT blocks ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "ARM.h"
10 #include "ARMMachineFunctionInfo.h"
11 #include "ARMSubtarget.h"
12 #include "Thumb2InstrInfo.h"
13 #include "llvm/ADT/SmallSet.h"
14 #include "llvm/ADT/SmallVector.h"
15 #include "llvm/ADT/Statistic.h"
16 #include "llvm/ADT/StringRef.h"
17 #include "llvm/CodeGen/MachineBasicBlock.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFunctionPass.h"
20 #include "llvm/CodeGen/MachineInstr.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineInstrBundle.h"
23 #include "llvm/CodeGen/MachineOperand.h"
24 #include "llvm/IR/DebugLoc.h"
25 #include "llvm/MC/MCInstrDesc.h"
26 #include <cassert>
27 #include <new>
28
29 using namespace llvm;
30
31 #define DEBUG_TYPE "thumb2-it"
32 #define PASS_NAME "Thumb IT blocks insertion pass"
33
34 STATISTIC(NumITs, "Number of IT blocks inserted");
35 STATISTIC(NumMovedInsts, "Number of predicated instructions moved");
36
37 using RegisterSet = SmallSet<unsigned, 4>;
38
39 namespace {
40
41 class Thumb2ITBlock : public MachineFunctionPass {
42 public:
43 static char ID;
44
45 bool restrictIT;
46 const Thumb2InstrInfo *TII;
47 const TargetRegisterInfo *TRI;
48 ARMFunctionInfo *AFI;
49
Thumb2ITBlock()50 Thumb2ITBlock() : MachineFunctionPass(ID) {}
51
52 bool runOnMachineFunction(MachineFunction &Fn) override;
53
getRequiredProperties() const54 MachineFunctionProperties getRequiredProperties() const override {
55 return MachineFunctionProperties().setNoVRegs();
56 }
57
getPassName() const58 StringRef getPassName() const override {
59 return PASS_NAME;
60 }
61
62 private:
63 bool MoveCopyOutOfITBlock(MachineInstr *MI,
64 ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
65 RegisterSet &Defs, RegisterSet &Uses);
66 bool InsertITInstructions(MachineBasicBlock &Block);
67 };
68
69 char Thumb2ITBlock::ID = 0;
70
71 } // end anonymous namespace
72
INITIALIZE_PASS(Thumb2ITBlock,DEBUG_TYPE,PASS_NAME,false,false)73 INITIALIZE_PASS(Thumb2ITBlock, DEBUG_TYPE, PASS_NAME, false, false)
74
75 /// TrackDefUses - Tracking what registers are being defined and used by
76 /// instructions in the IT block. This also tracks "dependencies", i.e. uses
77 /// in the IT block that are defined before the IT instruction.
78 static void TrackDefUses(MachineInstr *MI, RegisterSet &Defs, RegisterSet &Uses,
79 const TargetRegisterInfo *TRI) {
80 using RegList = SmallVector<unsigned, 4>;
81 RegList LocalDefs;
82 RegList LocalUses;
83
84 for (auto &MO : MI->operands()) {
85 if (!MO.isReg())
86 continue;
87 Register Reg = MO.getReg();
88 if (!Reg || Reg == ARM::ITSTATE || Reg == ARM::SP)
89 continue;
90 if (MO.isUse())
91 LocalUses.push_back(Reg);
92 else
93 LocalDefs.push_back(Reg);
94 }
95
96 auto InsertUsesDefs = [&](RegList &Regs, RegisterSet &UsesDefs) {
97 for (unsigned Reg : Regs)
98 UsesDefs.insert_range(TRI->subregs_inclusive(Reg));
99 };
100
101 InsertUsesDefs(LocalDefs, Defs);
102 InsertUsesDefs(LocalUses, Uses);
103 }
104
105 /// Clear kill flags for any uses in the given set. This will likely
106 /// conservatively remove more kill flags than are necessary, but removing them
107 /// is safer than incorrect kill flags remaining on instructions.
ClearKillFlags(MachineInstr * MI,RegisterSet & Uses)108 static void ClearKillFlags(MachineInstr *MI, RegisterSet &Uses) {
109 for (MachineOperand &MO : MI->operands()) {
110 if (!MO.isReg() || MO.isDef() || !MO.isKill())
111 continue;
112 if (!Uses.count(MO.getReg()))
113 continue;
114 MO.setIsKill(false);
115 }
116 }
117
isCopy(MachineInstr * MI)118 static bool isCopy(MachineInstr *MI) {
119 switch (MI->getOpcode()) {
120 default:
121 return false;
122 case ARM::MOVr:
123 case ARM::MOVr_TC:
124 case ARM::tMOVr:
125 case ARM::t2MOVr:
126 return true;
127 }
128 }
129
130 bool
MoveCopyOutOfITBlock(MachineInstr * MI,ARMCC::CondCodes CC,ARMCC::CondCodes OCC,RegisterSet & Defs,RegisterSet & Uses)131 Thumb2ITBlock::MoveCopyOutOfITBlock(MachineInstr *MI,
132 ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
133 RegisterSet &Defs, RegisterSet &Uses) {
134 if (!isCopy(MI))
135 return false;
136 // llvm models select's as two-address instructions. That means a copy
137 // is inserted before a t2MOVccr, etc. If the copy is scheduled in
138 // between selects we would end up creating multiple IT blocks.
139 assert(MI->getOperand(0).getSubReg() == 0 &&
140 MI->getOperand(1).getSubReg() == 0 &&
141 "Sub-register indices still around?");
142
143 Register DstReg = MI->getOperand(0).getReg();
144 Register SrcReg = MI->getOperand(1).getReg();
145
146 // First check if it's safe to move it.
147 if (Uses.count(DstReg) || Defs.count(SrcReg))
148 return false;
149
150 // If the CPSR is defined by this copy, then we don't want to move it. E.g.,
151 // if we have:
152 //
153 // movs r1, r1
154 // rsb r1, 0
155 // movs r2, r2
156 // rsb r2, 0
157 //
158 // we don't want this to be converted to:
159 //
160 // movs r1, r1
161 // movs r2, r2
162 // itt mi
163 // rsb r1, 0
164 // rsb r2, 0
165 //
166 const MCInstrDesc &MCID = MI->getDesc();
167 if (MI->hasOptionalDef() &&
168 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)
169 return false;
170
171 // Then peek at the next instruction to see if it's predicated on CC or OCC.
172 // If not, then there is nothing to be gained by moving the copy.
173 MachineBasicBlock::iterator I = MI;
174 ++I;
175 MachineBasicBlock::iterator E = MI->getParent()->end();
176
177 while (I != E && I->isDebugInstr())
178 ++I;
179
180 if (I != E) {
181 Register NPredReg;
182 ARMCC::CondCodes NCC = getITInstrPredicate(*I, NPredReg);
183 if (NCC == CC || NCC == OCC)
184 return true;
185 }
186 return false;
187 }
188
InsertITInstructions(MachineBasicBlock & MBB)189 bool Thumb2ITBlock::InsertITInstructions(MachineBasicBlock &MBB) {
190 bool Modified = false;
191 RegisterSet Defs, Uses;
192 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
193
194 while (MBBI != E) {
195 MachineInstr *MI = &*MBBI;
196 DebugLoc dl = MI->getDebugLoc();
197 Register PredReg;
198 ARMCC::CondCodes CC = getITInstrPredicate(*MI, PredReg);
199 if (CC == ARMCC::AL) {
200 ++MBBI;
201 continue;
202 }
203
204 Defs.clear();
205 Uses.clear();
206 TrackDefUses(MI, Defs, Uses, TRI);
207
208 // Insert an IT instruction.
209 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT))
210 .addImm(CC);
211
212 // Add implicit use of ITSTATE to IT block instructions.
213 MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
214 true/*isImp*/, false/*isKill*/));
215
216 MachineInstr *LastITMI = MI;
217 MachineBasicBlock::iterator InsertPos = MIB.getInstr();
218 ++MBBI;
219
220 // Form IT block.
221 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
222 unsigned Mask = 0, Pos = 3;
223
224 // IT blocks are limited to one conditional op if -arm-restrict-it
225 // is set: skip the loop
226 if (!restrictIT) {
227 LLVM_DEBUG(dbgs() << "Allowing complex IT block\n");
228 // Branches, including tricky ones like LDM_RET, need to end an IT
229 // block so check the instruction we just put in the block.
230 for (; MBBI != E && Pos &&
231 (!MI->isBranch() && !MI->isReturn()) ; ++MBBI) {
232 if (MBBI->isDebugInstr())
233 continue;
234
235 MachineInstr *NMI = &*MBBI;
236 MI = NMI;
237
238 Register NPredReg;
239 ARMCC::CondCodes NCC = getITInstrPredicate(*NMI, NPredReg);
240 if (NCC == CC || NCC == OCC) {
241 Mask |= ((NCC ^ CC) & 1) << Pos;
242 // Add implicit use of ITSTATE.
243 NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
244 true/*isImp*/, false/*isKill*/));
245 LastITMI = NMI;
246 } else {
247 if (NCC == ARMCC::AL &&
248 MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) {
249 --MBBI;
250 MBB.remove(NMI);
251 MBB.insert(InsertPos, NMI);
252 ClearKillFlags(MI, Uses);
253 ++NumMovedInsts;
254 continue;
255 }
256 break;
257 }
258 TrackDefUses(NMI, Defs, Uses, TRI);
259 --Pos;
260 }
261 }
262
263 // Finalize IT mask.
264 Mask |= (1 << Pos);
265 MIB.addImm(Mask);
266
267 // Last instruction in IT block kills ITSTATE.
268 LastITMI->findRegisterUseOperand(ARM::ITSTATE, /*TRI=*/nullptr)
269 ->setIsKill();
270
271 // Finalize the bundle.
272 finalizeBundle(MBB, InsertPos.getInstrIterator(),
273 ++LastITMI->getIterator());
274
275 Modified = true;
276 ++NumITs;
277 }
278
279 return Modified;
280 }
281
runOnMachineFunction(MachineFunction & Fn)282 bool Thumb2ITBlock::runOnMachineFunction(MachineFunction &Fn) {
283 const ARMSubtarget &STI = Fn.getSubtarget<ARMSubtarget>();
284 if (!STI.isThumb2())
285 return false;
286 AFI = Fn.getInfo<ARMFunctionInfo>();
287 TII = static_cast<const Thumb2InstrInfo *>(STI.getInstrInfo());
288 TRI = STI.getRegisterInfo();
289 restrictIT = STI.restrictIT();
290
291 if (!AFI->isThumbFunction())
292 return false;
293
294 bool Modified = false;
295 for (auto &MBB : Fn )
296 Modified |= InsertITInstructions(MBB);
297
298 if (Modified)
299 AFI->setHasITBlocks(true);
300
301 return Modified;
302 }
303
304 /// createThumb2ITBlockPass - Returns an instance of the Thumb2 IT blocks
305 /// insertion pass.
createThumb2ITBlockPass()306 FunctionPass *llvm::createThumb2ITBlockPass() { return new Thumb2ITBlock(); }
307