xref: /freebsd/contrib/llvm-project/llvm/lib/TargetParser/X86TargetParser.cpp (revision 700637cbb5e582861067a11aaca4d053546871d2) 
1 //===-- X86TargetParser - Parser for X86 features ---------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements a target parser to recognise X86 hardware features.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/TargetParser/X86TargetParser.h"
14 #include "llvm/ADT/Bitset.h"
15 #include "llvm/ADT/StringSwitch.h"
16 #include <numeric>
17 
18 using namespace llvm;
19 using namespace llvm::X86;
20 
21 namespace {
22 
23 using FeatureBitset = Bitset<X86::CPU_FEATURE_MAX>;
24 
25 struct ProcInfo {
26   StringLiteral Name;
27   X86::CPUKind Kind;
28   unsigned KeyFeature;
29   FeatureBitset Features;
30   char Mangling;
31   bool OnlyForCPUDispatchSpecific;
32 };
33 
34 struct FeatureInfo {
35   StringLiteral NameWithPlus;
36   FeatureBitset ImpliedFeatures;
37 
getName__anon54b81fad0111::FeatureInfo38   StringRef getName(bool WithPlus = false) const {
39     assert(NameWithPlus[0] == '+' && "Expected string to start with '+'");
40     if (WithPlus)
41       return NameWithPlus;
42     return NameWithPlus.drop_front();
43   }
44 };
45 
46 } // end anonymous namespace
47 
48 #define X86_FEATURE(ENUM, STRING)                                              \
49   constexpr FeatureBitset Feature##ENUM = {X86::FEATURE_##ENUM};
50 #include "llvm/TargetParser/X86TargetParser.def"
51 
52 // Pentium with MMX.
53 constexpr FeatureBitset FeaturesPentiumMMX =
54     FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
55 
56 // Pentium 2 and 3.
57 constexpr FeatureBitset FeaturesPentium2 =
58     FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeatureFXSR | FeatureCMOV;
59 constexpr FeatureBitset FeaturesPentium3 = FeaturesPentium2 | FeatureSSE;
60 
61 // Pentium 4 CPUs
62 constexpr FeatureBitset FeaturesPentium4 = FeaturesPentium3 | FeatureSSE2;
63 constexpr FeatureBitset FeaturesPrescott = FeaturesPentium4 | FeatureSSE3;
64 constexpr FeatureBitset FeaturesNocona =
65     FeaturesPrescott | Feature64BIT | FeatureCMPXCHG16B;
66 
67 // Basic 64-bit capable CPU.
68 constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | Feature64BIT;
69 constexpr FeatureBitset FeaturesX86_64_V2 = FeaturesX86_64 | FeatureSAHF |
70                                             FeaturePOPCNT | FeatureCRC32 |
71                                             FeatureSSE4_2 | FeatureCMPXCHG16B;
72 constexpr FeatureBitset FeaturesX86_64_V3 =
73     FeaturesX86_64_V2 | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureF16C |
74     FeatureFMA | FeatureLZCNT | FeatureMOVBE | FeatureXSAVE;
75 constexpr FeatureBitset FeaturesX86_64_V4 = FeaturesX86_64_V3 | FeatureEVEX512 |
76                                             FeatureAVX512BW | FeatureAVX512CD |
77                                             FeatureAVX512DQ | FeatureAVX512VL;
78 
79 // Intel Core CPUs
80 constexpr FeatureBitset FeaturesCore2 =
81     FeaturesNocona | FeatureSAHF | FeatureSSSE3;
82 constexpr FeatureBitset FeaturesPenryn = FeaturesCore2 | FeatureSSE4_1;
83 constexpr FeatureBitset FeaturesNehalem =
84     FeaturesPenryn | FeaturePOPCNT | FeatureCRC32 | FeatureSSE4_2;
85 constexpr FeatureBitset FeaturesWestmere = FeaturesNehalem | FeaturePCLMUL;
86 constexpr FeatureBitset FeaturesSandyBridge =
87     FeaturesWestmere | FeatureAVX | FeatureXSAVE | FeatureXSAVEOPT;
88 constexpr FeatureBitset FeaturesIvyBridge =
89     FeaturesSandyBridge | FeatureF16C | FeatureFSGSBASE | FeatureRDRND;
90 constexpr FeatureBitset FeaturesHaswell =
91     FeaturesIvyBridge | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureFMA |
92     FeatureINVPCID | FeatureLZCNT | FeatureMOVBE;
93 constexpr FeatureBitset FeaturesBroadwell =
94     FeaturesHaswell | FeatureADX | FeaturePRFCHW | FeatureRDSEED;
95 
96 // Intel Knights Landing and Knights Mill
97 // Knights Landing has feature parity with Broadwell.
98 constexpr FeatureBitset FeaturesKNL = FeaturesBroadwell | FeatureAES |
99                                       FeatureAVX512F | FeatureEVEX512 |
100                                       FeatureAVX512CD;
101 constexpr FeatureBitset FeaturesKNM = FeaturesKNL | FeatureAVX512VPOPCNTDQ;
102 
103 // Intel Skylake processors.
104 constexpr FeatureBitset FeaturesSkylakeClient =
105     FeaturesBroadwell | FeatureAES | FeatureCLFLUSHOPT | FeatureXSAVEC |
106     FeatureXSAVES | FeatureSGX;
107 // SkylakeServer inherits all SkylakeClient features except SGX.
108 // FIXME: That doesn't match gcc.
109 constexpr FeatureBitset FeaturesSkylakeServer =
110     (FeaturesSkylakeClient & ~FeatureSGX) | FeatureAVX512F | FeatureEVEX512 |
111     FeatureAVX512CD | FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL |
112     FeatureCLWB | FeaturePKU;
113 constexpr FeatureBitset FeaturesCascadeLake =
114     FeaturesSkylakeServer | FeatureAVX512VNNI;
115 constexpr FeatureBitset FeaturesCooperLake =
116     FeaturesCascadeLake | FeatureAVX512BF16;
117 
118 // Intel 10nm processors.
119 constexpr FeatureBitset FeaturesCannonlake =
120     FeaturesSkylakeClient | FeatureAVX512F | FeatureEVEX512 | FeatureAVX512CD |
121     FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA |
122     FeatureAVX512VBMI | FeaturePKU | FeatureSHA;
123 constexpr FeatureBitset FeaturesICLClient =
124     FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 |
125     FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureGFNI | FeatureRDPID |
126     FeatureVAES | FeatureVPCLMULQDQ;
127 constexpr FeatureBitset FeaturesRocketlake = FeaturesICLClient & ~FeatureSGX;
128 constexpr FeatureBitset FeaturesICLServer =
129     FeaturesICLClient | FeatureCLWB | FeaturePCONFIG | FeatureWBNOINVD;
130 constexpr FeatureBitset FeaturesTigerlake =
131     FeaturesICLClient | FeatureAVX512VP2INTERSECT | FeatureMOVDIR64B |
132     FeatureCLWB | FeatureMOVDIRI | FeatureSHSTK | FeatureKL | FeatureWIDEKL;
133 constexpr FeatureBitset FeaturesSapphireRapids =
134     FeaturesICLServer | FeatureAMX_BF16 | FeatureAMX_INT8 | FeatureAMX_TILE |
135     FeatureAVX512BF16 | FeatureAVX512FP16 | FeatureAVXVNNI | FeatureCLDEMOTE |
136     FeatureENQCMD | FeatureMOVDIR64B | FeatureMOVDIRI | FeaturePTWRITE |
137     FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureUINTR |
138     FeatureWAITPKG | FeatureAVX512DQ | FeatureAVX512VL;
139 constexpr FeatureBitset FeaturesGraniteRapids =
140     FeaturesSapphireRapids | FeatureAMX_FP16 | FeaturePREFETCHI;
141 constexpr FeatureBitset FeaturesDiamondRapids =
142     FeaturesGraniteRapids | FeatureAMX_COMPLEX | FeatureAVX10_2_512 |
143     FeatureCMPCCXADD | FeatureAVXIFMA | FeatureAVXNECONVERT |
144     FeatureAVXVNNIINT8 | FeatureAVXVNNIINT16 | FeatureSHA512 | FeatureSM3 |
145     FeatureSM4 | FeatureEGPR | FeatureZU | FeatureCCMP | FeaturePush2Pop2 |
146     FeaturePPX | FeatureNDD | FeatureNF | FeatureCF | FeatureMOVRS |
147     FeatureAMX_MOVRS | FeatureAMX_AVX512 | FeatureAMX_FP8 | FeatureAMX_TF32 |
148     FeatureAMX_TRANSPOSE | FeatureUSERMSR;
149 
150 // Intel Atom processors.
151 // Bonnell has feature parity with Core2 and adds MOVBE.
152 constexpr FeatureBitset FeaturesBonnell = FeaturesCore2 | FeatureMOVBE;
153 // Silvermont has parity with Westmere and Bonnell plus PRFCHW and RDRND.
154 constexpr FeatureBitset FeaturesSilvermont =
155     FeaturesBonnell | FeaturesWestmere | FeaturePRFCHW | FeatureRDRND;
156 constexpr FeatureBitset FeaturesGoldmont =
157     FeaturesSilvermont | FeatureAES | FeatureCLFLUSHOPT | FeatureFSGSBASE |
158     FeatureRDSEED | FeatureSHA | FeatureXSAVE | FeatureXSAVEC |
159     FeatureXSAVEOPT | FeatureXSAVES;
160 constexpr FeatureBitset FeaturesGoldmontPlus =
161     FeaturesGoldmont | FeaturePTWRITE | FeatureRDPID | FeatureSGX;
162 constexpr FeatureBitset FeaturesTremont =
163     FeaturesGoldmontPlus | FeatureCLWB | FeatureGFNI;
164 constexpr FeatureBitset FeaturesAlderlake =
165     FeaturesTremont | FeatureADX | FeatureBMI | FeatureBMI2 | FeatureF16C |
166     FeatureFMA | FeatureINVPCID | FeatureLZCNT | FeaturePCONFIG | FeaturePKU |
167     FeatureSERIALIZE | FeatureSHSTK | FeatureVAES | FeatureVPCLMULQDQ |
168     FeatureMOVDIR64B | FeatureMOVDIRI | FeatureWAITPKG | FeatureAVXVNNI |
169     FeatureHRESET | FeatureWIDEKL;
170 constexpr FeatureBitset FeaturesArrowlake =
171     FeaturesAlderlake | FeatureCMPCCXADD | FeatureAVXIFMA | FeatureUINTR |
172     FeatureENQCMD | FeatureAVXNECONVERT | FeatureAVXVNNIINT8;
173 constexpr FeatureBitset FeaturesSierraforest =
174     FeaturesArrowlake | FeatureCLDEMOTE;
175 constexpr FeatureBitset FeaturesArrowlakeS =
176     FeaturesArrowlake | FeatureAVXVNNIINT16 | FeatureSHA512 | FeatureSM3 |
177     FeatureSM4;
178 constexpr FeatureBitset FeaturesPantherlake =
179     FeaturesArrowlakeS ^ FeatureWIDEKL | FeaturePREFETCHI;
180 constexpr FeatureBitset FeaturesClearwaterforest =
181     FeaturesSierraforest ^ FeatureWIDEKL | FeatureAVXVNNIINT16 | FeatureSHA512 |
182     FeatureSM3 | FeatureSM4 | FeaturePREFETCHI | FeatureUSERMSR;
183 
184 // Geode Processor.
185 constexpr FeatureBitset FeaturesGeode =
186     FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeaturePRFCHW;
187 
188 // K6 processor.
189 constexpr FeatureBitset FeaturesK6 = FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
190 
191 // K7 and K8 architecture processors.
192 constexpr FeatureBitset FeaturesAthlon =
193     FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeaturePRFCHW;
194 constexpr FeatureBitset FeaturesAthlonXP =
195     FeaturesAthlon | FeatureFXSR | FeatureSSE;
196 constexpr FeatureBitset FeaturesK8 =
197     FeaturesAthlonXP | FeatureSSE2 | Feature64BIT;
198 constexpr FeatureBitset FeaturesK8SSE3 = FeaturesK8 | FeatureSSE3;
199 constexpr FeatureBitset FeaturesAMDFAM10 =
200     FeaturesK8SSE3 | FeatureCMPXCHG16B | FeatureLZCNT | FeaturePOPCNT |
201     FeaturePRFCHW | FeatureSAHF | FeatureSSE4_A;
202 
203 // Bobcat architecture processors.
204 constexpr FeatureBitset FeaturesBTVER1 =
205     FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT |
206     FeatureFXSR | FeatureLZCNT | FeatureMMX | FeaturePOPCNT | FeaturePRFCHW |
207     FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_A |
208     FeatureSAHF;
209 constexpr FeatureBitset FeaturesBTVER2 =
210     FeaturesBTVER1 | FeatureAES | FeatureAVX | FeatureBMI | FeatureCRC32 |
211     FeatureF16C | FeatureMOVBE | FeaturePCLMUL | FeatureXSAVE | FeatureXSAVEOPT;
212 
213 // AMD Bulldozer architecture processors.
214 constexpr FeatureBitset FeaturesBDVER1 =
215     FeatureX87 | FeatureAES | FeatureAVX | FeatureCMPXCHG8B |
216     FeatureCMPXCHG16B | FeatureCRC32 | Feature64BIT | FeatureFMA4 |
217     FeatureFXSR | FeatureLWP | FeatureLZCNT | FeatureMMX | FeaturePCLMUL |
218     FeaturePOPCNT | FeaturePRFCHW | FeatureSAHF | FeatureSSE | FeatureSSE2 |
219     FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4_A |
220     FeatureXOP | FeatureXSAVE;
221 constexpr FeatureBitset FeaturesBDVER2 =
222     FeaturesBDVER1 | FeatureBMI | FeatureFMA | FeatureF16C | FeatureTBM;
223 constexpr FeatureBitset FeaturesBDVER3 =
224     FeaturesBDVER2 | FeatureFSGSBASE | FeatureXSAVEOPT;
225 constexpr FeatureBitset FeaturesBDVER4 = FeaturesBDVER3 | FeatureAVX2 |
226                                          FeatureBMI2 | FeatureMOVBE |
227                                          FeatureMWAITX | FeatureRDRND;
228 
229 // AMD Zen architecture processors.
230 constexpr FeatureBitset FeaturesZNVER1 =
231     FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 |
232     FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO |
233     FeatureCMPXCHG8B | FeatureCMPXCHG16B | FeatureCRC32 | Feature64BIT |
234     FeatureF16C | FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT |
235     FeatureMMX | FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT |
236     FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA |
237     FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 |
238     FeatureSSE4_2 | FeatureSSE4_A | FeatureXSAVE | FeatureXSAVEC |
239     FeatureXSAVEOPT | FeatureXSAVES;
240 constexpr FeatureBitset FeaturesZNVER2 = FeaturesZNVER1 | FeatureCLWB |
241                                          FeatureRDPID | FeatureRDPRU |
242                                          FeatureWBNOINVD;
243 static constexpr FeatureBitset FeaturesZNVER3 = FeaturesZNVER2 |
244                                                 FeatureINVPCID | FeaturePKU |
245                                                 FeatureVAES | FeatureVPCLMULQDQ;
246 static constexpr FeatureBitset FeaturesZNVER4 =
247     FeaturesZNVER3 | FeatureAVX512F | FeatureEVEX512 | FeatureAVX512CD |
248     FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA |
249     FeatureAVX512VBMI | FeatureAVX512VBMI2 | FeatureAVX512VNNI |
250     FeatureAVX512BITALG | FeatureAVX512VPOPCNTDQ | FeatureAVX512BF16 |
251     FeatureGFNI | FeatureSHSTK;
252 
253 static constexpr FeatureBitset FeaturesZNVER5 =
254     FeaturesZNVER4 | FeatureAVXVNNI | FeatureMOVDIRI | FeatureMOVDIR64B |
255     FeatureAVX512VP2INTERSECT | FeaturePREFETCHI | FeatureAVXVNNI;
256 
257 // D151696 tranplanted Mangling and OnlyForCPUDispatchSpecific from
258 // X86TargetParser.def to here. They are assigned by following ways:
259 // 1. Copy the mangling from the original CPU_SPEICIFC MACROs. If no, assign
260 // to '\0' by default, which means not support cpu_specific/dispatch feature.
261 // 2. set OnlyForCPUDispatchSpecific as true if this cpu name was not
262 // listed here before, which means it doesn't support -march, -mtune and so on.
263 // FIXME: Remove OnlyForCPUDispatchSpecific after all CPUs here support both
264 // cpu_dispatch/specific() feature and -march, -mtune, and so on.
265 // clang-format off
266 constexpr ProcInfo Processors[] = {
267  // Empty processor. Include X87 and CMPXCHG8 for backwards compatibility.
268   { {""}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B, '\0', false },
269   { {"generic"}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B | Feature64BIT, 'A', true },
270   // i386-generation processors.
271   { {"i386"}, CK_i386, ~0U, FeatureX87, '\0', false },
272   // i486-generation processors.
273   { {"i486"}, CK_i486, ~0U, FeatureX87, '\0', false },
274   { {"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX, '\0', false },
275   { {"winchip2"}, CK_WinChip2, ~0U, FeaturesPentiumMMX | FeaturePRFCHW, '\0', false },
276   { {"c3"}, CK_C3, ~0U, FeaturesPentiumMMX | FeaturePRFCHW, '\0', false },
277   // i586-generation processors, P5 microarchitecture based.
278   { {"i586"}, CK_i586, ~0U, FeatureX87 | FeatureCMPXCHG8B, '\0', false },
279   { {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B, 'B', false },
280   { {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX, '\0', false },
281   { {"pentium_mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX, 'D', true },
282   // i686-generation processors, P6 / Pentium M microarchitecture based.
283   { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, 'C', false },
284   { {"pentium_pro"}, CK_PentiumPro, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, 'C', true },
285   { {"i686"}, CK_i686, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, '\0', false },
286   { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2, 'E', false },
287   { {"pentium_ii"}, CK_Pentium2, ~0U, FeaturesPentium2, 'E', true },
288   { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', false },
289   { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', false },
290   { {"pentium_iii"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', true },
291   { {"pentium_iii_no_xmm_regs"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', true },
292   { {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4, '\0', false },
293   { {"pentium_m"}, CK_PentiumM, ~0U, FeaturesPentium4, 'K', true },
294   { {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3, '\0', false },
295   { {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott, 'L', false },
296   // Netburst microarchitecture based processors.
297   { {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4, 'J', false },
298   { {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4, 'J', false },
299   { {"pentium_4"}, CK_Pentium4, ~0U, FeaturesPentium4, 'J', true },
300   { {"pentium_4_sse3"}, CK_Prescott, ~0U, FeaturesPrescott, 'L', true },
301   { {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott, 'L', false },
302   { {"nocona"}, CK_Nocona, ~0U, FeaturesNocona, 'L', false },
303   // Core microarchitecture based processors.
304   { {"core2"}, CK_Core2, FEATURE_SSSE3, FeaturesCore2, 'M', false },
305   { {"core_2_duo_ssse3"}, CK_Core2, ~0U, FeaturesCore2, 'M', true },
306   { {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn, 'N', false },
307   { {"core_2_duo_sse4_1"}, CK_Penryn, ~0U, FeaturesPenryn, 'N', true },
308   // Atom processors
309   { {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell, 'O', false },
310   { {"atom"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell, 'O', false },
311   { {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont, 'c', false },
312   { {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont, 'c', false },
313   { {"atom_sse4_2"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'c', true },
314   { {"atom_sse4_2_movbe"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont, 'd', true },
315   { {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont, 'i', false },
316   { {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus, '\0', false },
317   { {"goldmont_plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus, 'd', true },
318   { {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont, 'd', false },
319   // Nehalem microarchitecture based processors.
320   { {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'P', false },
321   { {"core_i7_sse4_2"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'P', true },
322   { {"corei7"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'P', false },
323   // Westmere microarchitecture based processors.
324   { {"westmere"}, CK_Westmere, FEATURE_PCLMUL, FeaturesWestmere, 'Q', false },
325   { {"core_aes_pclmulqdq"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'Q', true },
326   // Sandy Bridge microarchitecture based processors.
327   { {"sandybridge"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge, 'R', false },
328   { {"core_2nd_gen_avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge, 'R', true },
329   { {"corei7-avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge, '\0', false },
330   // Ivy Bridge microarchitecture based processors.
331   { {"ivybridge"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge, 'S', false },
332   { {"core_3rd_gen_avx"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge, 'S', true },
333   { {"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge, '\0', false },
334   // Haswell microarchitecture based processors.
335   { {"haswell"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell, 'V', false },
336   { {"core-avx2"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell, '\0', false },
337   { {"core_4th_gen_avx"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell, 'V', true },
338   { {"core_4th_gen_avx_tsx"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell, 'W', true },
339   // Broadwell microarchitecture based processors.
340   { {"broadwell"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell, 'X', false },
341   { {"core_5th_gen_avx"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell, 'X', true },
342   { {"core_5th_gen_avx_tsx"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell, 'Y', true },
343   // Skylake client microarchitecture based processors.
344   { {"skylake"}, CK_SkylakeClient, FEATURE_AVX2, FeaturesSkylakeClient, 'b', false },
345   // Skylake server microarchitecture based processors.
346   { {"skylake-avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer, '\0', false },
347   { {"skx"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer, 'a', false },
348   { {"skylake_avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer, 'a', true },
349   // Cascadelake Server microarchitecture based processors.
350   { {"cascadelake"}, CK_Cascadelake, FEATURE_AVX512VNNI, FeaturesCascadeLake, 'o', false },
351   // Cooperlake Server microarchitecture based processors.
352   { {"cooperlake"}, CK_Cooperlake, FEATURE_AVX512BF16, FeaturesCooperLake, 'f', false },
353   // Cannonlake client microarchitecture based processors.
354   { {"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, FeaturesCannonlake, 'e', false },
355   // Icelake client microarchitecture based processors.
356   { {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient, '\0', false },
357   { {"icelake_client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient, 'k', true },
358   // Rocketlake microarchitecture based processors.
359   { {"rocketlake"}, CK_Rocketlake, FEATURE_AVX512VBMI2, FeaturesRocketlake, 'k', false },
360   // Icelake server microarchitecture based processors.
361   { {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer, '\0', false },
362   { {"icelake_server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer, 'k', true },
363   // Tigerlake microarchitecture based processors.
364   { {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake, 'l', false },
365   // Sapphire Rapids microarchitecture based processors.
366   { {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512FP16, FeaturesSapphireRapids, 'n', false },
367   // Alderlake microarchitecture based processors.
368   { {"alderlake"}, CK_Alderlake, FEATURE_AVX2, FeaturesAlderlake, 'p', false },
369   // Raptorlake microarchitecture based processors.
370   { {"raptorlake"}, CK_Raptorlake, FEATURE_AVX2, FeaturesAlderlake, 'p', false },
371   // Meteorlake microarchitecture based processors.
372   { {"meteorlake"}, CK_Meteorlake, FEATURE_AVX2, FeaturesAlderlake, 'p', false },
373   // Arrowlake microarchitecture based processors.
374   { {"arrowlake"}, CK_Arrowlake, FEATURE_AVX2, FeaturesArrowlake, 'p', false },
375   { {"arrowlake-s"}, CK_ArrowlakeS, FEATURE_AVX2, FeaturesArrowlakeS, '\0', false },
376   { {"arrowlake_s"}, CK_ArrowlakeS, FEATURE_AVX2, FeaturesArrowlakeS, 'p', true },
377   // Lunarlake microarchitecture based processors.
378   { {"lunarlake"}, CK_Lunarlake, FEATURE_AVX2, FeaturesArrowlakeS, 'p', false },
379   // Gracemont microarchitecture based processors.
380   { {"gracemont"}, CK_Gracemont, FEATURE_AVX2, FeaturesAlderlake, 'p', false },
381   // Pantherlake microarchitecture based processors.
382   { {"pantherlake"}, CK_Lunarlake, FEATURE_AVX2, FeaturesPantherlake, 'p', false },
383   // Sierraforest microarchitecture based processors.
384   { {"sierraforest"}, CK_Sierraforest, FEATURE_AVX2, FeaturesSierraforest, 'p', false },
385   // Grandridge microarchitecture based processors.
386   { {"grandridge"}, CK_Grandridge, FEATURE_AVX2, FeaturesSierraforest, 'p', false },
387   // Granite Rapids microarchitecture based processors.
388   { {"graniterapids"}, CK_Graniterapids, FEATURE_AVX512FP16, FeaturesGraniteRapids, 'n', false },
389   // Granite Rapids D microarchitecture based processors.
390   { {"graniterapids-d"}, CK_GraniterapidsD, FEATURE_AVX512FP16, FeaturesGraniteRapids | FeatureAMX_COMPLEX, '\0', false },
391   { {"graniterapids_d"}, CK_GraniterapidsD, FEATURE_AVX512FP16, FeaturesGraniteRapids | FeatureAMX_COMPLEX, 'n', true },
392   // Emerald Rapids microarchitecture based processors.
393   { {"emeraldrapids"}, CK_Emeraldrapids, FEATURE_AVX512FP16, FeaturesSapphireRapids, 'n', false },
394   // Clearwaterforest microarchitecture based processors.
395   { {"clearwaterforest"}, CK_Lunarlake, FEATURE_AVX2, FeaturesClearwaterforest, 'p', false },
396   // Diamond Rapids microarchitecture based processors.
397   { {"diamondrapids"}, CK_Diamondrapids, FEATURE_AVX10_2_512, FeaturesDiamondRapids, 'z', false },
398   // Knights Landing processor.
399   { {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL, 'Z', false },
400   { {"mic_avx512"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL, 'Z', true },
401   // Knights Mill processor.
402   { {"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, FeaturesKNM, 'j', false },
403   // Lakemont microarchitecture based processors.
404   { {"lakemont"}, CK_Lakemont, ~0U, FeatureCMPXCHG8B, '\0', false },
405   // K6 architecture processors.
406   { {"k6"}, CK_K6, ~0U, FeaturesK6, '\0', false },
407   { {"k6-2"}, CK_K6_2, ~0U, FeaturesK6 | FeaturePRFCHW, '\0', false },
408   { {"k6-3"}, CK_K6_3, ~0U, FeaturesK6 | FeaturePRFCHW, '\0', false },
409   // K7 architecture processors.
410   { {"athlon"}, CK_Athlon, ~0U, FeaturesAthlon, '\0', false },
411   { {"athlon-tbird"}, CK_Athlon, ~0U, FeaturesAthlon, '\0', false },
412   { {"athlon-xp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP, '\0', false },
413   { {"athlon-mp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP, '\0', false },
414   { {"athlon-4"}, CK_AthlonXP, ~0U, FeaturesAthlonXP, '\0', false },
415   // K8 architecture processors.
416   { {"k8"}, CK_K8, ~0U, FeaturesK8, '\0', false },
417   { {"athlon64"}, CK_K8, ~0U, FeaturesK8, '\0', false },
418   { {"athlon-fx"}, CK_K8, ~0U, FeaturesK8, '\0', false },
419   { {"opteron"}, CK_K8, ~0U, FeaturesK8, '\0', false },
420   { {"k8-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3, '\0', false },
421   { {"athlon64-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3, '\0', false },
422   { {"opteron-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3, '\0', false },
423   { {"amdfam10"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10, '\0', false },
424   { {"barcelona"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10, '\0', false },
425   // Bobcat architecture processors.
426   { {"btver1"}, CK_BTVER1, FEATURE_SSE4_A, FeaturesBTVER1, '\0', false },
427   { {"btver2"}, CK_BTVER2, FEATURE_BMI, FeaturesBTVER2, '\0', false },
428   // Bulldozer architecture processors.
429   { {"bdver1"}, CK_BDVER1, FEATURE_XOP, FeaturesBDVER1, '\0', false },
430   { {"bdver2"}, CK_BDVER2, FEATURE_FMA, FeaturesBDVER2, '\0', false },
431   { {"bdver3"}, CK_BDVER3, FEATURE_FMA, FeaturesBDVER3, '\0', false },
432   { {"bdver4"}, CK_BDVER4, FEATURE_AVX2, FeaturesBDVER4, '\0', false },
433   // Zen architecture processors.
434   { {"znver1"}, CK_ZNVER1, FEATURE_AVX2, FeaturesZNVER1, '\0', false },
435   { {"znver2"}, CK_ZNVER2, FEATURE_AVX2, FeaturesZNVER2, '\0', false },
436   { {"znver3"}, CK_ZNVER3, FEATURE_AVX2, FeaturesZNVER3, '\0', false },
437   { {"znver4"}, CK_ZNVER4, FEATURE_AVX512VBMI2, FeaturesZNVER4, '\0', false },
438   { {"znver5"}, CK_ZNVER5, FEATURE_AVX512VP2INTERSECT, FeaturesZNVER5, '\0', false },
439   // Generic 64-bit processor.
440   { {"x86-64"}, CK_x86_64, FEATURE_SSE2 , FeaturesX86_64, '\0', false },
441   { {"x86-64-v2"}, CK_x86_64_v2, FEATURE_SSE4_2 , FeaturesX86_64_V2, '\0', false },
442   { {"x86-64-v3"}, CK_x86_64_v3, FEATURE_AVX2, FeaturesX86_64_V3, '\0', false },
443   { {"x86-64-v4"}, CK_x86_64_v4, FEATURE_AVX512VL, FeaturesX86_64_V4, '\0', false },
444   // Geode processors.
445   { {"geode"}, CK_Geode, ~0U, FeaturesGeode, '\0', false },
446 };
447 // clang-format on
448 
449 constexpr const char *NoTuneList[] = {"x86-64-v2", "x86-64-v3", "x86-64-v4"};
450 
parseArchX86(StringRef CPU,bool Only64Bit)451 X86::CPUKind llvm::X86::parseArchX86(StringRef CPU, bool Only64Bit) {
452   for (const auto &P : Processors)
453     if (!P.OnlyForCPUDispatchSpecific && P.Name == CPU &&
454         (P.Features[FEATURE_64BIT] || !Only64Bit))
455       return P.Kind;
456 
457   return CK_None;
458 }
459 
parseTuneCPU(StringRef CPU,bool Only64Bit)460 X86::CPUKind llvm::X86::parseTuneCPU(StringRef CPU, bool Only64Bit) {
461   if (llvm::is_contained(NoTuneList, CPU))
462     return CK_None;
463   return parseArchX86(CPU, Only64Bit);
464 }
465 
fillValidCPUArchList(SmallVectorImpl<StringRef> & Values,bool Only64Bit)466 void llvm::X86::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values,
467                                      bool Only64Bit) {
468   for (const auto &P : Processors)
469     if (!P.OnlyForCPUDispatchSpecific && !P.Name.empty() &&
470         (P.Features[FEATURE_64BIT] || !Only64Bit))
471       Values.emplace_back(P.Name);
472 }
473 
fillValidTuneCPUList(SmallVectorImpl<StringRef> & Values,bool Only64Bit)474 void llvm::X86::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values,
475                                      bool Only64Bit) {
476   for (const ProcInfo &P : Processors)
477     if (!P.OnlyForCPUDispatchSpecific && !P.Name.empty() &&
478         (P.Features[FEATURE_64BIT] || !Only64Bit) &&
479         !llvm::is_contained(NoTuneList, P.Name))
480       Values.emplace_back(P.Name);
481 }
482 
getKeyFeature(X86::CPUKind Kind)483 ProcessorFeatures llvm::X86::getKeyFeature(X86::CPUKind Kind) {
484   // FIXME: Can we avoid a linear search here? The table might be sorted by
485   // CPUKind so we could binary search?
486   for (const auto &P : Processors) {
487     if (P.Kind == Kind) {
488       assert(P.KeyFeature != ~0U && "Processor does not have a key feature.");
489       return static_cast<ProcessorFeatures>(P.KeyFeature);
490     }
491   }
492 
493   llvm_unreachable("Unable to find CPU kind!");
494 }
495 
496 // Features with no dependencies.
497 constexpr FeatureBitset ImpliedFeatures64BIT = {};
498 constexpr FeatureBitset ImpliedFeaturesADX = {};
499 constexpr FeatureBitset ImpliedFeaturesBMI = {};
500 constexpr FeatureBitset ImpliedFeaturesBMI2 = {};
501 constexpr FeatureBitset ImpliedFeaturesCLDEMOTE = {};
502 constexpr FeatureBitset ImpliedFeaturesCLFLUSHOPT = {};
503 constexpr FeatureBitset ImpliedFeaturesCLWB = {};
504 constexpr FeatureBitset ImpliedFeaturesCLZERO = {};
505 constexpr FeatureBitset ImpliedFeaturesCMOV = {};
506 constexpr FeatureBitset ImpliedFeaturesCMPXCHG16B = {};
507 constexpr FeatureBitset ImpliedFeaturesCMPXCHG8B = {};
508 constexpr FeatureBitset ImpliedFeaturesCRC32 = {};
509 constexpr FeatureBitset ImpliedFeaturesENQCMD = {};
510 constexpr FeatureBitset ImpliedFeaturesFSGSBASE = {};
511 constexpr FeatureBitset ImpliedFeaturesFXSR = {};
512 constexpr FeatureBitset ImpliedFeaturesINVPCID = {};
513 constexpr FeatureBitset ImpliedFeaturesLWP = {};
514 constexpr FeatureBitset ImpliedFeaturesLZCNT = {};
515 constexpr FeatureBitset ImpliedFeaturesMMX = {};
516 constexpr FeatureBitset ImpliedFeaturesMWAITX = {};
517 constexpr FeatureBitset ImpliedFeaturesMOVBE = {};
518 constexpr FeatureBitset ImpliedFeaturesMOVDIR64B = {};
519 constexpr FeatureBitset ImpliedFeaturesMOVDIRI = {};
520 constexpr FeatureBitset ImpliedFeaturesPCONFIG = {};
521 constexpr FeatureBitset ImpliedFeaturesPOPCNT = {};
522 constexpr FeatureBitset ImpliedFeaturesPKU = {};
523 constexpr FeatureBitset ImpliedFeaturesPRFCHW = {};
524 constexpr FeatureBitset ImpliedFeaturesPTWRITE = {};
525 constexpr FeatureBitset ImpliedFeaturesRDPID = {};
526 constexpr FeatureBitset ImpliedFeaturesRDPRU = {};
527 constexpr FeatureBitset ImpliedFeaturesRDRND = {};
528 constexpr FeatureBitset ImpliedFeaturesRDSEED = {};
529 constexpr FeatureBitset ImpliedFeaturesRTM = {};
530 constexpr FeatureBitset ImpliedFeaturesSAHF = {};
531 constexpr FeatureBitset ImpliedFeaturesSERIALIZE = {};
532 constexpr FeatureBitset ImpliedFeaturesSGX = {};
533 constexpr FeatureBitset ImpliedFeaturesSHSTK = {};
534 constexpr FeatureBitset ImpliedFeaturesTBM = {};
535 constexpr FeatureBitset ImpliedFeaturesTSXLDTRK = {};
536 constexpr FeatureBitset ImpliedFeaturesUINTR = {};
537 constexpr FeatureBitset ImpliedFeaturesUSERMSR = {};
538 constexpr FeatureBitset ImpliedFeaturesWAITPKG = {};
539 constexpr FeatureBitset ImpliedFeaturesWBNOINVD = {};
540 constexpr FeatureBitset ImpliedFeaturesVZEROUPPER = {};
541 constexpr FeatureBitset ImpliedFeaturesX87 = {};
542 constexpr FeatureBitset ImpliedFeaturesXSAVE = {};
543 constexpr FeatureBitset ImpliedFeaturesDUMMYFEATURE1 = {};
544 constexpr FeatureBitset ImpliedFeaturesDUMMYFEATURE2 = {};
545 
546 // Not really CPU features, but need to be in the table because clang uses
547 // target features to communicate them to the backend.
548 constexpr FeatureBitset ImpliedFeaturesRETPOLINE_EXTERNAL_THUNK = {};
549 constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_BRANCHES = {};
550 constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_CALLS = {};
551 constexpr FeatureBitset ImpliedFeaturesLVI_CFI = {};
552 constexpr FeatureBitset ImpliedFeaturesLVI_LOAD_HARDENING = {};
553 
554 // XSAVE features are dependent on basic XSAVE.
555 constexpr FeatureBitset ImpliedFeaturesXSAVEC = FeatureXSAVE;
556 constexpr FeatureBitset ImpliedFeaturesXSAVEOPT = FeatureXSAVE;
557 constexpr FeatureBitset ImpliedFeaturesXSAVES = FeatureXSAVE;
558 
559 // SSE/AVX/AVX512F chain.
560 constexpr FeatureBitset ImpliedFeaturesSSE = {};
561 constexpr FeatureBitset ImpliedFeaturesSSE2 = FeatureSSE;
562 constexpr FeatureBitset ImpliedFeaturesSSE3 = FeatureSSE2;
563 constexpr FeatureBitset ImpliedFeaturesSSSE3 = FeatureSSE3;
564 constexpr FeatureBitset ImpliedFeaturesSSE4_1 = FeatureSSSE3;
565 constexpr FeatureBitset ImpliedFeaturesSSE4_2 = FeatureSSE4_1;
566 constexpr FeatureBitset ImpliedFeaturesAVX = FeatureSSE4_2;
567 constexpr FeatureBitset ImpliedFeaturesAVX2 = FeatureAVX;
568 constexpr FeatureBitset ImpliedFeaturesEVEX512 = {};
569 constexpr FeatureBitset ImpliedFeaturesAVX512F =
570     FeatureAVX2 | FeatureF16C | FeatureFMA;
571 
572 // Vector extensions that build on SSE or AVX.
573 constexpr FeatureBitset ImpliedFeaturesAES = FeatureSSE2;
574 constexpr FeatureBitset ImpliedFeaturesF16C = FeatureAVX;
575 constexpr FeatureBitset ImpliedFeaturesFMA = FeatureAVX;
576 constexpr FeatureBitset ImpliedFeaturesGFNI = FeatureSSE2;
577 constexpr FeatureBitset ImpliedFeaturesPCLMUL = FeatureSSE2;
578 constexpr FeatureBitset ImpliedFeaturesSHA = FeatureSSE2;
579 constexpr FeatureBitset ImpliedFeaturesVAES = FeatureAES | FeatureAVX2;
580 constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ = FeatureAVX | FeaturePCLMUL;
581 constexpr FeatureBitset ImpliedFeaturesSM3 = FeatureAVX;
582 constexpr FeatureBitset ImpliedFeaturesSM4 = FeatureAVX2;
583 
584 // AVX512 features.
585 constexpr FeatureBitset ImpliedFeaturesAVX512CD = FeatureAVX512F;
586 constexpr FeatureBitset ImpliedFeaturesAVX512BW = FeatureAVX512F;
587 constexpr FeatureBitset ImpliedFeaturesAVX512DQ = FeatureAVX512F;
588 constexpr FeatureBitset ImpliedFeaturesAVX512VL = FeatureAVX512F;
589 
590 constexpr FeatureBitset ImpliedFeaturesAVX512BF16 = FeatureAVX512BW;
591 constexpr FeatureBitset ImpliedFeaturesAVX512BITALG = FeatureAVX512BW;
592 constexpr FeatureBitset ImpliedFeaturesAVX512IFMA = FeatureAVX512F;
593 constexpr FeatureBitset ImpliedFeaturesAVX512VNNI = FeatureAVX512F;
594 constexpr FeatureBitset ImpliedFeaturesAVX512VPOPCNTDQ = FeatureAVX512F;
595 constexpr FeatureBitset ImpliedFeaturesAVX512VBMI = FeatureAVX512BW;
596 constexpr FeatureBitset ImpliedFeaturesAVX512VBMI2 = FeatureAVX512BW;
597 constexpr FeatureBitset ImpliedFeaturesAVX512VP2INTERSECT = FeatureAVX512F;
598 
599 // FIXME: These two aren't really implemented and just exist in the feature
600 // list for __builtin_cpu_supports. So omit their dependencies.
601 constexpr FeatureBitset ImpliedFeaturesAVX5124FMAPS = {};
602 constexpr FeatureBitset ImpliedFeaturesAVX5124VNNIW = {};
603 
604 // SSE4_A->FMA4->XOP chain.
605 constexpr FeatureBitset ImpliedFeaturesSSE4_A = FeatureSSE3;
606 constexpr FeatureBitset ImpliedFeaturesFMA4 = FeatureAVX | FeatureSSE4_A;
607 constexpr FeatureBitset ImpliedFeaturesXOP = FeatureFMA4;
608 
609 // AMX Features
610 constexpr FeatureBitset ImpliedFeaturesAMX_TILE = {};
611 constexpr FeatureBitset ImpliedFeaturesAMX_BF16 = FeatureAMX_TILE;
612 constexpr FeatureBitset ImpliedFeaturesAMX_FP16 = FeatureAMX_TILE;
613 constexpr FeatureBitset ImpliedFeaturesAMX_INT8 = FeatureAMX_TILE;
614 constexpr FeatureBitset ImpliedFeaturesAMX_COMPLEX = FeatureAMX_TILE;
615 constexpr FeatureBitset ImpliedFeaturesAMX_FP8 = FeatureAMX_TILE;
616 constexpr FeatureBitset ImpliedFeaturesAMX_TRANSPOSE = FeatureAMX_TILE;
617 constexpr FeatureBitset ImpliedFeaturesAMX_MOVRS = FeatureAMX_TILE;
618 constexpr FeatureBitset ImpliedFeaturesAMX_AVX512 =
619     FeatureAMX_TILE | FeatureAVX10_2_512;
620 constexpr FeatureBitset ImpliedFeaturesAMX_TF32 = FeatureAMX_TILE;
621 constexpr FeatureBitset ImpliedFeaturesHRESET = {};
622 
623 constexpr FeatureBitset ImpliedFeaturesPREFETCHI = {};
624 constexpr FeatureBitset ImpliedFeaturesCMPCCXADD = {};
625 constexpr FeatureBitset ImpliedFeaturesRAOINT = {};
626 constexpr FeatureBitset ImpliedFeaturesAVXVNNIINT16 = FeatureAVX2;
627 constexpr FeatureBitset ImpliedFeaturesAVXVNNIINT8 = FeatureAVX2;
628 constexpr FeatureBitset ImpliedFeaturesAVXIFMA = FeatureAVX2;
629 constexpr FeatureBitset ImpliedFeaturesAVXNECONVERT = FeatureAVX2;
630 constexpr FeatureBitset ImpliedFeaturesSHA512 = FeatureAVX2;
631 constexpr FeatureBitset ImpliedFeaturesAVX512FP16 = FeatureAVX512BW;
632 // Key Locker Features
633 constexpr FeatureBitset ImpliedFeaturesKL = FeatureSSE2;
634 constexpr FeatureBitset ImpliedFeaturesWIDEKL = FeatureKL;
635 
636 // AVXVNNI Features
637 constexpr FeatureBitset ImpliedFeaturesAVXVNNI = FeatureAVX2;
638 
639 // AVX10 Features
640 constexpr FeatureBitset ImpliedFeaturesAVX10_1 =
641     FeatureAVX512CD | FeatureAVX512VBMI | FeatureAVX512IFMA |
642     FeatureAVX512VNNI | FeatureAVX512BF16 | FeatureAVX512VPOPCNTDQ |
643     FeatureAVX512VBMI2 | FeatureAVX512BITALG | FeatureAVX512FP16 |
644     FeatureAVX512DQ | FeatureAVX512VL;
645 constexpr FeatureBitset ImpliedFeaturesAVX10_1_512 =
646     FeatureAVX10_1 | FeatureEVEX512;
647 constexpr FeatureBitset ImpliedFeaturesAVX10_2 = FeatureAVX10_1;
648 constexpr FeatureBitset ImpliedFeaturesAVX10_2_512 =
649     FeatureAVX10_2 | FeatureAVX10_1_512;
650 
651 // APX Features
652 constexpr FeatureBitset ImpliedFeaturesEGPR = {};
653 constexpr FeatureBitset ImpliedFeaturesPush2Pop2 = {};
654 constexpr FeatureBitset ImpliedFeaturesPPX = {};
655 constexpr FeatureBitset ImpliedFeaturesNDD = {};
656 constexpr FeatureBitset ImpliedFeaturesCCMP = {};
657 constexpr FeatureBitset ImpliedFeaturesNF = {};
658 constexpr FeatureBitset ImpliedFeaturesCF = {};
659 constexpr FeatureBitset ImpliedFeaturesZU = {};
660 
661 constexpr FeatureBitset ImpliedFeaturesMOVRS = {};
662 
663 constexpr FeatureInfo FeatureInfos[X86::CPU_FEATURE_MAX] = {
664 #define X86_FEATURE(ENUM, STR) {{"+" STR}, ImpliedFeatures##ENUM},
665 #include "llvm/TargetParser/X86TargetParser.def"
666 };
667 
getFeaturesForCPU(StringRef CPU,SmallVectorImpl<StringRef> & EnabledFeatures,bool NeedPlus)668 void llvm::X86::getFeaturesForCPU(StringRef CPU,
669                                   SmallVectorImpl<StringRef> &EnabledFeatures,
670                                   bool NeedPlus) {
671   auto I = llvm::find_if(Processors,
672                          [&](const ProcInfo &P) { return P.Name == CPU; });
673   assert(I != std::end(Processors) && "Processor not found!");
674 
675   FeatureBitset Bits = I->Features;
676 
677   // Remove the 64-bit feature which we only use to validate if a CPU can
678   // be used with 64-bit mode.
679   Bits &= ~Feature64BIT;
680 
681   // Add the string version of all set bits.
682   for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
683     if (Bits[i] && !FeatureInfos[i].getName(NeedPlus).empty())
684       EnabledFeatures.push_back(FeatureInfos[i].getName(NeedPlus));
685 }
686 
687 // For each feature that is (transitively) implied by this feature, set it.
getImpliedEnabledFeatures(FeatureBitset & Bits,const FeatureBitset & Implies)688 static void getImpliedEnabledFeatures(FeatureBitset &Bits,
689                                       const FeatureBitset &Implies) {
690   // Fast path: Implies is often empty.
691   if (!Implies.any())
692     return;
693   FeatureBitset Prev;
694   Bits |= Implies;
695   do {
696     Prev = Bits;
697     for (unsigned i = CPU_FEATURE_MAX; i;)
698       if (Bits[--i])
699         Bits |= FeatureInfos[i].ImpliedFeatures;
700   } while (Prev != Bits);
701 }
702 
703 /// Create bit vector of features that are implied disabled if the feature
704 /// passed in Value is disabled.
getImpliedDisabledFeatures(FeatureBitset & Bits,unsigned Value)705 static void getImpliedDisabledFeatures(FeatureBitset &Bits, unsigned Value) {
706   // Check all features looking for any dependent on this feature. If we find
707   // one, mark it and recursively find any feature that depend on it.
708   FeatureBitset Prev;
709   Bits.set(Value);
710   do {
711     Prev = Bits;
712     for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
713       if ((FeatureInfos[i].ImpliedFeatures & Bits).any())
714         Bits.set(i);
715   } while (Prev != Bits);
716 }
717 
updateImpliedFeatures(StringRef Feature,bool Enabled,StringMap<bool> & Features)718 void llvm::X86::updateImpliedFeatures(
719     StringRef Feature, bool Enabled,
720     StringMap<bool> &Features) {
721   auto I = llvm::find_if(FeatureInfos, [&](const FeatureInfo &FI) {
722     return FI.getName() == Feature;
723   });
724   if (I == std::end(FeatureInfos)) {
725     // FIXME: This shouldn't happen, but may not have all features in the table
726     // yet.
727     return;
728   }
729 
730   FeatureBitset ImpliedBits;
731   if (Enabled)
732     getImpliedEnabledFeatures(ImpliedBits, I->ImpliedFeatures);
733   else
734     getImpliedDisabledFeatures(ImpliedBits,
735                                std::distance(std::begin(FeatureInfos), I));
736 
737   // Update the map entry for all implied features.
738   for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
739     if (ImpliedBits[i] && !FeatureInfos[i].getName().empty())
740       Features[FeatureInfos[i].getName()] = Enabled;
741 }
742 
getCPUDispatchMangling(StringRef CPU)743 char llvm::X86::getCPUDispatchMangling(StringRef CPU) {
744   auto I = llvm::find_if(Processors,
745                          [&](const ProcInfo &P) { return P.Name == CPU; });
746   assert(I != std::end(Processors) && "Processor not found!");
747   assert(I->Mangling != '\0' && "Processor dooesn't support function multiversion!");
748   return I->Mangling;
749 }
750 
validateCPUSpecificCPUDispatch(StringRef Name)751 bool llvm::X86::validateCPUSpecificCPUDispatch(StringRef Name) {
752   auto I = llvm::find_if(Processors,
753                          [&](const ProcInfo &P) { return P.Name == Name; });
754   return I != std::end(Processors);
755 }
756 
757 std::array<uint32_t, 4>
getCpuSupportsMask(ArrayRef<StringRef> FeatureStrs)758 llvm::X86::getCpuSupportsMask(ArrayRef<StringRef> FeatureStrs) {
759   // Processor features and mapping to processor feature value.
760   std::array<uint32_t, 4> FeatureMask{};
761   for (StringRef FeatureStr : FeatureStrs) {
762     unsigned Feature = StringSwitch<unsigned>(FeatureStr)
763 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY)                                \
764   .Case(STR, llvm::X86::FEATURE_##ENUM)
765 #define X86_MICROARCH_LEVEL(ENUM, STR, PRIORITY)                               \
766   .Case(STR, llvm::X86::FEATURE_##ENUM)
767 #include "llvm/TargetParser/X86TargetParser.def"
768         ;
769     assert(Feature / 32 < FeatureMask.size());
770     FeatureMask[Feature / 32] |= 1U << (Feature % 32);
771   }
772   return FeatureMask;
773 }
774 
getFeaturePriority(ProcessorFeatures Feat)775 unsigned llvm::X86::getFeaturePriority(ProcessorFeatures Feat) {
776 #ifndef NDEBUG
777   // Check that priorities are set properly in the .def file. We expect that
778   // "compat" features are assigned non-duplicate consecutive priorities
779   // starting from one (1, ..., 37) and multiple zeros.
780 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) PRIORITY,
781   unsigned Priorities[] = {
782 #include "llvm/TargetParser/X86TargetParser.def"
783   };
784   std::array<unsigned, std::size(Priorities)> HelperList;
785   const size_t MaxPriority = 37;
786   std::iota(HelperList.begin(), HelperList.begin() + MaxPriority + 1, 0);
787   for (size_t i = MaxPriority + 1; i != std::size(Priorities); ++i)
788     HelperList[i] = 0;
789   assert(std::is_permutation(HelperList.begin(), HelperList.end(),
790                              std::begin(Priorities), std::end(Priorities)) &&
791          "Priorities don't form consecutive range!");
792 #endif
793 
794   switch (Feat) {
795 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY)                                \
796   case X86::FEATURE_##ENUM:                                                    \
797     return PRIORITY;
798 #include "llvm/TargetParser/X86TargetParser.def"
799   default:
800     llvm_unreachable("No Feature Priority for non-CPUSupports Features");
801   }
802 }
803