1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2012-2014, 2018-2022, 2024 Intel Corporation 4 * Copyright (C) 2017 Intel Deutschland GmbH 5 */ 6 #ifndef __iwl_fw_api_rs_h__ 7 #define __iwl_fw_api_rs_h__ 8 9 #include "mac.h" 10 11 /** 12 * enum iwl_tlc_mng_cfg_flags - options for TLC config flags 13 * @IWL_TLC_MNG_CFG_FLAGS_STBC_MSK: enable STBC. For HE this enables STBC for 14 * bandwidths <= 80MHz 15 * @IWL_TLC_MNG_CFG_FLAGS_LDPC_MSK: enable LDPC 16 * @IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK: enable STBC in HE at 160MHz 17 * bandwidth 18 * @IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_1_MSK: enable HE Dual Carrier Modulation 19 * for BPSK (MCS 0) with 1 spatial 20 * stream 21 * @IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_2_MSK: enable HE Dual Carrier Modulation 22 * for BPSK (MCS 0) with 2 spatial 23 * streams 24 * @IWL_TLC_MNG_CFG_FLAGS_EHT_EXTRA_LTF_MSK: enable support for EHT extra LTF 25 */ 26 enum iwl_tlc_mng_cfg_flags { 27 IWL_TLC_MNG_CFG_FLAGS_STBC_MSK = BIT(0), 28 IWL_TLC_MNG_CFG_FLAGS_LDPC_MSK = BIT(1), 29 IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK = BIT(2), 30 IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_1_MSK = BIT(3), 31 IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_2_MSK = BIT(4), 32 IWL_TLC_MNG_CFG_FLAGS_EHT_EXTRA_LTF_MSK = BIT(6), 33 }; 34 35 /** 36 * enum iwl_tlc_mng_cfg_cw - channel width options 37 * @IWL_TLC_MNG_CH_WIDTH_20MHZ: 20MHZ channel 38 * @IWL_TLC_MNG_CH_WIDTH_40MHZ: 40MHZ channel 39 * @IWL_TLC_MNG_CH_WIDTH_80MHZ: 80MHZ channel 40 * @IWL_TLC_MNG_CH_WIDTH_160MHZ: 160MHZ channel 41 * @IWL_TLC_MNG_CH_WIDTH_320MHZ: 320MHZ channel 42 */ 43 enum iwl_tlc_mng_cfg_cw { 44 IWL_TLC_MNG_CH_WIDTH_20MHZ, 45 IWL_TLC_MNG_CH_WIDTH_40MHZ, 46 IWL_TLC_MNG_CH_WIDTH_80MHZ, 47 IWL_TLC_MNG_CH_WIDTH_160MHZ, 48 IWL_TLC_MNG_CH_WIDTH_320MHZ, 49 }; 50 51 /** 52 * enum iwl_tlc_mng_cfg_chains - possible chains 53 * @IWL_TLC_MNG_CHAIN_A_MSK: chain A 54 * @IWL_TLC_MNG_CHAIN_B_MSK: chain B 55 */ 56 enum iwl_tlc_mng_cfg_chains { 57 IWL_TLC_MNG_CHAIN_A_MSK = BIT(0), 58 IWL_TLC_MNG_CHAIN_B_MSK = BIT(1), 59 }; 60 61 /** 62 * enum iwl_tlc_mng_cfg_mode - supported modes 63 * @IWL_TLC_MNG_MODE_CCK: enable CCK 64 * @IWL_TLC_MNG_MODE_OFDM_NON_HT: enable OFDM (non HT) 65 * @IWL_TLC_MNG_MODE_NON_HT: enable non HT 66 * @IWL_TLC_MNG_MODE_HT: enable HT 67 * @IWL_TLC_MNG_MODE_VHT: enable VHT 68 * @IWL_TLC_MNG_MODE_HE: enable HE 69 * @IWL_TLC_MNG_MODE_EHT: enable EHT 70 */ 71 enum iwl_tlc_mng_cfg_mode { 72 IWL_TLC_MNG_MODE_CCK = 0, 73 IWL_TLC_MNG_MODE_OFDM_NON_HT = IWL_TLC_MNG_MODE_CCK, 74 IWL_TLC_MNG_MODE_NON_HT = IWL_TLC_MNG_MODE_CCK, 75 IWL_TLC_MNG_MODE_HT, 76 IWL_TLC_MNG_MODE_VHT, 77 IWL_TLC_MNG_MODE_HE, 78 IWL_TLC_MNG_MODE_EHT, 79 }; 80 81 /** 82 * enum iwl_tlc_mng_ht_rates - HT/VHT/HE rates 83 * @IWL_TLC_MNG_HT_RATE_MCS0: index of MCS0 84 * @IWL_TLC_MNG_HT_RATE_MCS1: index of MCS1 85 * @IWL_TLC_MNG_HT_RATE_MCS2: index of MCS2 86 * @IWL_TLC_MNG_HT_RATE_MCS3: index of MCS3 87 * @IWL_TLC_MNG_HT_RATE_MCS4: index of MCS4 88 * @IWL_TLC_MNG_HT_RATE_MCS5: index of MCS5 89 * @IWL_TLC_MNG_HT_RATE_MCS6: index of MCS6 90 * @IWL_TLC_MNG_HT_RATE_MCS7: index of MCS7 91 * @IWL_TLC_MNG_HT_RATE_MCS8: index of MCS8 92 * @IWL_TLC_MNG_HT_RATE_MCS9: index of MCS9 93 * @IWL_TLC_MNG_HT_RATE_MCS10: index of MCS10 94 * @IWL_TLC_MNG_HT_RATE_MCS11: index of MCS11 95 * @IWL_TLC_MNG_HT_RATE_MAX: maximal rate for HT/VHT 96 */ 97 enum iwl_tlc_mng_ht_rates { 98 IWL_TLC_MNG_HT_RATE_MCS0 = 0, 99 IWL_TLC_MNG_HT_RATE_MCS1, 100 IWL_TLC_MNG_HT_RATE_MCS2, 101 IWL_TLC_MNG_HT_RATE_MCS3, 102 IWL_TLC_MNG_HT_RATE_MCS4, 103 IWL_TLC_MNG_HT_RATE_MCS5, 104 IWL_TLC_MNG_HT_RATE_MCS6, 105 IWL_TLC_MNG_HT_RATE_MCS7, 106 IWL_TLC_MNG_HT_RATE_MCS8, 107 IWL_TLC_MNG_HT_RATE_MCS9, 108 IWL_TLC_MNG_HT_RATE_MCS10, 109 IWL_TLC_MNG_HT_RATE_MCS11, 110 IWL_TLC_MNG_HT_RATE_MAX = IWL_TLC_MNG_HT_RATE_MCS11, 111 }; 112 113 enum IWL_TLC_MNG_NSS { 114 IWL_TLC_NSS_1, 115 IWL_TLC_NSS_2, 116 IWL_TLC_NSS_MAX 117 }; 118 119 /** 120 * enum IWL_TLC_MCS_PER_BW - mcs index per BW 121 * @IWL_TLC_MCS_PER_BW_80: mcs for bw - 20Hhz, 40Hhz, 80Hhz 122 * @IWL_TLC_MCS_PER_BW_160: mcs for bw - 160Mhz 123 * @IWL_TLC_MCS_PER_BW_320: mcs for bw - 320Mhz 124 * @IWL_TLC_MCS_PER_BW_NUM_V3: number of entries up to version 3 125 * @IWL_TLC_MCS_PER_BW_NUM_V4: number of entries from version 4 126 */ 127 enum IWL_TLC_MCS_PER_BW { 128 IWL_TLC_MCS_PER_BW_80, 129 IWL_TLC_MCS_PER_BW_160, 130 IWL_TLC_MCS_PER_BW_320, 131 IWL_TLC_MCS_PER_BW_NUM_V3 = IWL_TLC_MCS_PER_BW_160 + 1, 132 IWL_TLC_MCS_PER_BW_NUM_V4 = IWL_TLC_MCS_PER_BW_320 + 1, 133 }; 134 135 /** 136 * struct iwl_tlc_config_cmd_v3 - TLC configuration 137 * @sta_id: station id 138 * @reserved1: reserved 139 * @max_ch_width: max supported channel width from @enum iwl_tlc_mng_cfg_cw 140 * @mode: &enum iwl_tlc_mng_cfg_mode 141 * @chains: bitmask of &enum iwl_tlc_mng_cfg_chains 142 * @amsdu: TX amsdu is supported 143 * @flags: bitmask of &enum iwl_tlc_mng_cfg_flags 144 * @non_ht_rates: bitmap of supported legacy rates 145 * @ht_rates: bitmap of &enum iwl_tlc_mng_ht_rates, per &enum IWL_TLC_MCS_PER_BW 146 * <nss, channel-width> pair (0 - 80mhz width and below, 1 - 160mhz). 147 * @max_mpdu_len: max MPDU length, in bytes 148 * @sgi_ch_width_supp: bitmap of SGI support per channel width 149 * use BIT(@enum iwl_tlc_mng_cfg_cw) 150 * @reserved2: reserved 151 * @max_tx_op: max TXOP in uSecs for all AC (BK, BE, VO, VI), 152 * set zero for no limit. 153 */ 154 struct iwl_tlc_config_cmd_v3 { 155 u8 sta_id; 156 u8 reserved1[3]; 157 u8 max_ch_width; 158 u8 mode; 159 u8 chains; 160 u8 amsdu; 161 __le16 flags; 162 __le16 non_ht_rates; 163 __le16 ht_rates[IWL_TLC_NSS_MAX][IWL_TLC_MCS_PER_BW_NUM_V3]; 164 __le16 max_mpdu_len; 165 u8 sgi_ch_width_supp; 166 u8 reserved2; 167 __le32 max_tx_op; 168 } __packed; /* TLC_MNG_CONFIG_CMD_API_S_VER_3 */ 169 170 /** 171 * struct iwl_tlc_config_cmd_v4 - TLC configuration 172 * @sta_id: station id 173 * @reserved1: reserved 174 * @max_ch_width: max supported channel width from &enum iwl_tlc_mng_cfg_cw 175 * @mode: &enum iwl_tlc_mng_cfg_mode 176 * @chains: bitmask of &enum iwl_tlc_mng_cfg_chains 177 * @sgi_ch_width_supp: bitmap of SGI support per channel width 178 * use BIT(&enum iwl_tlc_mng_cfg_cw) 179 * @flags: bitmask of &enum iwl_tlc_mng_cfg_flags 180 * @non_ht_rates: bitmap of supported legacy rates 181 * @ht_rates: bitmap of &enum iwl_tlc_mng_ht_rates, per <nss, channel-width> 182 * pair (0 - 80mhz width and below, 1 - 160mhz, 2 - 320mhz). 183 * @max_mpdu_len: max MPDU length, in bytes 184 * @max_tx_op: max TXOP in uSecs for all AC (BK, BE, VO, VI), 185 * set zero for no limit. 186 */ 187 struct iwl_tlc_config_cmd_v4 { 188 u8 sta_id; 189 u8 reserved1[3]; 190 u8 max_ch_width; 191 u8 mode; 192 u8 chains; 193 u8 sgi_ch_width_supp; 194 __le16 flags; 195 __le16 non_ht_rates; 196 __le16 ht_rates[IWL_TLC_NSS_MAX][IWL_TLC_MCS_PER_BW_NUM_V4]; 197 __le16 max_mpdu_len; 198 __le16 max_tx_op; 199 } __packed; /* TLC_MNG_CONFIG_CMD_API_S_VER_4 */ 200 201 /** 202 * enum iwl_tlc_update_flags - updated fields 203 * @IWL_TLC_NOTIF_FLAG_RATE: last initial rate update 204 * @IWL_TLC_NOTIF_FLAG_AMSDU: umsdu parameters update 205 */ 206 enum iwl_tlc_update_flags { 207 IWL_TLC_NOTIF_FLAG_RATE = BIT(0), 208 IWL_TLC_NOTIF_FLAG_AMSDU = BIT(1), 209 }; 210 211 /** 212 * struct iwl_tlc_update_notif - TLC notification from FW 213 * @sta_id: station id 214 * @reserved: reserved 215 * @flags: bitmap of notifications reported 216 * @rate: current initial rate 217 * @amsdu_size: Max AMSDU size, in bytes 218 * @amsdu_enabled: bitmap for per-TID AMSDU enablement 219 */ 220 struct iwl_tlc_update_notif { 221 u8 sta_id; 222 u8 reserved[3]; 223 __le32 flags; 224 __le32 rate; 225 __le32 amsdu_size; 226 __le32 amsdu_enabled; 227 } __packed; /* TLC_MNG_UPDATE_NTFY_API_S_VER_2 */ 228 229 /** 230 * enum iwl_tlc_debug_types - debug options 231 */ 232 enum iwl_tlc_debug_types { 233 /** 234 * @IWL_TLC_DEBUG_FIXED_RATE: set fixed rate for rate scaling 235 */ 236 IWL_TLC_DEBUG_FIXED_RATE, 237 /** 238 * @IWL_TLC_DEBUG_AGG_DURATION_LIM: time limit for a BA 239 * session, in usec 240 */ 241 IWL_TLC_DEBUG_AGG_DURATION_LIM, 242 /** 243 * @IWL_TLC_DEBUG_AGG_FRAME_CNT_LIM: set max number of frames 244 * in an aggregation 245 */ 246 IWL_TLC_DEBUG_AGG_FRAME_CNT_LIM, 247 /** 248 * @IWL_TLC_DEBUG_TPC_ENABLED: enable or disable tpc 249 */ 250 IWL_TLC_DEBUG_TPC_ENABLED, 251 /** 252 * @IWL_TLC_DEBUG_TPC_STATS: get number of frames Tx'ed in each 253 * tpc step 254 */ 255 IWL_TLC_DEBUG_TPC_STATS, 256 /** 257 * @IWL_TLC_DEBUG_RTS_DISABLE: disable RTS (bool true/false). 258 */ 259 IWL_TLC_DEBUG_RTS_DISABLE, 260 /** 261 * @IWL_TLC_DEBUG_PARTIAL_FIXED_RATE: set partial fixed rate to fw 262 */ 263 IWL_TLC_DEBUG_PARTIAL_FIXED_RATE, 264 }; /* TLC_MNG_DEBUG_TYPES_API_E */ 265 266 #define MAX_DATA_IN_DHC_TLC_CMD 10 267 268 /** 269 * struct iwl_dhc_tlc_cmd - fixed debug config 270 * @sta_id: bit 0 - enable/disable, bits 1 - 7 hold station id 271 * @reserved1: reserved 272 * @type: type id of %enum iwl_tlc_debug_types 273 * @data: data to send 274 */ 275 struct iwl_dhc_tlc_cmd { 276 u8 sta_id; 277 u8 reserved1[3]; 278 __le32 type; 279 __le32 data[MAX_DATA_IN_DHC_TLC_CMD]; 280 } __packed; /* TLC_MNG_DEBUG_CMD_S */ 281 282 #define IWL_MAX_MCS_DISPLAY_SIZE 12 283 284 struct iwl_rate_mcs_info { 285 char mbps[IWL_MAX_MCS_DISPLAY_SIZE]; 286 char mcs[IWL_MAX_MCS_DISPLAY_SIZE]; 287 }; 288 289 /* 290 * These serve as indexes into 291 * struct iwl_rate_info fw_rate_idx_to_plcp[IWL_RATE_COUNT]; 292 * TODO: avoid overlap between legacy and HT rates 293 */ 294 enum { 295 IWL_RATE_1M_INDEX = 0, 296 IWL_FIRST_CCK_RATE = IWL_RATE_1M_INDEX, 297 IWL_RATE_2M_INDEX, 298 IWL_RATE_5M_INDEX, 299 IWL_RATE_11M_INDEX, 300 IWL_LAST_CCK_RATE = IWL_RATE_11M_INDEX, 301 IWL_RATE_6M_INDEX, 302 IWL_FIRST_OFDM_RATE = IWL_RATE_6M_INDEX, 303 IWL_RATE_MCS_0_INDEX = IWL_RATE_6M_INDEX, 304 IWL_FIRST_HT_RATE = IWL_RATE_MCS_0_INDEX, 305 IWL_FIRST_VHT_RATE = IWL_RATE_MCS_0_INDEX, 306 IWL_RATE_9M_INDEX, 307 IWL_RATE_12M_INDEX, 308 IWL_RATE_MCS_1_INDEX = IWL_RATE_12M_INDEX, 309 IWL_RATE_18M_INDEX, 310 IWL_RATE_MCS_2_INDEX = IWL_RATE_18M_INDEX, 311 IWL_RATE_24M_INDEX, 312 IWL_RATE_MCS_3_INDEX = IWL_RATE_24M_INDEX, 313 IWL_RATE_36M_INDEX, 314 IWL_RATE_MCS_4_INDEX = IWL_RATE_36M_INDEX, 315 IWL_RATE_48M_INDEX, 316 IWL_RATE_MCS_5_INDEX = IWL_RATE_48M_INDEX, 317 IWL_RATE_54M_INDEX, 318 IWL_RATE_MCS_6_INDEX = IWL_RATE_54M_INDEX, 319 IWL_LAST_NON_HT_RATE = IWL_RATE_54M_INDEX, 320 IWL_RATE_60M_INDEX, 321 IWL_RATE_MCS_7_INDEX = IWL_RATE_60M_INDEX, 322 IWL_LAST_HT_RATE = IWL_RATE_MCS_7_INDEX, 323 IWL_RATE_MCS_8_INDEX, 324 IWL_RATE_MCS_9_INDEX, 325 IWL_LAST_VHT_RATE = IWL_RATE_MCS_9_INDEX, 326 IWL_RATE_MCS_10_INDEX, 327 IWL_RATE_MCS_11_INDEX, 328 IWL_LAST_HE_RATE = IWL_RATE_MCS_11_INDEX, 329 IWL_RATE_COUNT_LEGACY = IWL_LAST_NON_HT_RATE + 1, 330 IWL_RATE_COUNT = IWL_LAST_HE_RATE + 1, 331 IWL_RATE_INVM_INDEX = IWL_RATE_COUNT, 332 IWL_RATE_INVALID = IWL_RATE_COUNT, 333 }; 334 335 #define IWL_RATE_BIT_MSK(r) BIT(IWL_RATE_##r##M_INDEX) 336 337 /* fw API values for legacy bit rates, both OFDM and CCK */ 338 enum { 339 IWL_RATE_6M_PLCP = 13, 340 IWL_RATE_9M_PLCP = 15, 341 IWL_RATE_12M_PLCP = 5, 342 IWL_RATE_18M_PLCP = 7, 343 IWL_RATE_24M_PLCP = 9, 344 IWL_RATE_36M_PLCP = 11, 345 IWL_RATE_48M_PLCP = 1, 346 IWL_RATE_54M_PLCP = 3, 347 IWL_RATE_1M_PLCP = 10, 348 IWL_RATE_2M_PLCP = 20, 349 IWL_RATE_5M_PLCP = 55, 350 IWL_RATE_11M_PLCP = 110, 351 IWL_RATE_INVM_PLCP = -1, 352 }; 353 354 /* 355 * rate_n_flags bit fields version 1 356 * 357 * The 32-bit value has different layouts in the low 8 bites depending on the 358 * format. There are three formats, HT, VHT and legacy (11abg, with subformats 359 * for CCK and OFDM). 360 * 361 * High-throughput (HT) rate format 362 * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM) 363 * Very High-throughput (VHT) rate format 364 * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM) 365 * Legacy OFDM rate format for bits 7:0 366 * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM) 367 * Legacy CCK rate format for bits 7:0: 368 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK) 369 */ 370 371 /* Bit 8: (1) HT format, (0) legacy or VHT format */ 372 #define RATE_MCS_HT_POS 8 373 #define RATE_MCS_HT_MSK_V1 BIT(RATE_MCS_HT_POS) 374 375 /* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */ 376 #define RATE_MCS_CCK_POS_V1 9 377 #define RATE_MCS_CCK_MSK_V1 BIT(RATE_MCS_CCK_POS_V1) 378 379 /* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */ 380 #define RATE_MCS_VHT_POS_V1 26 381 #define RATE_MCS_VHT_MSK_V1 BIT(RATE_MCS_VHT_POS_V1) 382 383 384 /* 385 * High-throughput (HT) rate format for bits 7:0 386 * 387 * 2-0: MCS rate base 388 * 0) 6 Mbps 389 * 1) 12 Mbps 390 * 2) 18 Mbps 391 * 3) 24 Mbps 392 * 4) 36 Mbps 393 * 5) 48 Mbps 394 * 6) 54 Mbps 395 * 7) 60 Mbps 396 * 4-3: 0) Single stream (SISO) 397 * 1) Dual stream (MIMO) 398 * 2) Triple stream (MIMO) 399 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data 400 * (bits 7-6 are zero) 401 * 402 * Together the low 5 bits work out to the MCS index because we don't 403 * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two 404 * streams and 16-23 have three streams. We could also support MCS 32 405 * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.) 406 */ 407 #define RATE_HT_MCS_RATE_CODE_MSK_V1 0x7 408 #define RATE_HT_MCS_NSS_POS_V1 3 409 #define RATE_HT_MCS_NSS_MSK_V1 (3 << RATE_HT_MCS_NSS_POS_V1) 410 #define RATE_HT_MCS_MIMO2_MSK BIT(RATE_HT_MCS_NSS_POS_V1) 411 412 /* Bit 10: (1) Use Green Field preamble */ 413 #define RATE_HT_MCS_GF_POS 10 414 #define RATE_HT_MCS_GF_MSK (1 << RATE_HT_MCS_GF_POS) 415 416 #define RATE_HT_MCS_INDEX_MSK_V1 0x3f 417 418 /* 419 * Very High-throughput (VHT) rate format for bits 7:0 420 * 421 * 3-0: VHT MCS (0-9) 422 * 5-4: number of streams - 1: 423 * 0) Single stream (SISO) 424 * 1) Dual stream (MIMO) 425 * 2) Triple stream (MIMO) 426 */ 427 428 /* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */ 429 #define RATE_VHT_MCS_RATE_CODE_MSK 0xf 430 431 /* 432 * Legacy OFDM rate format for bits 7:0 433 * 434 * 3-0: 0xD) 6 Mbps 435 * 0xF) 9 Mbps 436 * 0x5) 12 Mbps 437 * 0x7) 18 Mbps 438 * 0x9) 24 Mbps 439 * 0xB) 36 Mbps 440 * 0x1) 48 Mbps 441 * 0x3) 54 Mbps 442 * (bits 7-4 are 0) 443 * 444 * Legacy CCK rate format for bits 7:0: 445 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK): 446 * 447 * 6-0: 10) 1 Mbps 448 * 20) 2 Mbps 449 * 55) 5.5 Mbps 450 * 110) 11 Mbps 451 * (bit 7 is 0) 452 */ 453 #define RATE_LEGACY_RATE_MSK_V1 0xff 454 455 /* Bit 10 - OFDM HE */ 456 #define RATE_MCS_HE_POS_V1 10 457 #define RATE_MCS_HE_MSK_V1 BIT(RATE_MCS_HE_POS_V1) 458 459 /* 460 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz 461 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT 462 */ 463 #define RATE_MCS_CHAN_WIDTH_POS 11 464 #define RATE_MCS_CHAN_WIDTH_MSK_V1 (3 << RATE_MCS_CHAN_WIDTH_POS) 465 466 /* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */ 467 #define RATE_MCS_SGI_POS_V1 13 468 #define RATE_MCS_SGI_MSK_V1 BIT(RATE_MCS_SGI_POS_V1) 469 470 /* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */ 471 #define RATE_MCS_ANT_POS 14 472 #define RATE_MCS_ANT_A_MSK (1 << RATE_MCS_ANT_POS) 473 #define RATE_MCS_ANT_B_MSK (2 << RATE_MCS_ANT_POS) 474 #define RATE_MCS_ANT_AB_MSK (RATE_MCS_ANT_A_MSK | \ 475 RATE_MCS_ANT_B_MSK) 476 #define RATE_MCS_ANT_MSK RATE_MCS_ANT_AB_MSK 477 478 /* Bit 17: (0) SS, (1) SS*2 */ 479 #define RATE_MCS_STBC_POS 17 480 #define RATE_MCS_STBC_MSK BIT(RATE_MCS_STBC_POS) 481 482 /* Bit 18: OFDM-HE dual carrier mode */ 483 #define RATE_HE_DUAL_CARRIER_MODE 18 484 #define RATE_HE_DUAL_CARRIER_MODE_MSK BIT(RATE_HE_DUAL_CARRIER_MODE) 485 486 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on */ 487 #define RATE_MCS_BF_POS 19 488 #define RATE_MCS_BF_MSK (1 << RATE_MCS_BF_POS) 489 490 /* 491 * Bit 20-21: HE LTF type and guard interval 492 * HE (ext) SU: 493 * 0 1xLTF+0.8us 494 * 1 2xLTF+0.8us 495 * 2 2xLTF+1.6us 496 * 3 & SGI (bit 13) clear 4xLTF+3.2us 497 * 3 & SGI (bit 13) set 4xLTF+0.8us 498 * HE MU: 499 * 0 4xLTF+0.8us 500 * 1 2xLTF+0.8us 501 * 2 2xLTF+1.6us 502 * 3 4xLTF+3.2us 503 * HE-EHT TRIG: 504 * 0 1xLTF+1.6us 505 * 1 2xLTF+1.6us 506 * 2 4xLTF+3.2us 507 * 3 (does not occur) 508 * EHT MU: 509 * 0 2xLTF+0.8us 510 * 1 2xLTF+1.6us 511 * 2 4xLTF+0.8us 512 * 3 4xLTF+3.2us 513 */ 514 #define RATE_MCS_HE_GI_LTF_POS 20 515 #define RATE_MCS_HE_GI_LTF_MSK_V1 (3 << RATE_MCS_HE_GI_LTF_POS) 516 517 /* Bit 22-23: HE type. (0) SU, (1) SU_EXT, (2) MU, (3) trigger based */ 518 #define RATE_MCS_HE_TYPE_POS_V1 22 519 #define RATE_MCS_HE_TYPE_SU_V1 (0 << RATE_MCS_HE_TYPE_POS_V1) 520 #define RATE_MCS_HE_TYPE_EXT_SU_V1 BIT(RATE_MCS_HE_TYPE_POS_V1) 521 #define RATE_MCS_HE_TYPE_MU_V1 (2 << RATE_MCS_HE_TYPE_POS_V1) 522 #define RATE_MCS_HE_TYPE_TRIG_V1 (3 << RATE_MCS_HE_TYPE_POS_V1) 523 #define RATE_MCS_HE_TYPE_MSK_V1 (3 << RATE_MCS_HE_TYPE_POS_V1) 524 525 /* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */ 526 #define RATE_MCS_DUP_POS_V1 24 527 #define RATE_MCS_DUP_MSK_V1 (3 << RATE_MCS_DUP_POS_V1) 528 529 /* Bit 27: (1) LDPC enabled, (0) LDPC disabled */ 530 #define RATE_MCS_LDPC_POS_V1 27 531 #define RATE_MCS_LDPC_MSK_V1 BIT(RATE_MCS_LDPC_POS_V1) 532 533 /* Bit 28: (1) 106-tone RX (8 MHz RU), (0) normal bandwidth */ 534 #define RATE_MCS_HE_106T_POS_V1 28 535 #define RATE_MCS_HE_106T_MSK_V1 BIT(RATE_MCS_HE_106T_POS_V1) 536 537 /* Bit 30-31: (1) RTS, (2) CTS */ 538 #define RATE_MCS_RTS_REQUIRED_POS (30) 539 #define RATE_MCS_RTS_REQUIRED_MSK (0x1 << RATE_MCS_RTS_REQUIRED_POS) 540 541 #define RATE_MCS_CTS_REQUIRED_POS (31) 542 #define RATE_MCS_CTS_REQUIRED_MSK (0x1 << RATE_MCS_CTS_REQUIRED_POS) 543 544 /* rate_n_flags bit field version 2 545 * 546 * The 32-bit value has different layouts in the low 8 bits depending on the 547 * format. There are three formats, HT, VHT and legacy (11abg, with subformats 548 * for CCK and OFDM). 549 * 550 */ 551 552 /* Bits 10-8: rate format 553 * (0) Legacy CCK (1) Legacy OFDM (2) High-throughput (HT) 554 * (3) Very High-throughput (VHT) (4) High-efficiency (HE) 555 * (5) Extremely High-throughput (EHT) 556 */ 557 #define RATE_MCS_MOD_TYPE_POS 8 558 #define RATE_MCS_MOD_TYPE_MSK (0x7 << RATE_MCS_MOD_TYPE_POS) 559 #define RATE_MCS_CCK_MSK (0 << RATE_MCS_MOD_TYPE_POS) 560 #define RATE_MCS_LEGACY_OFDM_MSK (1 << RATE_MCS_MOD_TYPE_POS) 561 #define RATE_MCS_HT_MSK (2 << RATE_MCS_MOD_TYPE_POS) 562 #define RATE_MCS_VHT_MSK (3 << RATE_MCS_MOD_TYPE_POS) 563 #define RATE_MCS_HE_MSK (4 << RATE_MCS_MOD_TYPE_POS) 564 #define RATE_MCS_EHT_MSK (5 << RATE_MCS_MOD_TYPE_POS) 565 566 /* 567 * Legacy CCK rate format for bits 0:3: 568 * 569 * (0) 0xa - 1 Mbps 570 * (1) 0x14 - 2 Mbps 571 * (2) 0x37 - 5.5 Mbps 572 * (3) 0x6e - 11 nbps 573 * 574 * Legacy OFDM rate format for bis 3:0: 575 * 576 * (0) 6 Mbps 577 * (1) 9 Mbps 578 * (2) 12 Mbps 579 * (3) 18 Mbps 580 * (4) 24 Mbps 581 * (5) 36 Mbps 582 * (6) 48 Mbps 583 * (7) 54 Mbps 584 * 585 */ 586 #define RATE_LEGACY_RATE_MSK 0x7 587 588 /* 589 * HT, VHT, HE, EHT rate format for bits 3:0 590 * 3-0: MCS 591 * 592 */ 593 #define RATE_HT_MCS_CODE_MSK 0x7 594 #define RATE_MCS_NSS_POS 4 595 #define RATE_MCS_NSS_MSK (1 << RATE_MCS_NSS_POS) 596 #define RATE_MCS_CODE_MSK 0xf 597 #define RATE_HT_MCS_INDEX(r) ((((r) & RATE_MCS_NSS_MSK) >> 1) | \ 598 ((r) & RATE_HT_MCS_CODE_MSK)) 599 600 /* Bits 7-5: reserved */ 601 602 /* 603 * Bits 13-11: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz, (4) 320MHz 604 */ 605 #define RATE_MCS_CHAN_WIDTH_MSK (0x7 << RATE_MCS_CHAN_WIDTH_POS) 606 #define RATE_MCS_CHAN_WIDTH_20_VAL 0 607 #define RATE_MCS_CHAN_WIDTH_20 (RATE_MCS_CHAN_WIDTH_20_VAL << RATE_MCS_CHAN_WIDTH_POS) 608 #define RATE_MCS_CHAN_WIDTH_40_VAL 1 609 #define RATE_MCS_CHAN_WIDTH_40 (RATE_MCS_CHAN_WIDTH_40_VAL << RATE_MCS_CHAN_WIDTH_POS) 610 #define RATE_MCS_CHAN_WIDTH_80_VAL 2 611 #define RATE_MCS_CHAN_WIDTH_80 (RATE_MCS_CHAN_WIDTH_80_VAL << RATE_MCS_CHAN_WIDTH_POS) 612 #define RATE_MCS_CHAN_WIDTH_160_VAL 3 613 #define RATE_MCS_CHAN_WIDTH_160 (RATE_MCS_CHAN_WIDTH_160_VAL << RATE_MCS_CHAN_WIDTH_POS) 614 #define RATE_MCS_CHAN_WIDTH_320_VAL 4 615 #define RATE_MCS_CHAN_WIDTH_320 (RATE_MCS_CHAN_WIDTH_320_VAL << RATE_MCS_CHAN_WIDTH_POS) 616 617 /* Bit 15-14: Antenna selection: 618 * Bit 14: Ant A active 619 * Bit 15: Ant B active 620 * 621 * All relevant definitions are same as in v1 622 */ 623 624 /* Bit 16 (1) LDPC enables, (0) LDPC disabled */ 625 #define RATE_MCS_LDPC_POS 16 626 #define RATE_MCS_LDPC_MSK (1 << RATE_MCS_LDPC_POS) 627 628 /* Bit 17: (0) SS, (1) SS*2 (same as v1) */ 629 630 /* Bit 18: OFDM-HE dual carrier mode (same as v1) */ 631 632 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on (same as v1) */ 633 634 /* 635 * Bit 22-20: HE LTF type and guard interval 636 * CCK: 637 * 0 long preamble 638 * 1 short preamble 639 * HT/VHT: 640 * 0 0.8us 641 * 1 0.4us 642 * HE (ext) SU: 643 * 0 1xLTF+0.8us 644 * 1 2xLTF+0.8us 645 * 2 2xLTF+1.6us 646 * 3 4xLTF+3.2us 647 * 4 4xLTF+0.8us 648 * HE MU: 649 * 0 4xLTF+0.8us 650 * 1 2xLTF+0.8us 651 * 2 2xLTF+1.6us 652 * 3 4xLTF+3.2us 653 * HE TRIG: 654 * 0 1xLTF+1.6us 655 * 1 2xLTF+1.6us 656 * 2 4xLTF+3.2us 657 * */ 658 #define RATE_MCS_HE_GI_LTF_MSK (0x7 << RATE_MCS_HE_GI_LTF_POS) 659 #define RATE_MCS_SGI_POS RATE_MCS_HE_GI_LTF_POS 660 #define RATE_MCS_SGI_MSK (1 << RATE_MCS_SGI_POS) 661 #define RATE_MCS_HE_SU_4_LTF 3 662 #define RATE_MCS_HE_SU_4_LTF_08_GI 4 663 664 /* Bit 24-23: HE type. (0) SU, (1) SU_EXT, (2) MU, (3) trigger based */ 665 #define RATE_MCS_HE_TYPE_POS 23 666 #define RATE_MCS_HE_TYPE_SU (0 << RATE_MCS_HE_TYPE_POS) 667 #define RATE_MCS_HE_TYPE_EXT_SU (1 << RATE_MCS_HE_TYPE_POS) 668 #define RATE_MCS_HE_TYPE_MU (2 << RATE_MCS_HE_TYPE_POS) 669 #define RATE_MCS_HE_TYPE_TRIG (3 << RATE_MCS_HE_TYPE_POS) 670 #define RATE_MCS_HE_TYPE_MSK (3 << RATE_MCS_HE_TYPE_POS) 671 672 /* Bit 25: duplicate channel enabled 673 * 674 * if this bit is set, duplicate is according to BW (bits 11-13): 675 * 676 * CCK: 2x 20MHz 677 * OFDM Legacy: N x 20Mhz, (N = BW \ 2 , either 2, 4, 8, 16) 678 * EHT: 2 x BW/2, (80 - 2x40, 160 - 2x80, 320 - 2x160) 679 * */ 680 #define RATE_MCS_DUP_POS 25 681 #define RATE_MCS_DUP_MSK (1 << RATE_MCS_DUP_POS) 682 683 /* Bit 26: (1) 106-tone RX (8 MHz RU), (0) normal bandwidth */ 684 #define RATE_MCS_HE_106T_POS 26 685 #define RATE_MCS_HE_106T_MSK (1 << RATE_MCS_HE_106T_POS) 686 687 /* Bit 27: EHT extra LTF: 688 * instead of 1 LTF for SISO use 2 LTFs, 689 * instead of 2 LTFs for NSTS=2 use 4 LTFs*/ 690 #define RATE_MCS_EHT_EXTRA_LTF_POS 27 691 #define RATE_MCS_EHT_EXTRA_LTF_MSK (1 << RATE_MCS_EHT_EXTRA_LTF_POS) 692 693 /* Bit 31-28: reserved */ 694 695 /* Link Quality definitions */ 696 697 /* # entries in rate scale table to support Tx retries */ 698 #define LQ_MAX_RETRY_NUM 16 699 700 /* Link quality command flags bit fields */ 701 702 /* Bit 0: (0) Don't use RTS (1) Use RTS */ 703 #define LQ_FLAG_USE_RTS_POS 0 704 #define LQ_FLAG_USE_RTS_MSK (1 << LQ_FLAG_USE_RTS_POS) 705 706 /* Bit 1-3: LQ command color. Used to match responses to LQ commands */ 707 #define LQ_FLAG_COLOR_POS 1 708 #define LQ_FLAG_COLOR_MSK (7 << LQ_FLAG_COLOR_POS) 709 #define LQ_FLAG_COLOR_GET(_f) (((_f) & LQ_FLAG_COLOR_MSK) >>\ 710 LQ_FLAG_COLOR_POS) 711 #define LQ_FLAGS_COLOR_INC(_c) ((((_c) + 1) << LQ_FLAG_COLOR_POS) &\ 712 LQ_FLAG_COLOR_MSK) 713 #define LQ_FLAG_COLOR_SET(_f, _c) ((_c) | ((_f) & ~LQ_FLAG_COLOR_MSK)) 714 715 /* Bit 4-5: Tx RTS BW Signalling 716 * (0) No RTS BW signalling 717 * (1) Static BW signalling 718 * (2) Dynamic BW signalling 719 */ 720 #define LQ_FLAG_RTS_BW_SIG_POS 4 721 #define LQ_FLAG_RTS_BW_SIG_NONE (0 << LQ_FLAG_RTS_BW_SIG_POS) 722 #define LQ_FLAG_RTS_BW_SIG_STATIC (1 << LQ_FLAG_RTS_BW_SIG_POS) 723 #define LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << LQ_FLAG_RTS_BW_SIG_POS) 724 725 /* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection 726 * Dyanmic BW selection allows Tx with narrower BW then requested in rates 727 */ 728 #define LQ_FLAG_DYNAMIC_BW_POS 6 729 #define LQ_FLAG_DYNAMIC_BW_MSK (1 << LQ_FLAG_DYNAMIC_BW_POS) 730 731 /* Single Stream Tx Parameters (lq_cmd->ss_params) 732 * Flags to control a smart FW decision about whether BFER/STBC/SISO will be 733 * used for single stream Tx. 734 */ 735 736 /* Bit 0-1: Max STBC streams allowed. Can be 0-3. 737 * (0) - No STBC allowed 738 * (1) - 2x1 STBC allowed (HT/VHT) 739 * (2) - 4x2 STBC allowed (HT/VHT) 740 * (3) - 3x2 STBC allowed (HT only) 741 * All our chips are at most 2 antennas so only (1) is valid for now. 742 */ 743 #define LQ_SS_STBC_ALLOWED_POS 0 744 #define LQ_SS_STBC_ALLOWED_MSK (3 << LQ_SS_STBC_ALLOWED_MSK) 745 746 /* 2x1 STBC is allowed */ 747 #define LQ_SS_STBC_1SS_ALLOWED (1 << LQ_SS_STBC_ALLOWED_POS) 748 749 /* Bit 2: Beamformer (VHT only) is allowed */ 750 #define LQ_SS_BFER_ALLOWED_POS 2 751 #define LQ_SS_BFER_ALLOWED (1 << LQ_SS_BFER_ALLOWED_POS) 752 753 /* Bit 3: Force BFER or STBC for testing 754 * If this is set: 755 * If BFER is allowed then force the ucode to choose BFER else 756 * If STBC is allowed then force the ucode to choose STBC over SISO 757 */ 758 #define LQ_SS_FORCE_POS 3 759 #define LQ_SS_FORCE (1 << LQ_SS_FORCE_POS) 760 761 /* Bit 31: ss_params field is valid. Used for FW backward compatibility 762 * with other drivers which don't support the ss_params API yet 763 */ 764 #define LQ_SS_PARAMS_VALID_POS 31 765 #define LQ_SS_PARAMS_VALID (1 << LQ_SS_PARAMS_VALID_POS) 766 767 /** 768 * struct iwl_lq_cmd - link quality command 769 * @sta_id: station to update 770 * @reduced_tpc: reduced transmit power control value 771 * @control: not used 772 * @flags: combination of LQ_FLAG_* 773 * @mimo_delim: the first SISO index in rs_table, which separates MIMO 774 * and SISO rates 775 * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD). 776 * Should be ANT_[ABC] 777 * @dual_stream_ant_msk: best antennas for MIMO, combination of ANT_[ABC] 778 * @initial_rate_index: first index from rs_table per AC category 779 * @agg_time_limit: aggregation max time threshold in usec/100, meaning 780 * value of 100 is one usec. Range is 100 to 8000 781 * @agg_disable_start_th: try-count threshold for starting aggregation. 782 * If a frame has higher try-count, it should not be selected for 783 * starting an aggregation sequence. 784 * @agg_frame_cnt_limit: max frame count in an aggregation. 785 * 0: no limit 786 * 1: no aggregation (one frame per aggregation) 787 * 2 - 0x3f: maximal number of frames (up to 3f == 63) 788 * @reserved2: reserved 789 * @rs_table: array of rates for each TX try, each is rate_n_flags, 790 * meaning it is a combination of RATE_MCS_* and IWL_RATE_*_PLCP 791 * @ss_params: single stream features. declare whether STBC or BFER are allowed. 792 */ 793 struct iwl_lq_cmd { 794 u8 sta_id; 795 u8 reduced_tpc; 796 __le16 control; 797 /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */ 798 u8 flags; 799 u8 mimo_delim; 800 u8 single_stream_ant_msk; 801 u8 dual_stream_ant_msk; 802 u8 initial_rate_index[AC_NUM]; 803 /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */ 804 __le16 agg_time_limit; 805 u8 agg_disable_start_th; 806 u8 agg_frame_cnt_limit; 807 __le32 reserved2; 808 __le32 rs_table[LQ_MAX_RETRY_NUM]; 809 __le32 ss_params; 810 }; /* LINK_QUALITY_CMD_API_S_VER_1 */ 811 812 u8 iwl_fw_rate_idx_to_plcp(int idx); 813 u32 iwl_new_rate_from_v1(u32 rate_v1); 814 const struct iwl_rate_mcs_info *iwl_rate_mcs(int idx); 815 const char *iwl_rs_pretty_ant(u8 ant); 816 const char *iwl_rs_pretty_bw(int bw); 817 int rs_pretty_print_rate(char *buf, int bufsz, const u32 rate); 818 bool iwl_he_is_sgi(u32 rate_n_flags); 819 820 #endif /* __iwl_fw_api_rs_h__ */ 821