1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29 #ifndef __ECORE_HSI_IWARP__ 30 #define __ECORE_HSI_IWARP__ 31 /************************************************************************/ 32 /* Add include to ecore hsi rdma target for both roce and iwarp ecore driver */ 33 /************************************************************************/ 34 #include "ecore_hsi_rdma.h" 35 /************************************************************************/ 36 /* Add include to common TCP target */ 37 /************************************************************************/ 38 #include "tcp_common.h" 39 40 /************************************************************************/ 41 /* Add include to common iwarp target for both eCore and protocol iwarp driver */ 42 /************************************************************************/ 43 #include "iwarp_common.h" 44 45 /* 46 * The iwarp storm context of Ystorm 47 */ 48 struct ystorm_iwarp_conn_st_ctx 49 { 50 __le32 reserved[4]; 51 }; 52 53 /* 54 * The iwarp storm context of Pstorm 55 */ 56 struct pstorm_iwarp_conn_st_ctx 57 { 58 __le32 reserved[36]; 59 }; 60 61 /* 62 * The iwarp storm context of Xstorm 63 */ 64 struct xstorm_iwarp_conn_st_ctx 65 { 66 __le32 reserved[48]; 67 }; 68 69 struct e4_xstorm_iwarp_conn_ag_ctx 70 { 71 u8 reserved0 /* cdu_validation */; 72 u8 state /* state */; 73 u8 flags0; 74 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 75 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 76 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1 /* exist_in_qm1 */ 77 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1 78 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_MASK 0x1 /* exist_in_qm2 */ 79 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_SHIFT 2 80 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 81 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 82 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 83 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4 84 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED2_MASK 0x1 /* cf_array_active */ 85 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED2_SHIFT 5 86 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT6_MASK 0x1 /* bit6 */ 87 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT6_SHIFT 6 88 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT7_MASK 0x1 /* bit7 */ 89 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT7_SHIFT 7 90 u8 flags1; 91 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT8_MASK 0x1 /* bit8 */ 92 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT8_SHIFT 0 93 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT9_MASK 0x1 /* bit9 */ 94 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT9_SHIFT 1 95 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT10_MASK 0x1 /* bit10 */ 96 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT10_SHIFT 2 97 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 98 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT11_SHIFT 3 99 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 100 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT12_SHIFT 4 101 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 102 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT13_SHIFT 5 103 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT14_MASK 0x1 /* bit14 */ 104 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT14_SHIFT 6 105 #define E4_XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_MASK 0x1 /* bit15 */ 106 #define E4_XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_SHIFT 7 107 u8 flags2; 108 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 109 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 0 110 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 111 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 2 112 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 113 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 4 114 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 /* timer_stop_all */ 115 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6 116 u8 flags3; 117 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 118 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 0 119 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 120 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 2 121 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 122 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 4 123 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 124 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 6 125 u8 flags4; 126 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 127 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 0 128 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 129 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9_SHIFT 2 130 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 131 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10_SHIFT 4 132 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 133 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11_SHIFT 6 134 u8 flags5; 135 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 136 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12_SHIFT 0 137 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 138 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13_SHIFT 2 139 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3 /* cf14 */ 140 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 4 141 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 142 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15_SHIFT 6 143 u8 flags6; 144 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_MASK 0x3 /* cf16 */ 145 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_SHIFT 0 146 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 147 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17_SHIFT 2 148 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */ 149 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18_SHIFT 4 150 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_MASK 0x3 /* cf19 */ 151 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_SHIFT 6 152 u8 flags7; 153 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */ 154 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 155 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_MASK 0x3 /* cf21 */ 156 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_SHIFT 2 157 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 158 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_SHIFT 4 159 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 160 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 6 161 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 162 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 7 163 u8 flags8; 164 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 165 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 0 166 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 /* cf3en */ 167 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1 168 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 169 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 2 170 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 171 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 3 172 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 173 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 4 174 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 175 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 5 176 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 177 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 6 178 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 179 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9EN_SHIFT 7 180 u8 flags9; 181 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 182 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10EN_SHIFT 0 183 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 184 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11EN_SHIFT 1 185 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 186 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12EN_SHIFT 2 187 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 188 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13EN_SHIFT 3 189 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1 /* cf14en */ 190 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 4 191 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 192 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15EN_SHIFT 5 193 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_MASK 0x1 /* cf16en */ 194 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_SHIFT 6 195 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 196 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17EN_SHIFT 7 197 u8 flags10; 198 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */ 199 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18EN_SHIFT 0 200 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1 /* cf19en */ 201 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1 202 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 203 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 204 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_MASK 0x1 /* cf21en */ 205 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_SHIFT 3 206 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 207 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 208 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 209 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF23EN_SHIFT 5 210 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 211 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 6 212 #define E4_XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK 0x1 /* rule1en */ 213 #define E4_XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_SHIFT 7 214 u8 flags11; 215 #define E4_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1 /* rule2en */ 216 #define E4_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0 217 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 218 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 1 219 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED3_MASK 0x1 /* rule4en */ 220 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED3_SHIFT 2 221 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 222 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 3 223 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 224 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 4 225 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 226 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 5 227 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 228 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 229 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 230 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE9EN_SHIFT 7 231 u8 flags12; 232 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_MASK 0x1 /* rule10en */ 233 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_SHIFT 0 234 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 235 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE11EN_SHIFT 1 236 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 237 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 238 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 239 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 240 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_MASK 0x1 /* rule14en */ 241 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_SHIFT 4 242 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 243 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE15EN_SHIFT 5 244 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 245 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE16EN_SHIFT 6 246 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 247 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE17EN_SHIFT 7 248 u8 flags13; 249 #define E4_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_MASK 0x1 /* rule18en */ 250 #define E4_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_SHIFT 0 251 #define E4_XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_MASK 0x1 /* rule19en */ 252 #define E4_XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_SHIFT 1 253 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_MASK 0x1 /* rule20en */ 254 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_SHIFT 2 255 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE21EN_MASK 0x1 /* rule21en */ 256 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE21EN_SHIFT 3 257 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 258 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 259 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_MASK 0x1 /* rule23en */ 260 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_SHIFT 5 261 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 262 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 263 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 264 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 265 u8 flags14; 266 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT16_MASK 0x1 /* bit16 */ 267 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT16_SHIFT 0 268 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 269 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT17_SHIFT 1 270 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT18_MASK 0x1 /* bit18 */ 271 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT18_SHIFT 2 272 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_MASK 0x1 /* bit19 */ 273 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_SHIFT 3 274 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_MASK 0x1 /* bit20 */ 275 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_SHIFT 4 276 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_MASK 0x1 /* bit21 */ 277 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_SHIFT 5 278 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 279 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF23_SHIFT 6 280 u8 byte2 /* byte2 */; 281 __le16 physical_q0 /* physical_q0 */; 282 __le16 physical_q1 /* physical_q1 */; 283 __le16 sq_comp_cons /* physical_q2 */; 284 __le16 sq_tx_cons /* word3 */; 285 __le16 sq_prod /* word4 */; 286 __le16 word5 /* word5 */; 287 __le16 conn_dpi /* conn_dpi */; 288 u8 byte3 /* byte3 */; 289 u8 byte4 /* byte4 */; 290 u8 byte5 /* byte5 */; 291 u8 byte6 /* byte6 */; 292 __le32 reg0 /* reg0 */; 293 __le32 reg1 /* reg1 */; 294 __le32 reg2 /* reg2 */; 295 __le32 more_to_send_seq /* reg3 */; 296 __le32 reg4 /* reg4 */; 297 __le32 rewinded_snd_max /* cf_array0 */; 298 __le32 rd_msn /* cf_array1 */; 299 __le16 irq_prod_via_msdm /* word7 */; 300 __le16 irq_cons /* word8 */; 301 __le16 hq_cons_th_or_mpa_data /* word9 */; 302 __le16 hq_cons /* word10 */; 303 __le32 atom_msn /* reg7 */; 304 __le32 orq_cons /* reg8 */; 305 __le32 orq_cons_th /* reg9 */; 306 u8 byte7 /* byte7 */; 307 u8 max_ord /* byte8 */; 308 u8 wqe_data_pad_bytes /* byte9 */; 309 u8 former_hq_prod /* byte10 */; 310 u8 irq_prod_via_msem /* byte11 */; 311 u8 byte12 /* byte12 */; 312 u8 max_pkt_pdu_size_lo /* byte13 */; 313 u8 max_pkt_pdu_size_hi /* byte14 */; 314 u8 byte15 /* byte15 */; 315 u8 e5_reserved /* e5_reserved */; 316 __le16 e5_reserved4 /* word11 */; 317 __le32 reg10 /* reg10 */; 318 __le32 reg11 /* reg11 */; 319 __le32 shared_queue_page_addr_lo /* reg12 */; 320 __le32 shared_queue_page_addr_hi /* reg13 */; 321 __le32 reg14 /* reg14 */; 322 __le32 reg15 /* reg15 */; 323 __le32 reg16 /* reg16 */; 324 __le32 reg17 /* reg17 */; 325 }; 326 327 struct e4_tstorm_iwarp_conn_ag_ctx 328 { 329 u8 reserved0 /* cdu_validation */; 330 u8 state /* state */; 331 u8 flags0; 332 #define E4_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 333 #define E4_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 334 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 335 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 336 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 337 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT2_SHIFT 2 338 #define E4_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 /* bit3 */ 339 #define E4_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 3 340 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 341 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4 342 #define E4_TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_MASK 0x1 /* bit5 */ 343 #define E4_TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_SHIFT 5 344 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 345 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 6 346 u8 flags1; 347 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_MASK 0x3 /* timer1cf */ 348 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_SHIFT 0 349 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_MASK 0x3 /* timer2cf */ 350 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_SHIFT 2 351 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 /* timer_stop_all */ 352 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4 353 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 354 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 6 355 u8 flags2; 356 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 357 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 0 358 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 359 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 2 360 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 361 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 4 362 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 363 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 6 364 u8 flags3; 365 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_MASK 0x3 /* cf9 */ 366 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_SHIFT 0 367 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_MASK 0x3 /* cf10 */ 368 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_SHIFT 2 369 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 370 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 4 371 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_MASK 0x1 /* cf1en */ 372 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_SHIFT 5 373 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_MASK 0x1 /* cf2en */ 374 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_SHIFT 6 375 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 /* cf3en */ 376 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7 377 u8 flags4; 378 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 379 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 0 380 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 381 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 1 382 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 383 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 2 384 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 385 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 3 386 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 387 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 4 388 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_EN_MASK 0x1 /* cf9en */ 389 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_EN_SHIFT 5 390 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_MASK 0x1 /* cf10en */ 391 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_SHIFT 6 392 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 393 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 7 394 u8 flags5; 395 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 396 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 0 397 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 398 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1 399 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 400 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2 401 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 402 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3 403 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 404 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4 405 #define E4_TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_MASK 0x1 /* rule6en */ 406 #define E4_TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_SHIFT 5 407 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 408 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6 409 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 410 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7 411 __le32 reg0 /* reg0 */; 412 __le32 reg1 /* reg1 */; 413 __le32 unaligned_nxt_seq /* reg2 */; 414 __le32 reg3 /* reg3 */; 415 __le32 reg4 /* reg4 */; 416 __le32 reg5 /* reg5 */; 417 __le32 reg6 /* reg6 */; 418 __le32 reg7 /* reg7 */; 419 __le32 reg8 /* reg8 */; 420 u8 orq_cache_idx /* byte2 */; 421 u8 hq_prod /* byte3 */; 422 __le16 sq_tx_cons_th /* word0 */; 423 u8 orq_prod /* byte4 */; 424 u8 irq_cons /* byte5 */; 425 __le16 sq_tx_cons /* word1 */; 426 __le16 conn_dpi /* conn_dpi */; 427 __le16 rq_prod /* word3 */; 428 __le32 snd_seq /* reg9 */; 429 __le32 last_hq_sequence /* reg10 */; 430 }; 431 432 /* 433 * The iwarp storm context of Tstorm 434 */ 435 struct tstorm_iwarp_conn_st_ctx 436 { 437 __le32 reserved[60]; 438 }; 439 440 /* 441 * The iwarp storm context of Mstorm 442 */ 443 struct mstorm_iwarp_conn_st_ctx 444 { 445 __le32 reserved[32]; 446 }; 447 448 /* 449 * The iwarp storm context of Ustorm 450 */ 451 struct ustorm_iwarp_conn_st_ctx 452 { 453 __le32 reserved[24]; 454 }; 455 456 /* 457 * iwarp connection context 458 */ 459 struct e4_iwarp_conn_context 460 { 461 struct ystorm_iwarp_conn_st_ctx ystorm_st_context /* ystorm storm context */; 462 struct regpair ystorm_st_padding[2] /* padding */; 463 struct pstorm_iwarp_conn_st_ctx pstorm_st_context /* pstorm storm context */; 464 struct regpair pstorm_st_padding[2] /* padding */; 465 struct xstorm_iwarp_conn_st_ctx xstorm_st_context /* xstorm storm context */; 466 struct regpair xstorm_st_padding[2] /* padding */; 467 struct e4_xstorm_iwarp_conn_ag_ctx xstorm_ag_context /* xstorm aggregative context */; 468 struct e4_tstorm_iwarp_conn_ag_ctx tstorm_ag_context /* tstorm aggregative context */; 469 struct timers_context timer_context /* timer context */; 470 struct e4_ustorm_rdma_conn_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 471 struct tstorm_iwarp_conn_st_ctx tstorm_st_context /* tstorm storm context */; 472 struct regpair tstorm_st_padding[2] /* padding */; 473 struct mstorm_iwarp_conn_st_ctx mstorm_st_context /* mstorm storm context */; 474 struct ustorm_iwarp_conn_st_ctx ustorm_st_context /* ustorm storm context */; 475 }; 476 477 struct e5_xstorm_iwarp_conn_ag_ctx 478 { 479 u8 reserved0 /* cdu_validation */; 480 u8 state_and_core_id /* state_and_core_id */; 481 u8 flags0; 482 #define E5_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 483 #define E5_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 484 #define E5_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1 /* exist_in_qm1 */ 485 #define E5_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1 486 #define E5_XSTORM_IWARP_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm2 */ 487 #define E5_XSTORM_IWARP_CONN_AG_CTX_RESERVED1_SHIFT 2 488 #define E5_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 489 #define E5_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 490 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 491 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4 492 #define E5_XSTORM_IWARP_CONN_AG_CTX_RESERVED2_MASK 0x1 /* cf_array_active */ 493 #define E5_XSTORM_IWARP_CONN_AG_CTX_RESERVED2_SHIFT 5 494 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT6_MASK 0x1 /* bit6 */ 495 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT6_SHIFT 6 496 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT7_MASK 0x1 /* bit7 */ 497 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT7_SHIFT 7 498 u8 flags1; 499 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT8_MASK 0x1 /* bit8 */ 500 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT8_SHIFT 0 501 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT9_MASK 0x1 /* bit9 */ 502 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT9_SHIFT 1 503 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT10_MASK 0x1 /* bit10 */ 504 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT10_SHIFT 2 505 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 506 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT11_SHIFT 3 507 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 508 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT12_SHIFT 4 509 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 510 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT13_SHIFT 5 511 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT14_MASK 0x1 /* bit14 */ 512 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT14_SHIFT 6 513 #define E5_XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_MASK 0x1 /* bit15 */ 514 #define E5_XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_SHIFT 7 515 u8 flags2; 516 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 517 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 0 518 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 519 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 2 520 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 521 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 4 522 #define E5_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 /* timer_stop_all */ 523 #define E5_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6 524 u8 flags3; 525 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 526 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 0 527 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 528 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 2 529 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 530 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 4 531 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 532 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 6 533 u8 flags4; 534 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 535 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 0 536 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 537 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF9_SHIFT 2 538 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 539 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF10_SHIFT 4 540 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 541 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF11_SHIFT 6 542 u8 flags5; 543 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 544 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF12_SHIFT 0 545 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 546 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF13_SHIFT 2 547 #define E5_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3 /* cf14 */ 548 #define E5_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 4 549 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 550 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF15_SHIFT 6 551 u8 flags6; 552 #define E5_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_MASK 0x3 /* cf16 */ 553 #define E5_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_SHIFT 0 554 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 555 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF17_SHIFT 2 556 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */ 557 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF18_SHIFT 4 558 #define E5_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_MASK 0x3 /* cf19 */ 559 #define E5_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_SHIFT 6 560 u8 flags7; 561 #define E5_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */ 562 #define E5_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 563 #define E5_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_MASK 0x3 /* cf21 */ 564 #define E5_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_SHIFT 2 565 #define E5_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 566 #define E5_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_SHIFT 4 567 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 568 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 6 569 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 570 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 7 571 u8 flags8; 572 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 573 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 0 574 #define E5_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 /* cf3en */ 575 #define E5_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1 576 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 577 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 2 578 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 579 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 3 580 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 581 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 4 582 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 583 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 5 584 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 585 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 6 586 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 587 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF9EN_SHIFT 7 588 u8 flags9; 589 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 590 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF10EN_SHIFT 0 591 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 592 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF11EN_SHIFT 1 593 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 594 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF12EN_SHIFT 2 595 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 596 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF13EN_SHIFT 3 597 #define E5_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1 /* cf14en */ 598 #define E5_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 4 599 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 600 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF15EN_SHIFT 5 601 #define E5_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_MASK 0x1 /* cf16en */ 602 #define E5_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_SHIFT 6 603 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 604 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF17EN_SHIFT 7 605 u8 flags10; 606 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */ 607 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF18EN_SHIFT 0 608 #define E5_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1 /* cf19en */ 609 #define E5_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1 610 #define E5_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 611 #define E5_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 612 #define E5_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_MASK 0x1 /* cf21en */ 613 #define E5_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_SHIFT 3 614 #define E5_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 615 #define E5_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 616 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 617 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF23EN_SHIFT 5 618 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 619 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 6 620 #define E5_XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK 0x1 /* rule1en */ 621 #define E5_XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_SHIFT 7 622 u8 flags11; 623 #define E5_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1 /* rule2en */ 624 #define E5_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0 625 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 626 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 1 627 #define E5_XSTORM_IWARP_CONN_AG_CTX_RESERVED3_MASK 0x1 /* rule4en */ 628 #define E5_XSTORM_IWARP_CONN_AG_CTX_RESERVED3_SHIFT 2 629 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 630 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 3 631 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 632 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 4 633 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 634 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 5 635 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 636 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 637 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 638 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE9EN_SHIFT 7 639 u8 flags12; 640 #define E5_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_MASK 0x1 /* rule10en */ 641 #define E5_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_SHIFT 0 642 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 643 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE11EN_SHIFT 1 644 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 645 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 646 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 647 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 648 #define E5_XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_MASK 0x1 /* rule14en */ 649 #define E5_XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_SHIFT 4 650 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 651 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE15EN_SHIFT 5 652 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 653 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE16EN_SHIFT 6 654 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 655 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE17EN_SHIFT 7 656 u8 flags13; 657 #define E5_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_MASK 0x1 /* rule18en */ 658 #define E5_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_SHIFT 0 659 #define E5_XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_MASK 0x1 /* rule19en */ 660 #define E5_XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_SHIFT 1 661 #define E5_XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_MASK 0x1 /* rule20en */ 662 #define E5_XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_SHIFT 2 663 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE21EN_MASK 0x1 /* rule21en */ 664 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE21EN_SHIFT 3 665 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 666 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 667 #define E5_XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_MASK 0x1 /* rule23en */ 668 #define E5_XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_SHIFT 5 669 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 670 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 671 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 672 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 673 u8 flags14; 674 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT16_MASK 0x1 /* bit16 */ 675 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT16_SHIFT 0 676 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 677 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT17_SHIFT 1 678 #define E5_XSTORM_IWARP_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 /* bit18 */ 679 #define E5_XSTORM_IWARP_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2 680 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT20_MASK 0x1 /* bit20 */ 681 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT20_SHIFT 4 682 #define E5_XSTORM_IWARP_CONN_AG_CTX_RDMA_EDPM_ENABLE_MASK 0x1 /* bit21 */ 683 #define E5_XSTORM_IWARP_CONN_AG_CTX_RDMA_EDPM_ENABLE_SHIFT 5 684 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 685 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF23_SHIFT 6 686 u8 byte2 /* byte2 */; 687 __le16 physical_q0 /* physical_q0 */; 688 __le16 physical_q1 /* physical_q1 */; 689 __le16 sq_comp_cons /* physical_q2 */; 690 __le16 sq_tx_cons /* word3 */; 691 __le16 sq_prod /* word4 */; 692 __le16 word5 /* word5 */; 693 __le16 conn_dpi /* conn_dpi */; 694 u8 byte3 /* byte3 */; 695 u8 byte4 /* byte4 */; 696 u8 byte5 /* byte5 */; 697 u8 byte6 /* byte6 */; 698 __le32 reg0 /* reg0 */; 699 __le32 reg1 /* reg1 */; 700 __le32 reg2 /* reg2 */; 701 __le32 more_to_send_seq /* reg3 */; 702 __le32 reg4 /* reg4 */; 703 __le32 rewinded_snd_max /* cf_array0 */; 704 __le32 rd_msn /* cf_array1 */; 705 u8 flags15; 706 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit22 */ 707 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 708 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit23 */ 709 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 710 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit24 */ 711 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 712 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf24 */ 713 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED4_SHIFT 3 714 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf24en */ 715 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED5_SHIFT 5 716 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule26en */ 717 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED6_SHIFT 6 718 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule27en */ 719 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED7_SHIFT 7 720 u8 byte7 /* byte7 */; 721 __le16 irq_prod_via_msdm /* word7 */; 722 __le16 irq_cons /* word8 */; 723 __le16 hq_cons_th_or_mpa_data /* word9 */; 724 __le16 hq_cons /* word10 */; 725 __le16 tx_rdma_edpm_usg_cnt /* word11 */; 726 __le32 atom_msn /* reg7 */; 727 __le32 orq_cons /* reg8 */; 728 __le32 orq_cons_th /* reg9 */; 729 u8 max_ord /* byte8 */; 730 u8 wqe_data_pad_bytes /* byte9 */; 731 u8 former_hq_prod /* byte10 */; 732 u8 irq_prod_via_msem /* byte11 */; 733 u8 byte12 /* byte12 */; 734 u8 max_pkt_pdu_size_lo /* byte13 */; 735 u8 max_pkt_pdu_size_hi /* byte14 */; 736 u8 byte15 /* byte15 */; 737 __le32 reg10 /* reg10 */; 738 __le32 reg11 /* reg11 */; 739 __le32 reg12 /* reg12 */; 740 __le32 shared_queue_page_addr_lo /* reg13 */; 741 __le32 shared_queue_page_addr_hi /* reg14 */; 742 __le32 reg15 /* reg15 */; 743 __le32 reg16 /* reg16 */; 744 __le32 reg17 /* reg17 */; 745 }; 746 747 struct e5_tstorm_iwarp_conn_ag_ctx 748 { 749 u8 reserved0 /* cdu_validation */; 750 u8 state_and_core_id /* state_and_core_id */; 751 u8 flags0; 752 #define E5_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 753 #define E5_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 754 #define E5_TSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 755 #define E5_TSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 756 #define E5_TSTORM_IWARP_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 757 #define E5_TSTORM_IWARP_CONN_AG_CTX_BIT2_SHIFT 2 758 #define E5_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 /* bit3 */ 759 #define E5_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 3 760 #define E5_TSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 761 #define E5_TSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4 762 #define E5_TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_MASK 0x1 /* bit5 */ 763 #define E5_TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_SHIFT 5 764 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 765 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 6 766 u8 flags1; 767 #define E5_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_MASK 0x3 /* timer1cf */ 768 #define E5_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_SHIFT 0 769 #define E5_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_MASK 0x3 /* timer2cf */ 770 #define E5_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_SHIFT 2 771 #define E5_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 /* timer_stop_all */ 772 #define E5_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4 773 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 774 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 6 775 u8 flags2; 776 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 777 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 0 778 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 779 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 2 780 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 781 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 4 782 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 783 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 6 784 u8 flags3; 785 #define E5_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf9 */ 786 #define E5_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 787 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 788 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF10_SHIFT 2 789 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 790 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 4 791 #define E5_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_MASK 0x1 /* cf1en */ 792 #define E5_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_SHIFT 5 793 #define E5_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_MASK 0x1 /* cf2en */ 794 #define E5_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_SHIFT 6 795 #define E5_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 /* cf3en */ 796 #define E5_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7 797 u8 flags4; 798 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 799 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 0 800 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 801 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 1 802 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 803 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 2 804 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 805 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 3 806 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 807 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 4 808 #define E5_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf9en */ 809 #define E5_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 5 810 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 811 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF10EN_SHIFT 6 812 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 813 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 7 814 u8 flags5; 815 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 816 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 0 817 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 818 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1 819 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 820 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2 821 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 822 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3 823 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 824 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4 825 #define E5_TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_MASK 0x1 /* rule6en */ 826 #define E5_TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_SHIFT 5 827 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 828 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6 829 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 830 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7 831 u8 flags6; 832 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit6 */ 833 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 834 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit7 */ 835 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 836 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit8 */ 837 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 838 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf11 */ 839 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED4_SHIFT 3 840 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf11en */ 841 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED5_SHIFT 5 842 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule9en */ 843 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED6_SHIFT 6 844 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule10en */ 845 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED7_SHIFT 7 846 u8 orq_cache_idx /* byte2 */; 847 __le16 sq_tx_cons_th /* word0 */; 848 __le32 reg0 /* reg0 */; 849 __le32 reg1 /* reg1 */; 850 __le32 unaligned_nxt_seq /* reg2 */; 851 __le32 reg3 /* reg3 */; 852 __le32 reg4 /* reg4 */; 853 __le32 reg5 /* reg5 */; 854 __le32 reg6 /* reg6 */; 855 __le32 reg7 /* reg7 */; 856 __le32 reg8 /* reg8 */; 857 u8 hq_prod /* byte3 */; 858 u8 orq_prod /* byte4 */; 859 u8 irq_cons /* byte5 */; 860 u8 e4_reserved8 /* byte6 */; 861 __le16 sq_tx_cons /* word1 */; 862 __le16 conn_dpi /* conn_dpi */; 863 __le32 snd_seq /* reg9 */; 864 __le16 rq_prod /* word3 */; 865 __le16 e4_reserved9 /* word4 */; 866 }; 867 868 /* 869 * iwarp connection context 870 */ 871 struct e5_iwarp_conn_context 872 { 873 struct ystorm_iwarp_conn_st_ctx ystorm_st_context /* ystorm storm context */; 874 struct regpair ystorm_st_padding[2] /* padding */; 875 struct pstorm_iwarp_conn_st_ctx pstorm_st_context /* pstorm storm context */; 876 struct regpair pstorm_st_padding[2] /* padding */; 877 struct xstorm_iwarp_conn_st_ctx xstorm_st_context /* xstorm storm context */; 878 struct regpair xstorm_st_padding[2] /* padding */; 879 struct e5_xstorm_iwarp_conn_ag_ctx xstorm_ag_context /* xstorm aggregative context */; 880 struct e5_tstorm_iwarp_conn_ag_ctx tstorm_ag_context /* tstorm aggregative context */; 881 struct timers_context timer_context /* timer context */; 882 struct e5_ustorm_rdma_conn_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 883 struct tstorm_iwarp_conn_st_ctx tstorm_st_context /* tstorm storm context */; 884 struct regpair tstorm_st_padding[2] /* padding */; 885 struct mstorm_iwarp_conn_st_ctx mstorm_st_context /* mstorm storm context */; 886 struct ustorm_iwarp_conn_st_ctx ustorm_st_context /* ustorm storm context */; 887 }; 888 889 /* 890 * iWARP create QP params passed by driver to FW in CreateQP Request Ramrod 891 */ 892 struct iwarp_create_qp_ramrod_data 893 { 894 u8 flags; 895 #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1 896 #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 0 897 #define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_MASK 0x1 898 #define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_SHIFT 1 899 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1 900 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT 2 901 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1 902 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3 903 #define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1 904 #define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_SHIFT 4 905 #define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_MASK 0x1 906 #define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_SHIFT 5 907 #define IWARP_CREATE_QP_RAMROD_DATA_LOW_LATENCY_QUEUE_EN_MASK 0x1 908 #define IWARP_CREATE_QP_RAMROD_DATA_LOW_LATENCY_QUEUE_EN_SHIFT 6 909 #define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_MASK 0x1 910 #define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_SHIFT 7 911 u8 reserved1 /* Basic/Enhanced (use enum mpa_negotiation_mode) */; 912 __le16 pd; 913 __le16 sq_num_pages; 914 __le16 rq_num_pages; 915 __le32 reserved3[2]; 916 struct regpair qp_handle_for_cqe /* For use in CQEs */; 917 struct rdma_srq_id srq_id; 918 __le32 cq_cid_for_sq /* Cid of the CQ that will be posted from SQ */; 919 __le32 cq_cid_for_rq /* Cid of the CQ that will be posted from RQ */; 920 __le16 dpi; 921 __le16 physical_q0 /* Physical QM queue to be tied to logical Q0 */; 922 __le16 physical_q1 /* Physical QM queue to be tied to logical Q1 */; 923 u8 reserved2[6]; 924 }; 925 926 /* 927 * iWARP completion queue types 928 */ 929 enum iwarp_eqe_async_opcode 930 { 931 IWARP_EVENT_TYPE_ASYNC_CONNECT_COMPLETE /* Async completion oafter TCP 3-way handshake */, 932 IWARP_EVENT_TYPE_ASYNC_ENHANCED_MPA_REPLY_ARRIVED /* Enhanced MPA reply arrived. Driver should either send RTR or reject */, 933 IWARP_EVENT_TYPE_ASYNC_MPA_HANDSHAKE_COMPLETE /* MPA Negotiations completed */, 934 IWARP_EVENT_TYPE_ASYNC_CID_CLEANED /* Async completion that indicates to the driver that the CID can be re-used. */, 935 IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED /* Async EQE indicating detection of an error/exception on a QP at Firmware */, 936 IWARP_EVENT_TYPE_ASYNC_QP_IN_ERROR_STATE /* Async EQE indicating QP is in Error state. */, 937 IWARP_EVENT_TYPE_ASYNC_CQ_OVERFLOW /* Async EQE indicating CQ, whose handle is sent with this event, has overflowed */, 938 MAX_IWARP_EQE_ASYNC_OPCODE 939 }; 940 941 struct iwarp_eqe_data_mpa_async_completion 942 { 943 __le16 ulp_data_len /* On active side, length of ULP Data, from peers MPA Connect Response */; 944 u8 reserved[6]; 945 }; 946 947 struct iwarp_eqe_data_tcp_async_completion 948 { 949 __le16 ulp_data_len /* On passive side, length of ULP Data, from peers active MPA Connect Request */; 950 u8 mpa_handshake_mode /* Negotiation type Basic/Enhanced */; 951 u8 reserved[5]; 952 }; 953 954 /* 955 * iWARP completion queue types 956 */ 957 enum iwarp_eqe_sync_opcode 958 { 959 IWARP_EVENT_TYPE_TCP_OFFLOAD=11 /* iWARP event queue response after option 2 offload Ramrod */, 960 IWARP_EVENT_TYPE_MPA_OFFLOAD /* Synchronous completion for MPA offload Request */, 961 IWARP_EVENT_TYPE_MPA_OFFLOAD_SEND_RTR, 962 IWARP_EVENT_TYPE_CREATE_QP, 963 IWARP_EVENT_TYPE_QUERY_QP, 964 IWARP_EVENT_TYPE_MODIFY_QP, 965 IWARP_EVENT_TYPE_DESTROY_QP, 966 IWARP_EVENT_TYPE_ABORT_TCP_OFFLOAD, 967 MAX_IWARP_EQE_SYNC_OPCODE 968 }; 969 970 /* 971 * iWARP EQE completion status 972 */ 973 enum iwarp_fw_return_code 974 { 975 IWARP_CONN_ERROR_TCP_CONNECT_INVALID_PACKET=5 /* Got invalid packet SYN/SYN-ACK */, 976 IWARP_CONN_ERROR_TCP_CONNECTION_RST /* Got RST during offload TCP connection */, 977 IWARP_CONN_ERROR_TCP_CONNECT_TIMEOUT /* TCP connection setup timed out */, 978 IWARP_CONN_ERROR_MPA_ERROR_REJECT /* Got Reject in MPA reply. */, 979 IWARP_CONN_ERROR_MPA_NOT_SUPPORTED_VER /* Got MPA request with higher version that we support. */, 980 IWARP_CONN_ERROR_MPA_RST /* Got RST during MPA negotiation */, 981 IWARP_CONN_ERROR_MPA_FIN /* Got FIN during MPA negotiation */, 982 IWARP_CONN_ERROR_MPA_RTR_MISMATCH /* RTR mismatch detected when MPA reply arrived. */, 983 IWARP_CONN_ERROR_MPA_INSUF_IRD /* Insufficient IRD on the MPA reply that arrived. */, 984 IWARP_CONN_ERROR_MPA_INVALID_PACKET /* Incoming MPAp acket failed on FW verifications */, 985 IWARP_CONN_ERROR_MPA_LOCAL_ERROR /* Detected an internal error during MPA negotiation. */, 986 IWARP_CONN_ERROR_MPA_TIMEOUT /* MPA negotiation timed out. */, 987 IWARP_CONN_ERROR_MPA_TERMINATE /* Got Terminate during MPA negotiation. */, 988 IWARP_QP_IN_ERROR_GOOD_CLOSE /* LLP connection was closed gracefully - Used for async IWARP_EVENT_TYPE_ASYNC_QP_IN_ERROR_STATE */, 989 IWARP_QP_IN_ERROR_BAD_CLOSE /* LLP Connection was closed abortively - Used for async IWARP_EVENT_TYPE_ASYNC_QP_IN_ERROR_STATE */, 990 IWARP_EXCEPTION_DETECTED_LLP_CLOSED /* LLP has been disociated from the QP, although the TCP connection may not be closed yet - Used for async IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED */, 991 IWARP_EXCEPTION_DETECTED_LLP_RESET /* LLP has Reset (either because of an RST, or a bad-close condition) - Used for async IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED */, 992 IWARP_EXCEPTION_DETECTED_IRQ_FULL /* Peer sent more outstanding Read Requests than IRD - Used for async IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED */, 993 IWARP_EXCEPTION_DETECTED_RQ_EMPTY /* SEND request received with RQ empty - Used for async IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED */, 994 IWARP_EXCEPTION_DETECTED_SRQ_EMPTY /* SEND request received with SRQ empty - Used for async IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED */, 995 IWARP_EXCEPTION_DETECTED_SRQ_LIMIT /* Number of SRQ wqes is below the limit */, 996 IWARP_EXCEPTION_DETECTED_LLP_TIMEOUT /* TCP Retransmissions timed out - Used for async IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED */, 997 IWARP_EXCEPTION_DETECTED_REMOTE_PROTECTION_ERROR /* Peers Remote Access caused error */, 998 IWARP_EXCEPTION_DETECTED_CQ_OVERFLOW /* CQ overflow detected */, 999 IWARP_EXCEPTION_DETECTED_LOCAL_CATASTROPHIC /* Local catastrophic error detected - Used for async IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED */, 1000 IWARP_EXCEPTION_DETECTED_LOCAL_ACCESS_ERROR /* Local Access error detected while responding - Used for async IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED */, 1001 IWARP_EXCEPTION_DETECTED_REMOTE_OPERATION_ERROR /* An operation/protocol error caused by Remote Consumer */, 1002 IWARP_EXCEPTION_DETECTED_TERMINATE_RECEIVED /* Peer sent a TERMINATE message */, 1003 MAX_IWARP_FW_RETURN_CODE 1004 }; 1005 1006 /* 1007 * unaligned opaque data received from LL2 1008 */ 1009 struct iwarp_init_func_params 1010 { 1011 u8 ll2_ooo_q_index /* LL2 OOO queue id. The unaligned queue id will be + 1 */; 1012 u8 reserved1[7]; 1013 }; 1014 1015 /* 1016 * iwarp func init ramrod data 1017 */ 1018 struct iwarp_init_func_ramrod_data 1019 { 1020 struct rdma_init_func_ramrod_data rdma; 1021 struct tcp_init_params tcp; 1022 struct iwarp_init_func_params iwarp; 1023 }; 1024 1025 /* 1026 * iWARP QP - possible states to transition to 1027 */ 1028 enum iwarp_modify_qp_new_state_type 1029 { 1030 IWARP_MODIFY_QP_STATE_CLOSING=1 /* graceful close */, 1031 IWARP_MODIFY_QP_STATE_ERROR=2 /* abortive close, if LLP connection still exists */, 1032 MAX_IWARP_MODIFY_QP_NEW_STATE_TYPE 1033 }; 1034 1035 /* 1036 * iwarp modify qp responder ramrod data 1037 */ 1038 struct iwarp_modify_qp_ramrod_data 1039 { 1040 __le16 transition_to_state /* (use enum iwarp_modify_qp_new_state_type) */; 1041 __le16 flags; 1042 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1 1043 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT 0 1044 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1 1045 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT 1 1046 #define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1 1047 #define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_SHIFT 2 1048 #define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_MASK 0x1 /* change QP state as per transition_to_state field */ 1049 #define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_SHIFT 3 1050 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1 /* If set, the rdma_rd/wr/atomic_en should be updated */ 1051 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 4 1052 #define IWARP_MODIFY_QP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK 0x1 /* If set, the physicalQ1Val/physicalQ0Val/regularLatencyPhyQueue should be updated */ 1053 #define IWARP_MODIFY_QP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_SHIFT 5 1054 #define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_MASK 0x3FF 1055 #define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_SHIFT 6 1056 __le16 physical_q0 /* Updated physicalQ0Val */; 1057 __le16 physical_q1 /* Updated physicalQ1Val */; 1058 __le32 reserved1[10]; 1059 }; 1060 1061 /* 1062 * MPA params for Enhanced mode 1063 */ 1064 struct mpa_rq_params 1065 { 1066 __le32 ird; 1067 __le32 ord; 1068 }; 1069 1070 /* 1071 * MPA host Address-Len for private data 1072 */ 1073 struct mpa_ulp_buffer 1074 { 1075 struct regpair addr; 1076 __le16 len; 1077 __le16 reserved[3]; 1078 }; 1079 1080 /* 1081 * iWARP MPA offload params common to Basic and Enhanced modes 1082 */ 1083 struct mpa_outgoing_params 1084 { 1085 u8 crc_needed; 1086 u8 reject /* Valid only for passive side. */; 1087 u8 reserved[6]; 1088 struct mpa_rq_params out_rq; 1089 struct mpa_ulp_buffer outgoing_ulp_buffer /* ULP buffer populated by the host */; 1090 }; 1091 1092 /* 1093 * iWARP MPA offload params passed by driver to FW in MPA Offload Request Ramrod 1094 */ 1095 struct iwarp_mpa_offload_ramrod_data 1096 { 1097 struct mpa_outgoing_params common; 1098 __le32 tcp_cid; 1099 u8 mode /* Basic/Enhanced (use enum mpa_negotiation_mode) */; 1100 u8 tcp_connect_side /* Passive/Active. use enum tcp_connect_mode */; 1101 u8 rtr_pref; 1102 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_MASK 0x7 /* (use enum mpa_rtr_type) */ 1103 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_SHIFT 0 1104 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_MASK 0x1F 1105 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_SHIFT 3 1106 u8 reserved2; 1107 struct mpa_ulp_buffer incoming_ulp_buffer /* host buffer for placing the incoming MPA reply */; 1108 struct regpair async_eqe_output_buf /* host buffer for async tcp/mpa completion information - must have space for at least 8 bytes */; 1109 struct regpair handle_for_async /* a host cookie that will be echoed back with in every qp-specific async EQE */; 1110 struct regpair shared_queue_addr /* Address of shared queue address that consist of SQ/RQ and FW internal queues (IRQ/ORQ/HQ) */; 1111 __le16 rcv_wnd /* TCP window after scaling */; 1112 u8 stats_counter_id /* Statistics counter ID to use */; 1113 u8 reserved3[13]; 1114 }; 1115 1116 /* 1117 * iWARP TCP connection offload params passed by driver to FW 1118 */ 1119 struct iwarp_offload_params 1120 { 1121 struct mpa_ulp_buffer incoming_ulp_buffer /* host buffer for placing the incoming MPA request */; 1122 struct regpair async_eqe_output_buf /* host buffer for async tcp/mpa completion information - must have space for at least 8 bytes */; 1123 struct regpair handle_for_async /* host handle that will be echoed back with in every qp-specific async EQE */; 1124 __le16 physical_q0 /* Physical QM queue to be tied to logical Q0 */; 1125 __le16 physical_q1 /* Physical QM queue to be tied to logical Q1 */; 1126 u8 stats_counter_id /* Statistics counter ID to use */; 1127 u8 mpa_mode /* Basic/Enahnced. Used for a verification for incoming MPA request (use enum mpa_negotiation_mode) */; 1128 u8 reserved[10]; 1129 }; 1130 1131 /* 1132 * iWARP query QP output params 1133 */ 1134 struct iwarp_query_qp_output_params 1135 { 1136 __le32 flags; 1137 #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1 1138 #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0 1139 #define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF 1140 #define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_SHIFT 1 1141 u8 reserved1[4] /* 64 bit alignment */; 1142 }; 1143 1144 /* 1145 * iWARP query QP ramrod data 1146 */ 1147 struct iwarp_query_qp_ramrod_data 1148 { 1149 struct regpair output_params_addr; 1150 }; 1151 1152 /* 1153 * iWARP Ramrod Command IDs 1154 */ 1155 enum iwarp_ramrod_cmd_id 1156 { 1157 IWARP_RAMROD_CMD_ID_TCP_OFFLOAD=11 /* iWARP TCP connection offload ramrod */, 1158 IWARP_RAMROD_CMD_ID_MPA_OFFLOAD /* iWARP MPA offload ramrod */, 1159 IWARP_RAMROD_CMD_ID_MPA_OFFLOAD_SEND_RTR, 1160 IWARP_RAMROD_CMD_ID_CREATE_QP, 1161 IWARP_RAMROD_CMD_ID_QUERY_QP, 1162 IWARP_RAMROD_CMD_ID_MODIFY_QP, 1163 IWARP_RAMROD_CMD_ID_DESTROY_QP, 1164 IWARP_RAMROD_CMD_ID_ABORT_TCP_OFFLOAD, 1165 MAX_IWARP_RAMROD_CMD_ID 1166 }; 1167 1168 /* 1169 * Per PF iWARP retransmit path statistics 1170 */ 1171 struct iwarp_rxmit_stats_drv 1172 { 1173 struct regpair tx_go_to_slow_start_event_cnt /* Number of times slow start event occurred */; 1174 struct regpair tx_fast_retransmit_event_cnt /* Number of times fast retransmit event occurred */; 1175 }; 1176 1177 /* 1178 * iWARP and TCP connection offload params passed by driver to FW in iWARP offload ramrod 1179 */ 1180 struct iwarp_tcp_offload_ramrod_data 1181 { 1182 struct iwarp_offload_params iwarp /* iWARP connection offload params */; 1183 struct tcp_offload_params_opt2 tcp /* tcp offload params */; 1184 }; 1185 1186 /* 1187 * iWARP MPA negotiation types 1188 */ 1189 enum mpa_negotiation_mode 1190 { 1191 MPA_NEGOTIATION_TYPE_BASIC=1, 1192 MPA_NEGOTIATION_TYPE_ENHANCED=2, 1193 MAX_MPA_NEGOTIATION_MODE 1194 }; 1195 1196 /* 1197 * iWARP MPA Enhanced mode RTR types 1198 */ 1199 enum mpa_rtr_type 1200 { 1201 MPA_RTR_TYPE_NONE=0 /* No RTR type */, 1202 MPA_RTR_TYPE_ZERO_SEND=1, 1203 MPA_RTR_TYPE_ZERO_WRITE=2, 1204 MPA_RTR_TYPE_ZERO_SEND_AND_WRITE=3, 1205 MPA_RTR_TYPE_ZERO_READ=4, 1206 MPA_RTR_TYPE_ZERO_SEND_AND_READ=5, 1207 MPA_RTR_TYPE_ZERO_WRITE_AND_READ=6, 1208 MPA_RTR_TYPE_ZERO_SEND_AND_WRITE_AND_READ=7, 1209 MAX_MPA_RTR_TYPE 1210 }; 1211 1212 /* 1213 * unaligned opaque data received from LL2 1214 */ 1215 struct unaligned_opaque_data 1216 { 1217 __le16 first_mpa_offset /* offset of first MPA byte that should be processed */; 1218 u8 tcp_payload_offset /* offset of first the byte that comes after the last byte of the TCP Hdr */; 1219 u8 flags; 1220 #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_MASK 0x1 /* packet reached window right edge */ 1221 #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_SHIFT 0 1222 #define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_MASK 0x1 /* Indication that the connection is closed. Clean all connecitons database. */ 1223 #define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_SHIFT 1 1224 #define UNALIGNED_OPAQUE_DATA_RESERVED_MASK 0x3F 1225 #define UNALIGNED_OPAQUE_DATA_RESERVED_SHIFT 2 1226 __le32 cid; 1227 }; 1228 1229 struct e4_mstorm_iwarp_conn_ag_ctx 1230 { 1231 u8 reserved /* cdu_validation */; 1232 u8 state /* state */; 1233 u8 flags0; 1234 #define E4_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1235 #define E4_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1236 #define E4_MSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1237 #define E4_MSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 1238 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_MASK 0x3 /* cf0 */ 1239 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_SHIFT 2 1240 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1241 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4 1242 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1243 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6 1244 u8 flags1; 1245 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_MASK 0x1 /* cf0en */ 1246 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_SHIFT 0 1247 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1248 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1 1249 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1250 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2 1251 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1252 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3 1253 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1254 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4 1255 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1256 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5 1257 #define E4_MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_MASK 0x1 /* rule3en */ 1258 #define E4_MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_SHIFT 6 1259 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1260 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7 1261 __le16 rcq_cons /* word0 */; 1262 __le16 rcq_cons_th /* word1 */; 1263 __le32 reg0 /* reg0 */; 1264 __le32 reg1 /* reg1 */; 1265 }; 1266 1267 struct e4_ustorm_iwarp_conn_ag_ctx 1268 { 1269 u8 reserved /* cdu_validation */; 1270 u8 byte1 /* state */; 1271 u8 flags0; 1272 #define E4_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1273 #define E4_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1274 #define E4_USTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1275 #define E4_USTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 1276 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1277 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2 1278 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1279 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4 1280 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1281 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6 1282 u8 flags1; 1283 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1284 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3_SHIFT 0 1285 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3 /* cf4 */ 1286 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2 1287 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3 /* cf5 */ 1288 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4 1289 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1290 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 6 1291 u8 flags2; 1292 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1293 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0 1294 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1295 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1 1296 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1297 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2 1298 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1299 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3EN_SHIFT 3 1300 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1 /* cf4en */ 1301 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4 1302 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1 /* cf5en */ 1303 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5 1304 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1305 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 6 1306 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_MASK 0x1 /* rule0en */ 1307 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_SHIFT 7 1308 u8 flags3; 1309 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_EN_MASK 0x1 /* rule1en */ 1310 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_EN_SHIFT 0 1311 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1312 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1 1313 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1314 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2 1315 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1316 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3 1317 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1318 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4 1319 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1320 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 5 1321 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1322 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6 1323 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 1324 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7 1325 u8 byte2 /* byte2 */; 1326 u8 byte3 /* byte3 */; 1327 __le16 word0 /* conn_dpi */; 1328 __le16 word1 /* word1 */; 1329 __le32 cq_cons /* reg0 */; 1330 __le32 cq_se_prod /* reg1 */; 1331 __le32 cq_prod /* reg2 */; 1332 __le32 reg3 /* reg3 */; 1333 __le16 word2 /* word2 */; 1334 __le16 word3 /* word3 */; 1335 }; 1336 1337 struct e4_ystorm_iwarp_conn_ag_ctx 1338 { 1339 u8 byte0 /* cdu_validation */; 1340 u8 byte1 /* state */; 1341 u8 flags0; 1342 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1343 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT0_SHIFT 0 1344 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1345 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 1346 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1347 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2 1348 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1349 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4 1350 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1351 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6 1352 u8 flags1; 1353 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1354 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0 1355 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1356 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1 1357 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1358 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2 1359 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1360 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3 1361 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1362 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4 1363 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1364 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5 1365 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1366 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 6 1367 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1368 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7 1369 u8 byte2 /* byte2 */; 1370 u8 byte3 /* byte3 */; 1371 __le16 word0 /* word0 */; 1372 __le32 reg0 /* reg0 */; 1373 __le32 reg1 /* reg1 */; 1374 __le16 word1 /* word1 */; 1375 __le16 word2 /* word2 */; 1376 __le16 word3 /* word3 */; 1377 __le16 word4 /* word4 */; 1378 __le32 reg2 /* reg2 */; 1379 __le32 reg3 /* reg3 */; 1380 }; 1381 1382 struct e5_mstorm_iwarp_conn_ag_ctx 1383 { 1384 u8 reserved /* cdu_validation */; 1385 u8 state_and_core_id /* state_and_core_id */; 1386 u8 flags0; 1387 #define E5_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1388 #define E5_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1389 #define E5_MSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1390 #define E5_MSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 1391 #define E5_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_MASK 0x3 /* cf0 */ 1392 #define E5_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_SHIFT 2 1393 #define E5_MSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1394 #define E5_MSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4 1395 #define E5_MSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1396 #define E5_MSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6 1397 u8 flags1; 1398 #define E5_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_MASK 0x1 /* cf0en */ 1399 #define E5_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_SHIFT 0 1400 #define E5_MSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1401 #define E5_MSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1 1402 #define E5_MSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1403 #define E5_MSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2 1404 #define E5_MSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1405 #define E5_MSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3 1406 #define E5_MSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1407 #define E5_MSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4 1408 #define E5_MSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1409 #define E5_MSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5 1410 #define E5_MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_MASK 0x1 /* rule3en */ 1411 #define E5_MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_SHIFT 6 1412 #define E5_MSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1413 #define E5_MSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7 1414 __le16 rcq_cons /* word0 */; 1415 __le16 rcq_cons_th /* word1 */; 1416 __le32 reg0 /* reg0 */; 1417 __le32 reg1 /* reg1 */; 1418 }; 1419 1420 struct e5_ustorm_iwarp_conn_ag_ctx 1421 { 1422 u8 reserved /* cdu_validation */; 1423 u8 byte1 /* state_and_core_id */; 1424 u8 flags0; 1425 #define E5_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1426 #define E5_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1427 #define E5_USTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1428 #define E5_USTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 1429 #define E5_USTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1430 #define E5_USTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2 1431 #define E5_USTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1432 #define E5_USTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4 1433 #define E5_USTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1434 #define E5_USTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6 1435 u8 flags1; 1436 #define E5_USTORM_IWARP_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1437 #define E5_USTORM_IWARP_CONN_AG_CTX_CF3_SHIFT 0 1438 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3 /* cf4 */ 1439 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2 1440 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3 /* cf5 */ 1441 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4 1442 #define E5_USTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1443 #define E5_USTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 6 1444 u8 flags2; 1445 #define E5_USTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1446 #define E5_USTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0 1447 #define E5_USTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1448 #define E5_USTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1 1449 #define E5_USTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1450 #define E5_USTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2 1451 #define E5_USTORM_IWARP_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1452 #define E5_USTORM_IWARP_CONN_AG_CTX_CF3EN_SHIFT 3 1453 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1 /* cf4en */ 1454 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4 1455 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1 /* cf5en */ 1456 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5 1457 #define E5_USTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1458 #define E5_USTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 6 1459 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_MASK 0x1 /* rule0en */ 1460 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_SHIFT 7 1461 u8 flags3; 1462 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_EN_MASK 0x1 /* rule1en */ 1463 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_EN_SHIFT 0 1464 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1465 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1 1466 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1467 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2 1468 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1469 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3 1470 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1471 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4 1472 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1473 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 5 1474 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1475 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6 1476 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 1477 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7 1478 u8 flags4; 1479 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */ 1480 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 1481 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */ 1482 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 1483 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf7 */ 1484 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 1485 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf8 */ 1486 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED4_SHIFT 4 1487 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf7en */ 1488 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED5_SHIFT 6 1489 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf8en */ 1490 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED6_SHIFT 7 1491 u8 byte2 /* byte2 */; 1492 __le16 word0 /* conn_dpi */; 1493 __le16 word1 /* word1 */; 1494 __le32 cq_cons /* reg0 */; 1495 __le32 cq_se_prod /* reg1 */; 1496 __le32 cq_prod /* reg2 */; 1497 __le32 reg3 /* reg3 */; 1498 __le16 word2 /* word2 */; 1499 __le16 word3 /* word3 */; 1500 }; 1501 1502 struct e5_ystorm_iwarp_conn_ag_ctx 1503 { 1504 u8 byte0 /* cdu_validation */; 1505 u8 byte1 /* state_and_core_id */; 1506 u8 flags0; 1507 #define E5_YSTORM_IWARP_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1508 #define E5_YSTORM_IWARP_CONN_AG_CTX_BIT0_SHIFT 0 1509 #define E5_YSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1510 #define E5_YSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 1511 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1512 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2 1513 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1514 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4 1515 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1516 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6 1517 u8 flags1; 1518 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1519 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0 1520 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1521 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1 1522 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1523 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2 1524 #define E5_YSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1525 #define E5_YSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3 1526 #define E5_YSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1527 #define E5_YSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4 1528 #define E5_YSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1529 #define E5_YSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5 1530 #define E5_YSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1531 #define E5_YSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 6 1532 #define E5_YSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1533 #define E5_YSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7 1534 u8 byte2 /* byte2 */; 1535 u8 byte3 /* byte3 */; 1536 __le16 word0 /* word0 */; 1537 __le32 reg0 /* reg0 */; 1538 __le32 reg1 /* reg1 */; 1539 __le16 word1 /* word1 */; 1540 __le16 word2 /* word2 */; 1541 __le16 word3 /* word3 */; 1542 __le16 word4 /* word4 */; 1543 __le32 reg2 /* reg2 */; 1544 __le32 reg3 /* reg3 */; 1545 }; 1546 1547 #endif /* __ECORE_HSI_IWARP__ */ 1548