1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2007-2022 Intel Corporation */ 3 #ifndef ADF_CFG_COMMON_H_ 4 #define ADF_CFG_COMMON_H_ 5 6 #include <sys/types.h> 7 #include <sys/ioccom.h> 8 #include <sys/cpuset.h> 9 10 #define ADF_CFG_MAX_STR_LEN 128 11 #define ADF_CFG_MAX_KEY_LEN_IN_BYTES ADF_CFG_MAX_STR_LEN 12 /* 13 * Max value length increased to 128 to support more length of values. 14 * like Dc0CoreAffinity = 0, 1, 2,... config values to max cores 15 */ 16 #define ADF_CFG_MAX_VAL_LEN_IN_BYTES 128 17 #define ADF_CFG_MAX_SECTION_LEN_IN_BYTES ADF_CFG_MAX_STR_LEN 18 #define ADF_CFG_NULL_TERM_SIZE 1 19 #define ADF_CFG_BASE_DEC 10 20 #define ADF_CFG_BASE_HEX 16 21 #define ADF_CFG_ALL_DEVICES 0xFFFE 22 #define ADF_CFG_NO_DEVICE 0xFFFF 23 #define ADF_CFG_AFFINITY_WHATEVER 0xFF 24 #define MAX_DEVICE_NAME_SIZE 32 25 #define ADF_MAX_DEVICES (32 * 32) 26 #define ADF_MAX_ACCELENGINES 12 27 #define ADF_CFG_STORAGE_ENABLED 1 28 #define ADF_DEVS_ARRAY_SIZE BITS_TO_LONGS(ADF_MAX_DEVICES) 29 #define ADF_GEN2_SSM_WDT_PKE_DEFAULT_VALUE 0x3000000 30 #define ADF_WDT_TIMER_SYM_COMP_MS 3 31 #define ADF_MIN_HB_TIMER_MS 100 32 #define ADF_CFG_MAX_NUM_OF_SECTIONS 16 33 #define ADF_CFG_MAX_NUM_OF_TOKENS 16 34 #define ADF_CFG_MAX_TOKENS_IN_CONFIG 8 35 #define ADF_CFG_RESP_POLL 1 36 #define ADF_CFG_RESP_EPOLL 2 37 #define ADF_CFG_DEF_CY_RING_ASYM_SIZE 64 38 #define ADF_CFG_DEF_CY_RING_SYM_SIZE 512 39 #define ADF_CFG_DEF_DC_RING_SIZE 512 40 #define ADF_CFG_MAX_CORE_NUM 256 41 #define ADF_CFG_MAX_TOKENS ADF_CFG_MAX_CORE_NUM 42 #define ADF_CFG_MAX_TOKEN_LEN 10 43 #define ADF_CFG_ACCEL_DEF_COALES 1 44 #define ADF_CFG_ACCEL_DEF_COALES_TIMER 10000 45 #define ADF_CFG_ACCEL_DEF_COALES_NUM_MSG 0 46 #define ADF_CFG_ASYM_SRV_MASK 1 47 #define ADF_CFG_SYM_SRV_MASK 2 48 #define ADF_CFG_DC_SRV_MASK 8 49 #define ADF_CFG_UNKNOWN_SRV_MASK 0 50 #define ADF_CFG_DEF_ASYM_MASK 0x03 51 #define ADF_CFG_MAX_SERVICES 4 52 #define ADF_MAX_SERVICES 3 53 54 enum adf_svc_type { 55 ADF_SVC_ASYM = 0, 56 ADF_SVC_SYM = 1, 57 ADF_SVC_DC = 2, 58 ADF_SVC_NONE = 3 59 }; 60 61 struct adf_pci_address { 62 unsigned char bus; 63 unsigned char dev; 64 unsigned char func; 65 } __packed; 66 67 #define ADF_CFG_SERV_RING_PAIR_0_SHIFT 0 68 #define ADF_CFG_SERV_RING_PAIR_1_SHIFT 3 69 #define ADF_CFG_SERV_RING_PAIR_2_SHIFT 6 70 #define ADF_CFG_SERV_RING_PAIR_3_SHIFT 9 71 72 enum adf_cfg_service_type { NA = 0, CRYPTO, COMP, SYM, ASYM, USED }; 73 74 enum adf_cfg_bundle_type { FREE, KERNEL, USER }; 75 76 enum adf_cfg_val_type { ADF_DEC, ADF_HEX, ADF_STR }; 77 78 enum adf_device_type { 79 DEV_UNKNOWN = 0, 80 DEV_DH895XCC, 81 DEV_DH895XCCVF, 82 DEV_C62X, 83 DEV_C62XVF, 84 DEV_C3XXX, 85 DEV_C3XXXVF, 86 DEV_200XX, 87 DEV_200XXVF, 88 DEV_C4XXX, 89 DEV_C4XXXVF, 90 DEV_D15XX, 91 DEV_D15XXVF, 92 DEV_4XXX, 93 DEV_4XXXVF 94 }; 95 96 enum adf_cfg_fw_image_type { 97 ADF_FW_IMAGE_DEFAULT = 0, 98 ADF_FW_IMAGE_CRYPTO, 99 ADF_FW_IMAGE_COMPRESSION, 100 ADF_FW_IMAGE_CUSTOM1 101 }; 102 103 struct adf_dev_status_info { 104 enum adf_device_type type; 105 uint16_t accel_id; 106 uint16_t instance_id; 107 uint8_t num_ae; 108 uint8_t num_accel; 109 uint8_t num_logical_accel; 110 uint8_t banks_per_accel; 111 uint8_t state; 112 uint8_t bus; 113 uint8_t dev; 114 uint8_t fun; 115 int domain; 116 char name[MAX_DEVICE_NAME_SIZE]; 117 u8 sku; 118 u32 node_id; 119 u32 device_mem_available; 120 u32 pci_device_id; 121 }; 122 123 struct adf_cfg_device { 124 /* contains all the bundles info */ 125 struct adf_cfg_bundle **bundles; 126 /* contains all the instances info */ 127 struct adf_cfg_instance **instances; 128 int bundle_num; 129 int instance_index; 130 char name[ADF_CFG_MAX_STR_LEN]; 131 int dev_id; 132 int max_kernel_bundle_nr; 133 u16 total_num_inst; 134 }; 135 136 enum adf_accel_serv_type { 137 ADF_ACCEL_SERV_NA = 0x0, 138 ADF_ACCEL_SERV_ASYM, 139 ADF_ACCEL_SERV_SYM, 140 ADF_ACCEL_SERV_RND, 141 ADF_ACCEL_SERV_DC 142 }; 143 144 struct adf_cfg_ring { 145 u8 mode : 1; 146 enum adf_accel_serv_type serv_type; 147 u8 number : 4; 148 }; 149 150 struct adf_cfg_bundle { 151 /* Section(s) name this bundle is shared by */ 152 char **sections; 153 int max_section; 154 int section_index; 155 int number; 156 enum adf_cfg_bundle_type type; 157 cpuset_t affinity_mask; 158 int polling_mode; 159 int instance_num; 160 int num_of_rings; 161 /* contains all the info about rings */ 162 struct adf_cfg_ring **rings; 163 u16 in_use; 164 u16 max_cfg_svc_num; 165 }; 166 167 struct adf_cfg_instance { 168 enum adf_cfg_service_type stype; 169 char name[ADF_CFG_MAX_STR_LEN]; 170 int polling_mode; 171 cpuset_t affinity_mask; 172 /* rings within an instance for services */ 173 int asym_tx; 174 int asym_rx; 175 int sym_tx; 176 int sym_rx; 177 int dc_tx; 178 int dc_rx; 179 int bundle; 180 }; 181 182 #define ADF_CFG_MAX_CORE_NUM 256 183 #define ADF_CFG_MAX_TOKENS_IN_CONFIG 8 184 #define ADF_CFG_MAX_TOKEN_LEN 10 185 #define ADF_CFG_MAX_TOKENS ADF_CFG_MAX_CORE_NUM 186 #define ADF_CFG_ACCEL_DEF_COALES 1 187 #define ADF_CFG_ACCEL_DEF_COALES_TIMER 10000 188 #define ADF_CFG_ACCEL_DEF_COALES_NUM_MSG 0 189 #define ADF_CFG_RESP_EPOLL 2 190 #define ADF_CFG_SERV_RING_PAIR_1_SHIFT 3 191 #define ADF_CFG_SERV_RING_PAIR_2_SHIFT 6 192 #define ADF_CFG_SERV_RING_PAIR_3_SHIFT 9 193 #define ADF_CFG_RESP_POLL 1 194 #define ADF_CFG_ASYM_SRV_MASK 1 195 #define ADF_CFG_SYM_SRV_MASK 2 196 #define ADF_CFG_DC_SRV_MASK 8 197 #define ADF_CFG_UNKNOWN_SRV_MASK 0 198 #define ADF_CFG_DEF_ASYM_MASK 0x03 199 #define ADF_CFG_MAX_SERVICES 4 200 201 #define ADF_CTL_IOC_MAGIC 'a' 202 #define IOCTL_STATUS_ACCEL_DEV \ 203 _IOWR(ADF_CTL_IOC_MAGIC, 3, struct adf_dev_status_info) 204 #define IOCTL_RESERVE_RING \ 205 _IOWR(ADF_CTL_IOC_MAGIC, 10, struct adf_user_reserve_ring) 206 #define IOCTL_RELEASE_RING \ 207 _IOWR(ADF_CTL_IOC_MAGIC, 11, struct adf_user_reserve_ring) 208 #define IOCTL_ENABLE_RING \ 209 _IOWR(ADF_CTL_IOC_MAGIC, 12, struct adf_user_reserve_ring) 210 #define IOCTL_DISABLE_RING \ 211 _IOWR(ADF_CTL_IOC_MAGIC, 13, struct adf_user_reserve_ring) 212 #define IOCTL_GET_NUM_DEVICES _IOR(ADF_CTL_IOC_MAGIC, 4, int32_t) 213 #define ADF_CFG_HB_DEFAULT_VALUE 500 214 #define ADF_CFG_HB_COUNT_THRESHOLD 3 215 #define ADF_MIN_HB_TIMER_MS 100 216 #define IOCTL_GET_CFG_VAL \ 217 _IOW(ADF_CTL_IOC_MAGIC, 5, struct adf_user_cfg_ctl_data) 218 219 enum adf_device_heartbeat_status { 220 DEV_HB_UNRESPONSIVE = 0, 221 DEV_HB_ALIVE, 222 DEV_HB_UNSUPPORTED 223 }; 224 225 struct adf_dev_heartbeat_status_ctl { 226 uint16_t device_id; 227 enum adf_device_heartbeat_status status; 228 }; 229 #define IOCTL_HEARTBEAT_ACCEL_DEV \ 230 _IOWR(ADF_CTL_IOC_MAGIC, 9, struct adf_dev_heartbeat_status_ctl) 231 #endif 232