1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _VMM_DEV_H_ 30 #define _VMM_DEV_H_ 31 32 #include <machine/vmm.h> 33 #include <machine/vmm_snapshot.h> 34 35 struct vm_memmap { 36 vm_paddr_t gpa; 37 int segid; /* memory segment */ 38 vm_ooffset_t segoff; /* offset into memory segment */ 39 size_t len; /* mmap length */ 40 int prot; /* RWX */ 41 int flags; 42 }; 43 #define VM_MEMMAP_F_WIRED 0x01 44 #define VM_MEMMAP_F_IOMMU 0x02 45 46 struct vm_munmap { 47 vm_paddr_t gpa; 48 size_t len; 49 }; 50 51 #define VM_MEMSEG_NAME(m) ((m)->name[0] != '\0' ? (m)->name : NULL) 52 struct vm_memseg { 53 int segid; 54 size_t len; 55 char name[VM_MAX_SUFFIXLEN + 1]; 56 }; 57 58 struct vm_register { 59 int cpuid; 60 int regnum; /* enum vm_reg_name */ 61 uint64_t regval; 62 }; 63 64 struct vm_seg_desc { /* data or code segment */ 65 int cpuid; 66 int regnum; /* enum vm_reg_name */ 67 struct seg_desc desc; 68 }; 69 70 struct vm_register_set { 71 int cpuid; 72 unsigned int count; 73 const int *regnums; /* enum vm_reg_name */ 74 uint64_t *regvals; 75 }; 76 77 struct vm_run { 78 int cpuid; 79 cpuset_t *cpuset; /* CPU set storage */ 80 size_t cpusetsize; 81 struct vm_exit *vm_exit; 82 }; 83 84 struct vm_exception { 85 int cpuid; 86 int vector; 87 uint32_t error_code; 88 int error_code_valid; 89 int restart_instruction; 90 }; 91 92 struct vm_lapic_msi { 93 uint64_t msg; 94 uint64_t addr; 95 }; 96 97 struct vm_lapic_irq { 98 int cpuid; 99 int vector; 100 }; 101 102 struct vm_ioapic_irq { 103 int irq; 104 }; 105 106 struct vm_isa_irq { 107 int atpic_irq; 108 int ioapic_irq; 109 }; 110 111 struct vm_isa_irq_trigger { 112 int atpic_irq; 113 enum vm_intr_trigger trigger; 114 }; 115 116 struct vm_capability { 117 int cpuid; 118 enum vm_cap_type captype; 119 int capval; 120 int allcpus; 121 }; 122 123 struct vm_pptdev { 124 int bus; 125 int slot; 126 int func; 127 }; 128 129 struct vm_pptdev_mmio { 130 int bus; 131 int slot; 132 int func; 133 vm_paddr_t gpa; 134 vm_paddr_t hpa; 135 size_t len; 136 }; 137 138 struct vm_pptdev_msi { 139 int vcpu; /* unused */ 140 int bus; 141 int slot; 142 int func; 143 int numvec; /* 0 means disabled */ 144 uint64_t msg; 145 uint64_t addr; 146 }; 147 148 struct vm_pptdev_msix { 149 int vcpu; /* unused */ 150 int bus; 151 int slot; 152 int func; 153 int idx; 154 uint64_t msg; 155 uint32_t vector_control; 156 uint64_t addr; 157 }; 158 159 struct vm_nmi { 160 int cpuid; 161 }; 162 163 #define MAX_VM_STATS 64 164 struct vm_stats { 165 int cpuid; /* in */ 166 int index; /* in */ 167 int num_entries; /* out */ 168 struct timeval tv; 169 uint64_t statbuf[MAX_VM_STATS]; 170 }; 171 172 struct vm_stat_desc { 173 int index; /* in */ 174 char desc[128]; /* out */ 175 }; 176 177 struct vm_x2apic { 178 int cpuid; 179 enum x2apic_state state; 180 }; 181 182 struct vm_gpa_pte { 183 uint64_t gpa; /* in */ 184 uint64_t pte[4]; /* out */ 185 int ptenum; 186 }; 187 188 struct vm_hpet_cap { 189 uint32_t capabilities; /* lower 32 bits of HPET capabilities */ 190 }; 191 192 struct vm_suspend { 193 enum vm_suspend_how how; 194 }; 195 196 struct vm_gla2gpa { 197 int vcpuid; /* inputs */ 198 int prot; /* PROT_READ or PROT_WRITE */ 199 uint64_t gla; 200 struct vm_guest_paging paging; 201 int fault; /* outputs */ 202 uint64_t gpa; 203 }; 204 205 struct vm_activate_cpu { 206 int vcpuid; 207 }; 208 209 struct vm_cpuset { 210 int which; 211 int cpusetsize; 212 cpuset_t *cpus; 213 }; 214 #define VM_ACTIVE_CPUS 0 215 #define VM_SUSPENDED_CPUS 1 216 #define VM_DEBUG_CPUS 2 217 218 struct vm_intinfo { 219 int vcpuid; 220 uint64_t info1; 221 uint64_t info2; 222 }; 223 224 struct vm_rtc_time { 225 time_t secs; 226 }; 227 228 struct vm_rtc_data { 229 int offset; 230 uint8_t value; 231 }; 232 233 struct vm_cpu_topology { 234 uint16_t sockets; 235 uint16_t cores; 236 uint16_t threads; 237 uint16_t maxcpus; 238 }; 239 240 struct vm_readwrite_kernemu_device { 241 int vcpuid; 242 unsigned access_width : 3; 243 unsigned _unused : 29; 244 uint64_t gpa; 245 uint64_t value; 246 }; 247 _Static_assert(sizeof(struct vm_readwrite_kernemu_device) == 24, "ABI"); 248 249 enum { 250 /* general routines */ 251 IOCNUM_ABIVERS = 0, 252 IOCNUM_RUN = 1, 253 IOCNUM_SET_CAPABILITY = 2, 254 IOCNUM_GET_CAPABILITY = 3, 255 IOCNUM_SUSPEND = 4, 256 IOCNUM_REINIT = 5, 257 258 /* memory apis */ 259 IOCNUM_MAP_MEMORY = 10, /* deprecated */ 260 IOCNUM_GET_MEMORY_SEG = 11, /* deprecated */ 261 IOCNUM_GET_GPA_PMAP = 12, 262 IOCNUM_GLA2GPA = 13, 263 IOCNUM_ALLOC_MEMSEG = 14, 264 IOCNUM_GET_MEMSEG = 15, 265 IOCNUM_MMAP_MEMSEG = 16, 266 IOCNUM_MMAP_GETNEXT = 17, 267 IOCNUM_GLA2GPA_NOFAULT = 18, 268 IOCNUM_MUNMAP_MEMSEG = 19, 269 270 /* register/state accessors */ 271 IOCNUM_SET_REGISTER = 20, 272 IOCNUM_GET_REGISTER = 21, 273 IOCNUM_SET_SEGMENT_DESCRIPTOR = 22, 274 IOCNUM_GET_SEGMENT_DESCRIPTOR = 23, 275 IOCNUM_SET_REGISTER_SET = 24, 276 IOCNUM_GET_REGISTER_SET = 25, 277 IOCNUM_GET_KERNEMU_DEV = 26, 278 IOCNUM_SET_KERNEMU_DEV = 27, 279 280 /* interrupt injection */ 281 IOCNUM_GET_INTINFO = 28, 282 IOCNUM_SET_INTINFO = 29, 283 IOCNUM_INJECT_EXCEPTION = 30, 284 IOCNUM_LAPIC_IRQ = 31, 285 IOCNUM_INJECT_NMI = 32, 286 IOCNUM_IOAPIC_ASSERT_IRQ = 33, 287 IOCNUM_IOAPIC_DEASSERT_IRQ = 34, 288 IOCNUM_IOAPIC_PULSE_IRQ = 35, 289 IOCNUM_LAPIC_MSI = 36, 290 IOCNUM_LAPIC_LOCAL_IRQ = 37, 291 IOCNUM_IOAPIC_PINCOUNT = 38, 292 IOCNUM_RESTART_INSTRUCTION = 39, 293 294 /* PCI pass-thru */ 295 IOCNUM_BIND_PPTDEV = 40, 296 IOCNUM_UNBIND_PPTDEV = 41, 297 IOCNUM_MAP_PPTDEV_MMIO = 42, 298 IOCNUM_PPTDEV_MSI = 43, 299 IOCNUM_PPTDEV_MSIX = 44, 300 IOCNUM_PPTDEV_DISABLE_MSIX = 45, 301 IOCNUM_UNMAP_PPTDEV_MMIO = 46, 302 303 /* statistics */ 304 IOCNUM_VM_STATS = 50, 305 IOCNUM_VM_STAT_DESC = 51, 306 307 /* kernel device state */ 308 IOCNUM_SET_X2APIC_STATE = 60, 309 IOCNUM_GET_X2APIC_STATE = 61, 310 IOCNUM_GET_HPET_CAPABILITIES = 62, 311 312 /* CPU Topology */ 313 IOCNUM_SET_TOPOLOGY = 63, 314 IOCNUM_GET_TOPOLOGY = 64, 315 316 /* legacy interrupt injection */ 317 IOCNUM_ISA_ASSERT_IRQ = 80, 318 IOCNUM_ISA_DEASSERT_IRQ = 81, 319 IOCNUM_ISA_PULSE_IRQ = 82, 320 IOCNUM_ISA_SET_IRQ_TRIGGER = 83, 321 322 /* vm_cpuset */ 323 IOCNUM_ACTIVATE_CPU = 90, 324 IOCNUM_GET_CPUSET = 91, 325 IOCNUM_SUSPEND_CPU = 92, 326 IOCNUM_RESUME_CPU = 93, 327 328 /* RTC */ 329 IOCNUM_RTC_READ = 100, 330 IOCNUM_RTC_WRITE = 101, 331 IOCNUM_RTC_SETTIME = 102, 332 IOCNUM_RTC_GETTIME = 103, 333 334 /* checkpoint */ 335 IOCNUM_SNAPSHOT_REQ = 113, 336 337 IOCNUM_RESTORE_TIME = 115 338 }; 339 340 #define VM_RUN \ 341 _IOW('v', IOCNUM_RUN, struct vm_run) 342 #define VM_SUSPEND \ 343 _IOW('v', IOCNUM_SUSPEND, struct vm_suspend) 344 #define VM_REINIT \ 345 _IO('v', IOCNUM_REINIT) 346 #define VM_ALLOC_MEMSEG \ 347 _IOW('v', IOCNUM_ALLOC_MEMSEG, struct vm_memseg) 348 #define VM_GET_MEMSEG \ 349 _IOWR('v', IOCNUM_GET_MEMSEG, struct vm_memseg) 350 #define VM_MMAP_MEMSEG \ 351 _IOW('v', IOCNUM_MMAP_MEMSEG, struct vm_memmap) 352 #define VM_MMAP_GETNEXT \ 353 _IOWR('v', IOCNUM_MMAP_GETNEXT, struct vm_memmap) 354 #define VM_MUNMAP_MEMSEG \ 355 _IOW('v', IOCNUM_MUNMAP_MEMSEG, struct vm_munmap) 356 #define VM_SET_REGISTER \ 357 _IOW('v', IOCNUM_SET_REGISTER, struct vm_register) 358 #define VM_GET_REGISTER \ 359 _IOWR('v', IOCNUM_GET_REGISTER, struct vm_register) 360 #define VM_SET_SEGMENT_DESCRIPTOR \ 361 _IOW('v', IOCNUM_SET_SEGMENT_DESCRIPTOR, struct vm_seg_desc) 362 #define VM_GET_SEGMENT_DESCRIPTOR \ 363 _IOWR('v', IOCNUM_GET_SEGMENT_DESCRIPTOR, struct vm_seg_desc) 364 #define VM_SET_REGISTER_SET \ 365 _IOW('v', IOCNUM_SET_REGISTER_SET, struct vm_register_set) 366 #define VM_GET_REGISTER_SET \ 367 _IOWR('v', IOCNUM_GET_REGISTER_SET, struct vm_register_set) 368 #define VM_SET_KERNEMU_DEV \ 369 _IOW('v', IOCNUM_SET_KERNEMU_DEV, \ 370 struct vm_readwrite_kernemu_device) 371 #define VM_GET_KERNEMU_DEV \ 372 _IOWR('v', IOCNUM_GET_KERNEMU_DEV, \ 373 struct vm_readwrite_kernemu_device) 374 #define VM_INJECT_EXCEPTION \ 375 _IOW('v', IOCNUM_INJECT_EXCEPTION, struct vm_exception) 376 #define VM_LAPIC_IRQ \ 377 _IOW('v', IOCNUM_LAPIC_IRQ, struct vm_lapic_irq) 378 #define VM_LAPIC_LOCAL_IRQ \ 379 _IOW('v', IOCNUM_LAPIC_LOCAL_IRQ, struct vm_lapic_irq) 380 #define VM_LAPIC_MSI \ 381 _IOW('v', IOCNUM_LAPIC_MSI, struct vm_lapic_msi) 382 #define VM_IOAPIC_ASSERT_IRQ \ 383 _IOW('v', IOCNUM_IOAPIC_ASSERT_IRQ, struct vm_ioapic_irq) 384 #define VM_IOAPIC_DEASSERT_IRQ \ 385 _IOW('v', IOCNUM_IOAPIC_DEASSERT_IRQ, struct vm_ioapic_irq) 386 #define VM_IOAPIC_PULSE_IRQ \ 387 _IOW('v', IOCNUM_IOAPIC_PULSE_IRQ, struct vm_ioapic_irq) 388 #define VM_IOAPIC_PINCOUNT \ 389 _IOR('v', IOCNUM_IOAPIC_PINCOUNT, int) 390 #define VM_ISA_ASSERT_IRQ \ 391 _IOW('v', IOCNUM_ISA_ASSERT_IRQ, struct vm_isa_irq) 392 #define VM_ISA_DEASSERT_IRQ \ 393 _IOW('v', IOCNUM_ISA_DEASSERT_IRQ, struct vm_isa_irq) 394 #define VM_ISA_PULSE_IRQ \ 395 _IOW('v', IOCNUM_ISA_PULSE_IRQ, struct vm_isa_irq) 396 #define VM_ISA_SET_IRQ_TRIGGER \ 397 _IOW('v', IOCNUM_ISA_SET_IRQ_TRIGGER, struct vm_isa_irq_trigger) 398 #define VM_SET_CAPABILITY \ 399 _IOW('v', IOCNUM_SET_CAPABILITY, struct vm_capability) 400 #define VM_GET_CAPABILITY \ 401 _IOWR('v', IOCNUM_GET_CAPABILITY, struct vm_capability) 402 #define VM_BIND_PPTDEV \ 403 _IOW('v', IOCNUM_BIND_PPTDEV, struct vm_pptdev) 404 #define VM_UNBIND_PPTDEV \ 405 _IOW('v', IOCNUM_UNBIND_PPTDEV, struct vm_pptdev) 406 #define VM_MAP_PPTDEV_MMIO \ 407 _IOW('v', IOCNUM_MAP_PPTDEV_MMIO, struct vm_pptdev_mmio) 408 #define VM_PPTDEV_MSI \ 409 _IOW('v', IOCNUM_PPTDEV_MSI, struct vm_pptdev_msi) 410 #define VM_PPTDEV_MSIX \ 411 _IOW('v', IOCNUM_PPTDEV_MSIX, struct vm_pptdev_msix) 412 #define VM_PPTDEV_DISABLE_MSIX \ 413 _IOW('v', IOCNUM_PPTDEV_DISABLE_MSIX, struct vm_pptdev) 414 #define VM_UNMAP_PPTDEV_MMIO \ 415 _IOW('v', IOCNUM_UNMAP_PPTDEV_MMIO, struct vm_pptdev_mmio) 416 #define VM_INJECT_NMI \ 417 _IOW('v', IOCNUM_INJECT_NMI, struct vm_nmi) 418 #define VM_STATS \ 419 _IOWR('v', IOCNUM_VM_STATS, struct vm_stats) 420 #define VM_STAT_DESC \ 421 _IOWR('v', IOCNUM_VM_STAT_DESC, struct vm_stat_desc) 422 #define VM_SET_X2APIC_STATE \ 423 _IOW('v', IOCNUM_SET_X2APIC_STATE, struct vm_x2apic) 424 #define VM_GET_X2APIC_STATE \ 425 _IOWR('v', IOCNUM_GET_X2APIC_STATE, struct vm_x2apic) 426 #define VM_GET_HPET_CAPABILITIES \ 427 _IOR('v', IOCNUM_GET_HPET_CAPABILITIES, struct vm_hpet_cap) 428 #define VM_SET_TOPOLOGY \ 429 _IOW('v', IOCNUM_SET_TOPOLOGY, struct vm_cpu_topology) 430 #define VM_GET_TOPOLOGY \ 431 _IOR('v', IOCNUM_GET_TOPOLOGY, struct vm_cpu_topology) 432 #define VM_GET_GPA_PMAP \ 433 _IOWR('v', IOCNUM_GET_GPA_PMAP, struct vm_gpa_pte) 434 #define VM_GLA2GPA \ 435 _IOWR('v', IOCNUM_GLA2GPA, struct vm_gla2gpa) 436 #define VM_GLA2GPA_NOFAULT \ 437 _IOWR('v', IOCNUM_GLA2GPA_NOFAULT, struct vm_gla2gpa) 438 #define VM_ACTIVATE_CPU \ 439 _IOW('v', IOCNUM_ACTIVATE_CPU, struct vm_activate_cpu) 440 #define VM_GET_CPUS \ 441 _IOW('v', IOCNUM_GET_CPUSET, struct vm_cpuset) 442 #define VM_SUSPEND_CPU \ 443 _IOW('v', IOCNUM_SUSPEND_CPU, struct vm_activate_cpu) 444 #define VM_RESUME_CPU \ 445 _IOW('v', IOCNUM_RESUME_CPU, struct vm_activate_cpu) 446 #define VM_SET_INTINFO \ 447 _IOW('v', IOCNUM_SET_INTINFO, struct vm_intinfo) 448 #define VM_GET_INTINFO \ 449 _IOWR('v', IOCNUM_GET_INTINFO, struct vm_intinfo) 450 #define VM_RTC_WRITE \ 451 _IOW('v', IOCNUM_RTC_WRITE, struct vm_rtc_data) 452 #define VM_RTC_READ \ 453 _IOWR('v', IOCNUM_RTC_READ, struct vm_rtc_data) 454 #define VM_RTC_SETTIME \ 455 _IOW('v', IOCNUM_RTC_SETTIME, struct vm_rtc_time) 456 #define VM_RTC_GETTIME \ 457 _IOR('v', IOCNUM_RTC_GETTIME, struct vm_rtc_time) 458 #define VM_RESTART_INSTRUCTION \ 459 _IOW('v', IOCNUM_RESTART_INSTRUCTION, int) 460 #define VM_SNAPSHOT_REQ \ 461 _IOWR('v', IOCNUM_SNAPSHOT_REQ, struct vm_snapshot_meta) 462 #define VM_RESTORE_TIME \ 463 _IOWR('v', IOCNUM_RESTORE_TIME, int) 464 #endif 465