1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_INTEL_FAMILY_H 3 #define _ASM_X86_INTEL_FAMILY_H 4 5 /* 6 * "Big Core" Processors (Branded as Core, Xeon, etc...) 7 * 8 * While adding a new CPUID for a new microarchitecture, add a new 9 * group to keep logically sorted out in chronological order. Within 10 * that group keep the CPUID for the variants sorted by model number. 11 * 12 * The defined symbol names have the following form: 13 * INTEL_{OPTFAMILY}_{MICROARCH}{OPTDIFF} 14 * where: 15 * OPTFAMILY Describes the family of CPUs that this belongs to. Default 16 * is assumed to be "_CORE" (and should be omitted). Other values 17 * currently in use are _ATOM and _XEON_PHI 18 * MICROARCH Is the code name for the micro-architecture for this core. 19 * N.B. Not the platform name. 20 * OPTDIFF If needed, a short string to differentiate by market segment. 21 * 22 * Common OPTDIFFs: 23 * 24 * - regular client parts 25 * _L - regular mobile parts 26 * _G - parts with extra graphics on 27 * _X - regular server parts 28 * _D - micro server parts 29 * _N,_P - other mobile parts 30 * _H - premium mobile parts 31 * _S - other client parts 32 * 33 * Historical OPTDIFFs: 34 * 35 * _EP - 2 socket server parts 36 * _EX - 4+ socket server parts 37 * 38 * The #define line may optionally include a comment including platform or core 39 * names. An exception is made for skylake/kabylake where steppings seem to have gotten 40 * their own names :-( 41 */ 42 43 #define IFM(_fam, _model) VFM_MAKE(X86_VENDOR_INTEL, _fam, _model) 44 45 /* Wildcard match so X86_MATCH_VFM(ANY) works */ 46 #define INTEL_ANY IFM(X86_FAMILY_ANY, X86_MODEL_ANY) 47 48 #define INTEL_PENTIUM_PRO IFM(6, 0x01) 49 50 #define INTEL_CORE_YONAH IFM(6, 0x0E) 51 52 #define INTEL_CORE2_MEROM IFM(6, 0x0F) 53 #define INTEL_CORE2_MEROM_L IFM(6, 0x16) 54 #define INTEL_CORE2_PENRYN IFM(6, 0x17) 55 #define INTEL_CORE2_DUNNINGTON IFM(6, 0x1D) 56 57 #define INTEL_NEHALEM IFM(6, 0x1E) 58 #define INTEL_NEHALEM_G IFM(6, 0x1F) /* Auburndale / Havendale */ 59 #define INTEL_NEHALEM_EP IFM(6, 0x1A) 60 #define INTEL_NEHALEM_EX IFM(6, 0x2E) 61 62 #define INTEL_WESTMERE IFM(6, 0x25) 63 #define INTEL_WESTMERE_EP IFM(6, 0x2C) 64 #define INTEL_WESTMERE_EX IFM(6, 0x2F) 65 66 #define INTEL_SANDYBRIDGE IFM(6, 0x2A) 67 #define INTEL_SANDYBRIDGE_X IFM(6, 0x2D) 68 #define INTEL_IVYBRIDGE IFM(6, 0x3A) 69 #define INTEL_IVYBRIDGE_X IFM(6, 0x3E) 70 71 #define INTEL_HASWELL IFM(6, 0x3C) 72 #define INTEL_HASWELL_X IFM(6, 0x3F) 73 #define INTEL_HASWELL_L IFM(6, 0x45) 74 #define INTEL_HASWELL_G IFM(6, 0x46) 75 76 #define INTEL_BROADWELL IFM(6, 0x3D) 77 #define INTEL_BROADWELL_G IFM(6, 0x47) 78 #define INTEL_BROADWELL_X IFM(6, 0x4F) 79 #define INTEL_BROADWELL_D IFM(6, 0x56) 80 81 #define INTEL_SKYLAKE_L IFM(6, 0x4E) /* Sky Lake */ 82 #define INTEL_SKYLAKE IFM(6, 0x5E) /* Sky Lake */ 83 #define INTEL_SKYLAKE_X IFM(6, 0x55) /* Sky Lake */ 84 /* CASCADELAKE_X 0x55 Sky Lake -- s: 7 */ 85 /* COOPERLAKE_X 0x55 Sky Lake -- s: 11 */ 86 87 #define INTEL_KABYLAKE_L IFM(6, 0x8E) /* Sky Lake */ 88 /* AMBERLAKE_L 0x8E Sky Lake -- s: 9 */ 89 /* COFFEELAKE_L 0x8E Sky Lake -- s: 10 */ 90 /* WHISKEYLAKE_L 0x8E Sky Lake -- s: 11,12 */ 91 92 #define INTEL_KABYLAKE IFM(6, 0x9E) /* Sky Lake */ 93 /* COFFEELAKE 0x9E Sky Lake -- s: 10-13 */ 94 95 #define INTEL_COMETLAKE IFM(6, 0xA5) /* Sky Lake */ 96 #define INTEL_COMETLAKE_L IFM(6, 0xA6) /* Sky Lake */ 97 98 #define INTEL_CANNONLAKE_L IFM(6, 0x66) /* Palm Cove */ 99 100 #define INTEL_ICELAKE_X IFM(6, 0x6A) /* Sunny Cove */ 101 #define INTEL_ICELAKE_D IFM(6, 0x6C) /* Sunny Cove */ 102 #define INTEL_ICELAKE IFM(6, 0x7D) /* Sunny Cove */ 103 #define INTEL_ICELAKE_L IFM(6, 0x7E) /* Sunny Cove */ 104 #define INTEL_ICELAKE_NNPI IFM(6, 0x9D) /* Sunny Cove */ 105 106 #define INTEL_ROCKETLAKE IFM(6, 0xA7) /* Cypress Cove */ 107 108 #define INTEL_TIGERLAKE_L IFM(6, 0x8C) /* Willow Cove */ 109 #define INTEL_TIGERLAKE IFM(6, 0x8D) /* Willow Cove */ 110 111 #define INTEL_SAPPHIRERAPIDS_X IFM(6, 0x8F) /* Golden Cove */ 112 113 #define INTEL_EMERALDRAPIDS_X IFM(6, 0xCF) 114 115 #define INTEL_GRANITERAPIDS_X IFM(6, 0xAD) 116 #define INTEL_GRANITERAPIDS_D IFM(6, 0xAE) 117 118 /* "Hybrid" Processors (P-Core/E-Core) */ 119 120 #define INTEL_LAKEFIELD IFM(6, 0x8A) /* Sunny Cove / Tremont */ 121 122 #define INTEL_ALDERLAKE IFM(6, 0x97) /* Golden Cove / Gracemont */ 123 #define INTEL_ALDERLAKE_L IFM(6, 0x9A) /* Golden Cove / Gracemont */ 124 125 #define INTEL_RAPTORLAKE IFM(6, 0xB7) /* Raptor Cove / Enhanced Gracemont */ 126 #define INTEL_RAPTORLAKE_P IFM(6, 0xBA) 127 #define INTEL_RAPTORLAKE_S IFM(6, 0xBF) 128 129 #define INTEL_METEORLAKE IFM(6, 0xAC) 130 #define INTEL_METEORLAKE_L IFM(6, 0xAA) 131 132 #define INTEL_ARROWLAKE_H IFM(6, 0xC5) 133 #define INTEL_ARROWLAKE IFM(6, 0xC6) 134 #define INTEL_ARROWLAKE_U IFM(6, 0xB5) 135 136 #define INTEL_LUNARLAKE_M IFM(6, 0xBD) 137 138 /* "Small Core" Processors (Atom/E-Core) */ 139 140 #define INTEL_ATOM_BONNELL IFM(6, 0x1C) /* Diamondville, Pineview */ 141 #define INTEL_ATOM_BONNELL_MID IFM(6, 0x26) /* Silverthorne, Lincroft */ 142 143 #define INTEL_ATOM_SALTWELL IFM(6, 0x36) /* Cedarview */ 144 #define INTEL_ATOM_SALTWELL_MID IFM(6, 0x27) /* Penwell */ 145 #define INTEL_ATOM_SALTWELL_TABLET IFM(6, 0x35) /* Cloverview */ 146 147 #define INTEL_ATOM_SILVERMONT IFM(6, 0x37) /* Bay Trail, Valleyview */ 148 #define INTEL_ATOM_SILVERMONT_D IFM(6, 0x4D) /* Avaton, Rangely */ 149 #define INTEL_ATOM_SILVERMONT_MID IFM(6, 0x4A) /* Merriefield */ 150 151 #define INTEL_ATOM_AIRMONT IFM(6, 0x4C) /* Cherry Trail, Braswell */ 152 #define INTEL_ATOM_AIRMONT_MID IFM(6, 0x5A) /* Moorefield */ 153 #define INTEL_ATOM_AIRMONT_NP IFM(6, 0x75) /* Lightning Mountain */ 154 155 #define INTEL_ATOM_GOLDMONT IFM(6, 0x5C) /* Apollo Lake */ 156 #define INTEL_ATOM_GOLDMONT_D IFM(6, 0x5F) /* Denverton */ 157 158 /* Note: the micro-architecture is "Goldmont Plus" */ 159 #define INTEL_ATOM_GOLDMONT_PLUS IFM(6, 0x7A) /* Gemini Lake */ 160 161 #define INTEL_ATOM_TREMONT_D IFM(6, 0x86) /* Jacobsville */ 162 #define INTEL_ATOM_TREMONT IFM(6, 0x96) /* Elkhart Lake */ 163 #define INTEL_ATOM_TREMONT_L IFM(6, 0x9C) /* Jasper Lake */ 164 165 #define INTEL_ATOM_GRACEMONT IFM(6, 0xBE) /* Alderlake N */ 166 167 #define INTEL_ATOM_CRESTMONT_X IFM(6, 0xAF) /* Sierra Forest */ 168 #define INTEL_ATOM_CRESTMONT IFM(6, 0xB6) /* Grand Ridge */ 169 170 #define INTEL_ATOM_DARKMONT_X IFM(6, 0xDD) /* Clearwater Forest */ 171 172 /* Xeon Phi */ 173 174 #define INTEL_XEON_PHI_KNL IFM(6, 0x57) /* Knights Landing */ 175 #define INTEL_XEON_PHI_KNM IFM(6, 0x85) /* Knights Mill */ 176 177 /* Family 5 */ 178 #define INTEL_FAM5_QUARK_X1000 0x09 /* Quark X1000 SoC */ 179 #define INTEL_QUARK_X1000 IFM(5, 0x09) /* Quark X1000 SoC */ 180 181 #endif /* _ASM_X86_INTEL_FAMILY_H */ 182