xref: /titanic_41/usr/src/uts/common/sys/agp/agpdefs.h (revision 2e6e901d9406e1a048063c872149376a6bf7cb63)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright (c) 2009, Intel Corporation.
24  * All Rights Reserved.
25  */
26 
27 /*
28  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
29  * Use is subject to license terms.
30  */
31 
32 #ifndef _SYS_AGPDEFS_H
33 #define	_SYS_AGPDEFS_H
34 
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38 
39 /*
40  * This AGP memory type is required by some hardware like i810 video
41  * card, which need physical contiguous pages to setup hardware cursor.
42  * Usually, several tens of kilo bytes are needed in this case.
43  * We use DDI DMA interfaces to allocate such memory in agpgart driver,
44  * and it can not be exported to user applications directly by calling mmap
45  * on agpgart driver. The typical usage scenario is as the following:
46  * Firstly, Xserver get the memory physical address by calling AGPIOC_ALLOCATE
47  * on agpgart driver. Secondly, Xserver use the physical address to mmap
48  * the memory to Xserver space area by xsvc driver.
49  *
50  */
51 #define	AGP_PHYSICAL		2	/* Only used for i810, HW curosr */
52 
53 #ifdef _KERNEL
54 
55 /* AGP space units */
56 #define	AGP_PAGE_SHIFT			12
57 #define	AGP_PAGE_SIZE			(1 << AGP_PAGE_SHIFT)
58 #define	AGP_PAGE_OFFSET			(AGP_PAGE_SIZE - 1)
59 #define	AGP_MB2PAGES(x)			((x) << 8)
60 #define	AGP_PAGES2BYTES(x)		((x) << AGP_PAGE_SHIFT)
61 #define	AGP_BYTES2PAGES(x)		((x) >> AGP_PAGE_SHIFT)
62 #define	AGP_PAGES2KB(x)			((x) << 2)
63 #define	AGP_ALIGNED(offset)		(((offset) & AGP_PAGE_OFFSET) == 0)
64 
65 /* stand pci register offset */
66 #define	PCI_CONF_CAP_MASK		0x10
67 #define	PCI_CONF_CAPID_MASK		0xff
68 #define	PCI_CONF_NCAPID_MASK		0xff00
69 
70 #define	INTEL_VENDOR_ID			0x8086
71 #define	AMD_VENDOR_ID			0x1022
72 #define	VENDOR_ID_MASK			0xffff
73 
74 /* macros for device types */
75 #define	DEVICE_IS_I810		11 /* intel i810 series video card */
76 #define	DEVICE_IS_I830		12 /* intel i830, i845, i855 series */
77 #define	DEVICE_IS_AGP		21 /* external AGP video card */
78 #define	CHIP_IS_INTEL		10 /* intel agp bridge */
79 #define	CHIP_IS_AMD		20 /* amd agp bridge */
80 
81 /* AGP bridge device id */
82 #define	AMD_BR_8151			0x74541022
83 #define	INTEL_BR_810			0x71208086
84 #define	INTEL_BR_810DC			0x71228086
85 #define	INTEL_BR_810E			0x71248086
86 #define	INTEL_BR_815			0x11308086 /* include 815G/EG/P/EP */
87 #define	INTEL_BR_830M			0x35758086
88 #define	INTEL_BR_845			0x25608086 /* include 845G/P */
89 #define	INTEL_BR_855GM			0x35808086 /* include 852GM/PM */
90 #define	INTEL_BR_855PM			0x33408086
91 #define	INTEL_BR_865			0x25708086
92 #define	INTEL_BR_915			0x25808086
93 #define	INTEL_BR_915GM			0x25908086
94 #define	INTEL_BR_945			0x27708086
95 #define	INTEL_BR_945GM			0x27a08086
96 #define	INTEL_BR_945GME			0x27ac8086
97 #define	INTEL_BR_946GZ			0x29708086
98 #define	INTEL_BR_965G1			0x29808086
99 #define	INTEL_BR_965Q			0x29908086
100 #define	INTEL_BR_965G2			0x29a08086
101 #define	INTEL_BR_965GM			0x2a008086
102 #define	INTEL_BR_965GME			0x2a108086
103 #define	INTEL_BR_Q35			0x29b08086
104 #define	INTEL_BR_G33			0x29c08086
105 #define	INTEL_BR_Q33			0x29d08086
106 #define	INTEL_BR_GM45			0x2a408086
107 #define	INTEL_BR_EL			0x2e008086
108 #define	INTEL_BR_Q45			0x2e108086
109 #define	INTEL_BR_G45			0x2e208086
110 #define	INTEL_BR_G41			0x2e308086
111 #define	INTEL_BR_IGDNG_D		0x00408086
112 #define	INTEL_BR_IGDNG_M		0x00448086
113 #define	INTEL_BR_IGDNG_MA		0x00628086
114 #define	INTEL_BR_IGDNG_MC2		0x006a8086
115 #define	INTEL_BR_B43			0x2e408086
116 
117 /* AGP common register offset in pci configuration space */
118 #define	AGP_CONF_MISC			0x51 /* one byte */
119 #define	AGP_CONF_CAPPTR			0x34
120 #define	AGP_CONF_APERBASE		0x10
121 #define	AGP_CONF_STATUS			0x04 /* CAP + 0x4 */
122 #define	AGP_CONF_COMMAND		0x08 /* CAP + 0x8 */
123 
124 /* AGP target register and mask defines */
125 #define	AGP_CONF_CONTROL		0x10 /* CAP + 0x10 */
126 #define	AGP_TARGET_BAR1			1
127 #define	AGP_32_APERBASE_MASK		0xffc00000 /* 4M aligned */
128 #define	AGP_64_APERBASE_MASK		0xffffc00000LL /* 4M aligned */
129 #define	AGP_CONF_APERSIZE		0x14 /* CAP + 0x14 */
130 #define	AGP_CONF_ATTBASE		0x18 /* CAP + 0x18 */
131 #define	AGP_ATTBASE_MASK		0xfffff000
132 #define	AGPCTRL_GTLBEN			(0x1 << 7)
133 #define	AGP_APER_TYPE_MASK		0x4
134 #define	AGP_APER_SIZE_MASK		0xf00
135 #define	AGP_APER_128M_MASK		0x3f
136 #define	AGP_APER_4G_MASK		0xf00
137 #define	AGP_APER_4M			0x3f
138 #define	AGP_APER_8M			0x3e
139 #define	AGP_APER_16M			0x3c
140 #define	AGP_APER_32M			0x38
141 #define	AGP_APER_64M			0x30
142 #define	AGP_APER_128M			0x20
143 #define	AGP_APER_256M			0xf00
144 #define	AGP_APER_512M			0xe00
145 #define	AGP_APER_1024M			0xc00
146 #define	AGP_APER_2048M			0x800
147 #define	AGP_APER_4G			0x000
148 #define	AGP_MISC_APEN			0x2
149 
150 /* AGP gart table definition */
151 #define	AGP_ENTRY_VALID			0x1
152 
153 /* AGP term definitions */
154 #define	AGP_CAP_ID			0x2
155 #define	AGP_CAP_OFF_DEF			0xa0
156 
157 /* Intel integrated video card, chipset id */
158 #define	INTEL_IGD_810			0x71218086
159 #define	INTEL_IGD_810DC			0x71238086
160 #define	INTEL_IGD_810E			0x71258086
161 #define	INTEL_IGD_815			0x11328086
162 #define	INTEL_IGD_830M			0x35778086
163 #define	INTEL_IGD_845G			0x25628086
164 #define	INTEL_IGD_855GM			0x35828086
165 #define	INTEL_IGD_865G			0x25728086
166 #define	INTEL_IGD_915			0x25828086
167 #define	INTEL_IGD_915GM			0x25928086
168 #define	INTEL_IGD_945			0x27728086
169 #define	INTEL_IGD_945GM			0x27a28086
170 #define	INTEL_IGD_945GME		0x27ae8086
171 #define	INTEL_IGD_946GZ			0x29728086
172 #define	INTEL_IGD_965G1			0x29828086
173 #define	INTEL_IGD_965Q			0x29928086
174 #define	INTEL_IGD_965G2			0x29a28086
175 #define	INTEL_IGD_965GM			0x2a028086
176 #define	INTEL_IGD_965GME		0x2a128086
177 #define	INTEL_IGD_Q35			0x29b28086
178 #define	INTEL_IGD_G33			0x29c28086
179 #define	INTEL_IGD_Q33			0x29d28086
180 #define	INTEL_IGD_GM45			0x2a428086
181 #define	INTEL_IGD_EL			0x2e028086
182 #define	INTEL_IGD_Q45			0x2e128086
183 #define	INTEL_IGD_G45			0x2e228086
184 #define	INTEL_IGD_G41			0x2e328086
185 #define	INTEL_IGD_IGDNG_D		0x00428086
186 #define	INTEL_IGD_IGDNG_M		0x00468086
187 #define	INTEL_IGD_B43			0x2e428086
188 
189 /* Intel 915 and 945 series */
190 #define	IS_INTEL_915(device) ((device == INTEL_IGD_915) ||	\
191 	(device == INTEL_IGD_915GM) ||	\
192 	(device == INTEL_IGD_945) ||	\
193 	(device == INTEL_IGD_945GM) ||	\
194 	(device == INTEL_IGD_945GME))
195 
196 /* Intel 965 series */
197 #define	IS_INTEL_965(device) ((device == INTEL_IGD_946GZ) ||	\
198 	(device == INTEL_IGD_965G1) ||	\
199 	(device == INTEL_IGD_965Q) ||	\
200 	(device == INTEL_IGD_965G2) ||	\
201 	(device == INTEL_IGD_965GM) ||	\
202 	(device == INTEL_IGD_965GME) ||	\
203 	(device == INTEL_IGD_GM45) ||	\
204 	IS_INTEL_G4X(device))
205 
206 /* Intel G33 series */
207 #define	IS_INTEL_X33(device) ((device == INTEL_IGD_Q35) ||	\
208 	(device == INTEL_IGD_G33) ||	\
209 	(device == INTEL_IGD_Q33))
210 
211 /* IGDNG */
212 #define	IS_IGDNG(device)	((device == INTEL_IGD_IGDNG_D) ||	\
213 			(device == INTEL_IGD_IGDNG_M))
214 
215 /* Intel G4X series */
216 #define	IS_INTEL_G4X(device) ((device == INTEL_IGD_EL) ||	\
217 	(device == INTEL_IGD_Q45) ||	\
218 	(device == INTEL_IGD_G45) ||	\
219 	(device == INTEL_IGD_G41) ||	\
220 	IS_IGDNG(device) ||	\
221 	(device == INTEL_IGD_B43))
222 
223 /* register offsets in PCI config space */
224 #define	I8XX_CONF_GMADR			0x10 /* GMADR of i8xx series */
225 #define	I915_CONF_GMADR			0x18 /* GMADR of i915 series */
226 /* (Mirror) GMCH Graphics Control Register (GGC, MGGC) */
227 #define	I8XX_CONF_GC			0x52
228 
229 /* Intel integrated video card graphics mode mask */
230 #define	I8XX_GC_MODE_MASK		0x70
231 #define	IX33_GC_MODE_MASK		0xf0
232 /* GTT Graphics Memory Size (9:8) in GMCH Graphics Control Register */
233 #define	IX33_GGMS_MASK			0x300
234 /* No VT mode, 1MB allocated for GTT */
235 #define	IX33_GGMS_1M			0x100
236 /* VT mode, 2MB allocated for GTT */
237 #define	IX33_GGMS_2M			0x200
238 
239 /* Intel integrated video card GTT definition */
240 #define	GTT_PAGE_SHIFT			12
241 #define	GTT_PAGE_SIZE			(1 << GTT_PAGE_SHIFT)
242 #define	GTT_PAGE_OFFSET			(GTT_PAGE_SIZE - 1)
243 #define	GTT_PTE_MASK			(~GTT_PAGE_OFFSET)
244 #define	GTT_PTE_VALID			0x1
245 #define	GTT_TABLE_VALID			0x1
246 #define	GTT_BASE_MASK			0xfffff000
247 #define	GTT_MB_TO_PAGES(m)		((m) << 8)
248 #define	GTT_POINTER_MASK		0xffffffff00000000
249 
250 /* Intel i810 register offset */
251 #define	I810_POINTER_MASK		0xffffffffc0000000
252 #define	I810_CONF_SMRAM			0x70 /* offset in PCI config space */
253 #define	I810_GMS_MASK			0xc0 /* smram register mask */
254 /*
255  *	GART and GTT entry format table
256  *
257  * 		AMD64 GART entry
258  * 	from bios and kernel develop guide for amd64
259  *	 -----------------------------
260  * 	Bits		Description	|
261  * 	0		valid		|
262  * 	1		coherent	|
263  * 	3:2		reserved	|
264  * 	11:4		physaddr[39:32]	|
265  * 	31:12	physaddr[31:12]	|
266  * 	-----------------------------
267  *		Intel GTT entry
268  * 	Intel video programming manual
269  * 	-----------------------------
270  * 	Bits		descrition	|
271  * 	0		valid		|
272  * 	2:1		memory type	|
273  * 	29:12		PhysAddr[29:12]	|
274  * 	31:30		reserved	|
275  * 	-----------------------------
276  *		AGP entry
277  * 	from AGP protocol 3.0
278  * 	-----------------------------
279  * 	Bits		descrition	|
280  * 	0		valid		|
281  * 	1		coherent	|
282  * 	3:2		reserved	|
283  * 	11:4		PhysAddr[39:32]	|
284  * 	31:12	PhysAddr[31:12]		|
285  * 	63:32	PhysAddr[71:40]		|
286  *	 -----------------------------
287  */
288 
289 /*
290  *	gart and gtt table base register format
291  *
292  *  		AMD64 register format
293  * 	from bios and kernel develop guide for AMD64
294  * 	---------------------------------------------
295  * 	Bits			Description		|
296  * 	3:0			reserved		|
297  * 	31:4			physical addr 39:12	|
298  * 	----------------------------------------------
299  * 		INTEL AGPGART table base register format
300  * 	from AGP protocol 3.0 p142, only support 32 bits
301  * 	---------------------------------------------
302  * 	Bits			Description		|
303  * 	11:0			reserved		|
304  * 	31:12		physical addr 31:12		|
305  * 	63:32		physical addr 63:32		|
306  * 	---------------------------------------------
307  * 		INTEL i810 GTT table base register format
308  * 	_____________________________________________
309  * 	Bits			Description		|
310  * 	0			GTT table enable bit	|
311  * 	11:1			reserved		|
312  * 	31:12			physical addr 31:12	|
313  * 	---------------------------------------------
314  */
315 
316 /* Intel agp bridge specific */
317 #define	AGP_INTEL_POINTER_MASK		0xffffffff00000000
318 
319 /* Amd64 cpu gart device reigster offset */
320 #define	AMD64_APERTURE_CONTROL		0x90
321 #define	AMD64_APERTURE_BASE		0x94
322 #define	AMD64_GART_CACHE_CTL		0x9c
323 #define	AMD64_GART_BASE			0x98
324 
325 /* Amd64 cpu gart bits */
326 #define	AMD64_APERBASE_SHIFT		25
327 #define	AMD64_APERBASE_MASK		0x00007fff
328 #define	AMD64_GARTBASE_SHIFT		8
329 #define	AMD64_GARTBASE_MASK		0xfffffff0
330 #define	AMD64_POINTER_MASK		0xffffff0000000000
331 #define	AMD64_INVALID_CACHE		0x1
332 #define	AMD64_GART_SHIFT		12
333 #define	AMD64_RESERVE_SHIFT		4
334 #define	AMD64_APERSIZE_MASK		0xe
335 #define	AMD64_GARTEN			0x1
336 #define	AMD64_DISGARTCPU		0x10
337 #define	AMD64_DISGARTIO			0x20
338 #define	AMD64_ENTRY_VALID		0x1
339 
340 /* Other common routines */
341 #define	MB2BYTES(m)		((m) << 20)
342 #define	BYTES2MB(m)		((m) >> 20)
343 #define	GIGA_MASK		0xC0000000
344 #define	UI32_MASK		0xffffffffU
345 #define	MAXAPERMEGAS		0x1000 /* Aper size no more than 4G */
346 #define	MINAPERMEGAS		192
347 
348 #endif /* _KERNEL */
349 
350 #ifdef __cplusplus
351 }
352 #endif
353 
354 #endif /* _SYS_AGPDEFS_H */
355