1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2013 Daisuke Aoyama <aoyama@peach.ne.jp>
5 * Copyright (c) 2013 Oleksandr Tymoshenko <gonzo@bluezbox.com>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 */
29
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/bus.h>
33 #include <sys/kernel.h>
34 #include <sys/lock.h>
35 #include <sys/malloc.h>
36 #include <sys/module.h>
37 #include <sys/mutex.h>
38 #include <sys/queue.h>
39 #include <sys/resource.h>
40 #include <sys/rman.h>
41
42 #include <dev/ofw/openfirm.h>
43 #include <dev/ofw/ofw_bus.h>
44 #include <dev/ofw/ofw_bus_subr.h>
45
46 #include <vm/vm.h>
47 #include <vm/pmap.h>
48 #include <machine/bus.h>
49
50 #include "bcm2835_dma.h"
51 #include "bcm2835_vcbus.h"
52
53 #define MAX_REG 9
54
55 /* private flags */
56 #define BCM_DMA_CH_USED 0x00000001
57 #define BCM_DMA_CH_FREE 0x40000000
58 #define BCM_DMA_CH_UNMAP 0x80000000
59
60 /* Register Map (4.2.1.2) */
61 #define BCM_DMA_CS(n) (0x100*(n) + 0x00)
62 #define CS_ACTIVE (1 << 0)
63 #define CS_END (1 << 1)
64 #define CS_INT (1 << 2)
65 #define CS_DREQ (1 << 3)
66 #define CS_ISPAUSED (1 << 4)
67 #define CS_ISHELD (1 << 5)
68 #define CS_ISWAIT (1 << 6)
69 #define CS_ERR (1 << 8)
70 #define CS_WAITWRT (1 << 28)
71 #define CS_DISDBG (1 << 29)
72 #define CS_ABORT (1 << 30)
73 #define CS_RESET (1U << 31)
74 #define BCM_DMA_CBADDR(n) (0x100*(n) + 0x04)
75 #define BCM_DMA_INFO(n) (0x100*(n) + 0x08)
76 #define INFO_INT_EN (1 << 0)
77 #define INFO_TDMODE (1 << 1)
78 #define INFO_WAIT_RESP (1 << 3)
79 #define INFO_D_INC (1 << 4)
80 #define INFO_D_WIDTH (1 << 5)
81 #define INFO_D_DREQ (1 << 6)
82 #define INFO_S_INC (1 << 8)
83 #define INFO_S_WIDTH (1 << 9)
84 #define INFO_S_DREQ (1 << 10)
85 #define INFO_WAITS_SHIFT (21)
86 #define INFO_PERMAP_SHIFT (16)
87 #define INFO_PERMAP_MASK (0x1f << INFO_PERMAP_SHIFT)
88
89 #define BCM_DMA_SRC(n) (0x100*(n) + 0x0C)
90 #define BCM_DMA_DST(n) (0x100*(n) + 0x10)
91 #define BCM_DMA_LEN(n) (0x100*(n) + 0x14)
92 #define BCM_DMA_STRIDE(n) (0x100*(n) + 0x18)
93 #define BCM_DMA_CBNEXT(n) (0x100*(n) + 0x1C)
94 #define BCM_DMA_DEBUG(n) (0x100*(n) + 0x20)
95 #define DEBUG_ERROR_MASK (7)
96
97 #define BCM_DMA_INT_STATUS 0xfe0
98 #define BCM_DMA_ENABLE 0xff0
99
100 /* relative offset from BCM_VC_DMA0_BASE (p.39) */
101 #define BCM_DMA_CH(n) (0x100*(n))
102
103 /* channels used by GPU */
104 #define BCM_DMA_CH_BULK 0
105 #define BCM_DMA_CH_FAST1 2
106 #define BCM_DMA_CH_FAST2 3
107
108 #define BCM_DMA_CH_GPU_MASK ((1 << BCM_DMA_CH_BULK) | \
109 (1 << BCM_DMA_CH_FAST1) | \
110 (1 << BCM_DMA_CH_FAST2))
111
112 /* DMA Control Block - 256bit aligned (p.40) */
113 struct bcm_dma_cb {
114 uint32_t info; /* Transfer Information */
115 uint32_t src; /* Source Address */
116 uint32_t dst; /* Destination Address */
117 uint32_t len; /* Transfer Length */
118 uint32_t stride; /* 2D Mode Stride */
119 uint32_t next; /* Next Control Block Address */
120 uint32_t rsvd1; /* Reserved */
121 uint32_t rsvd2; /* Reserved */
122 };
123
124 #ifdef DEBUG
125 static void bcm_dma_cb_dump(struct bcm_dma_cb *cb);
126 static void bcm_dma_reg_dump(int ch);
127 #endif
128
129 /* DMA channel private info */
130 struct bcm_dma_ch {
131 int ch;
132 uint32_t flags;
133 struct bcm_dma_cb * cb;
134 uint32_t vc_cb;
135 bus_dmamap_t dma_map;
136 void (*intr_func)(int, void *);
137 void * intr_arg;
138 };
139
140 struct bcm_dma_softc {
141 device_t sc_dev;
142 struct mtx sc_mtx;
143 struct resource * sc_mem;
144 struct resource * sc_irq[BCM_DMA_CH_MAX];
145 void * sc_intrhand[BCM_DMA_CH_MAX];
146 struct bcm_dma_ch sc_dma_ch[BCM_DMA_CH_MAX];
147 bus_dma_tag_t sc_dma_tag;
148 };
149
150 static struct bcm_dma_softc *bcm_dma_sc = NULL;
151 static uint32_t bcm_dma_channel_mask;
152
153 static struct ofw_compat_data compat_data[] = {
154 {"broadcom,bcm2835-dma", 1},
155 {"brcm,bcm2835-dma", 1},
156 {NULL, 0}
157 };
158
159 static void
bcm_dmamap_cb(void * arg,bus_dma_segment_t * segs,int nseg,int err)160 bcm_dmamap_cb(void *arg, bus_dma_segment_t *segs,
161 int nseg, int err)
162 {
163 bus_addr_t *addr;
164
165 if (err)
166 return;
167
168 addr = (bus_addr_t*)arg;
169 *addr = ARMC_TO_VCBUS(segs[0].ds_addr);
170 }
171
172 static void
bcm_dma_reset(device_t dev,int ch)173 bcm_dma_reset(device_t dev, int ch)
174 {
175 struct bcm_dma_softc *sc = device_get_softc(dev);
176 struct bcm_dma_cb *cb;
177 uint32_t cs;
178 int count;
179
180 if (ch < 0 || ch >= BCM_DMA_CH_MAX)
181 return;
182
183 cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch));
184
185 if (cs & CS_ACTIVE) {
186 /* pause current task */
187 bus_write_4(sc->sc_mem, BCM_DMA_CS(ch), 0);
188
189 count = 1000;
190 do {
191 cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch));
192 } while (!(cs & CS_ISPAUSED) && (count-- > 0));
193
194 if (!(cs & CS_ISPAUSED)) {
195 device_printf(dev,
196 "Can't abort DMA transfer at channel %d\n", ch);
197 }
198
199 bus_write_4(sc->sc_mem, BCM_DMA_CBNEXT(ch), 0);
200
201 /* Complete everything, clear interrupt */
202 bus_write_4(sc->sc_mem, BCM_DMA_CS(ch),
203 CS_ABORT | CS_INT | CS_END| CS_ACTIVE);
204 }
205
206 /* clear control blocks */
207 bus_write_4(sc->sc_mem, BCM_DMA_CBADDR(ch), 0);
208 bus_write_4(sc->sc_mem, BCM_DMA_CBNEXT(ch), 0);
209
210 /* Reset control block */
211 cb = sc->sc_dma_ch[ch].cb;
212 bzero(cb, sizeof(*cb));
213 cb->info = INFO_WAIT_RESP;
214 }
215
216 static int
bcm_dma_init(device_t dev)217 bcm_dma_init(device_t dev)
218 {
219 struct bcm_dma_softc *sc = device_get_softc(dev);
220 uint32_t reg;
221 struct bcm_dma_ch *ch;
222 void *cb_virt;
223 vm_paddr_t cb_phys;
224 int err;
225 int i;
226
227 /*
228 * Only channels set in bcm_dma_channel_mask can be controlled by us.
229 * The others are out of our control as well as the corresponding bits
230 * in both BCM_DMA_ENABLE and BCM_DMA_INT_STATUS global registers. As
231 * these registers are RW ones, there is no safe way how to write only
232 * the bits which can be controlled by us.
233 *
234 * Fortunately, after reset, all channels are enabled in BCM_DMA_ENABLE
235 * register and all statuses are cleared in BCM_DMA_INT_STATUS one.
236 * Not touching these registers is a trade off between correct
237 * initialization which does not count on anything and not messing up
238 * something we have no control over.
239 */
240 reg = bus_read_4(sc->sc_mem, BCM_DMA_ENABLE);
241 if ((reg & bcm_dma_channel_mask) != bcm_dma_channel_mask)
242 device_printf(dev, "channels are not enabled\n");
243 reg = bus_read_4(sc->sc_mem, BCM_DMA_INT_STATUS);
244 if ((reg & bcm_dma_channel_mask) != 0)
245 device_printf(dev, "statuses are not cleared\n");
246
247 /*
248 * Allocate DMA chunks control blocks based on p.40 of the peripheral
249 * spec - control block should be 32-bit aligned. The DMA controller
250 * has a full 32-bit register dedicated to this address, so we do not
251 * need to bother with the per-SoC peripheral restrictions.
252 */
253 err = bus_dma_tag_create(bus_get_dma_tag(dev),
254 1, 0, BUS_SPACE_MAXADDR_32BIT,
255 BUS_SPACE_MAXADDR, NULL, NULL,
256 sizeof(struct bcm_dma_cb), 1,
257 sizeof(struct bcm_dma_cb),
258 BUS_DMA_ALLOCNOW, NULL, NULL,
259 &sc->sc_dma_tag);
260
261 if (err) {
262 device_printf(dev, "failed allocate DMA tag\n");
263 return (err);
264 }
265
266 /* setup initial settings */
267 for (i = 0; i < BCM_DMA_CH_MAX; i++) {
268 ch = &sc->sc_dma_ch[i];
269
270 bzero(ch, sizeof(struct bcm_dma_ch));
271 ch->ch = i;
272 ch->flags = BCM_DMA_CH_UNMAP;
273
274 if ((bcm_dma_channel_mask & (1 << i)) == 0)
275 continue;
276
277 err = bus_dmamem_alloc(sc->sc_dma_tag, &cb_virt,
278 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
279 &ch->dma_map);
280 if (err) {
281 device_printf(dev, "cannot allocate DMA memory\n");
282 break;
283 }
284
285 /*
286 * Least alignment for busdma-allocated stuff is cache
287 * line size, so just make sure nothing stupid happened
288 * and we got properly aligned address
289 */
290 if ((uintptr_t)cb_virt & 0x1f) {
291 device_printf(dev,
292 "DMA address is not 32-bytes aligned: %p\n",
293 (void*)cb_virt);
294 break;
295 }
296
297 err = bus_dmamap_load(sc->sc_dma_tag, ch->dma_map, cb_virt,
298 sizeof(struct bcm_dma_cb), bcm_dmamap_cb, &cb_phys,
299 BUS_DMA_WAITOK);
300 if (err) {
301 device_printf(dev, "cannot load DMA memory\n");
302 break;
303 }
304
305 ch->cb = cb_virt;
306 ch->vc_cb = cb_phys;
307 ch->flags = BCM_DMA_CH_FREE;
308 ch->cb->info = INFO_WAIT_RESP;
309
310 /* reset DMA engine */
311 bus_write_4(sc->sc_mem, BCM_DMA_CS(i), CS_RESET);
312 }
313
314 return (0);
315 }
316
317 /*
318 * Allocate DMA channel for further use, returns channel # or
319 * BCM_DMA_CH_INVALID
320 */
321 int
bcm_dma_allocate(int req_ch)322 bcm_dma_allocate(int req_ch)
323 {
324 struct bcm_dma_softc *sc = bcm_dma_sc;
325 int ch = BCM_DMA_CH_INVALID;
326 int i;
327
328 if (sc == NULL)
329 return (BCM_DMA_CH_INVALID);
330
331 if (req_ch >= BCM_DMA_CH_MAX)
332 return (BCM_DMA_CH_INVALID);
333
334 /* Auto(req_ch < 0) or CH specified */
335 mtx_lock(&sc->sc_mtx);
336
337 if (req_ch < 0) {
338 for (i = 0; i < BCM_DMA_CH_MAX; i++) {
339 if (sc->sc_dma_ch[i].flags & BCM_DMA_CH_FREE) {
340 ch = i;
341 sc->sc_dma_ch[ch].flags &= ~BCM_DMA_CH_FREE;
342 sc->sc_dma_ch[ch].flags |= BCM_DMA_CH_USED;
343 break;
344 }
345 }
346 } else if (sc->sc_dma_ch[req_ch].flags & BCM_DMA_CH_FREE) {
347 ch = req_ch;
348 sc->sc_dma_ch[ch].flags &= ~BCM_DMA_CH_FREE;
349 sc->sc_dma_ch[ch].flags |= BCM_DMA_CH_USED;
350 }
351
352 mtx_unlock(&sc->sc_mtx);
353 return (ch);
354 }
355
356 /*
357 * Frees allocated channel. Returns 0 on success, -1 otherwise
358 */
359 int
bcm_dma_free(int ch)360 bcm_dma_free(int ch)
361 {
362 struct bcm_dma_softc *sc = bcm_dma_sc;
363
364 if (sc == NULL)
365 return (-1);
366
367 if (ch < 0 || ch >= BCM_DMA_CH_MAX)
368 return (-1);
369
370 mtx_lock(&sc->sc_mtx);
371 if (sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED) {
372 sc->sc_dma_ch[ch].flags |= BCM_DMA_CH_FREE;
373 sc->sc_dma_ch[ch].flags &= ~BCM_DMA_CH_USED;
374 sc->sc_dma_ch[ch].intr_func = NULL;
375 sc->sc_dma_ch[ch].intr_arg = NULL;
376
377 /* reset DMA engine */
378 bcm_dma_reset(sc->sc_dev, ch);
379 }
380
381 mtx_unlock(&sc->sc_mtx);
382 return (0);
383 }
384
385 /*
386 * Assign handler function for channel interrupt
387 * Returns 0 on success, -1 otherwise
388 */
389 int
bcm_dma_setup_intr(int ch,void (* func)(int,void *),void * arg)390 bcm_dma_setup_intr(int ch, void (*func)(int, void *), void *arg)
391 {
392 struct bcm_dma_softc *sc = bcm_dma_sc;
393 struct bcm_dma_cb *cb;
394
395 if (sc == NULL)
396 return (-1);
397
398 if (ch < 0 || ch >= BCM_DMA_CH_MAX)
399 return (-1);
400
401 if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED))
402 return (-1);
403
404 sc->sc_dma_ch[ch].intr_func = func;
405 sc->sc_dma_ch[ch].intr_arg = arg;
406 cb = sc->sc_dma_ch[ch].cb;
407 cb->info |= INFO_INT_EN;
408
409 return (0);
410 }
411
412 /*
413 * Setup DMA source parameters
414 * ch - channel number
415 * dreq - hardware DREQ # or BCM_DMA_DREQ_NONE if
416 * source is physical memory
417 * inc_addr - BCM_DMA_INC_ADDR if source address
418 * should be increased after each access or
419 * BCM_DMA_SAME_ADDR if address should remain
420 * the same
421 * width - size of read operation, BCM_DMA_32BIT
422 * for 32bit bursts, BCM_DMA_128BIT for 128 bits
423 *
424 * Returns 0 on success, -1 otherwise
425 */
426 int
bcm_dma_setup_src(int ch,int dreq,int inc_addr,int width)427 bcm_dma_setup_src(int ch, int dreq, int inc_addr, int width)
428 {
429 struct bcm_dma_softc *sc = bcm_dma_sc;
430 uint32_t info;
431
432 if (ch < 0 || ch >= BCM_DMA_CH_MAX)
433 return (-1);
434
435 if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED))
436 return (-1);
437
438 info = sc->sc_dma_ch[ch].cb->info;
439 info &= ~INFO_PERMAP_MASK;
440 info |= (dreq << INFO_PERMAP_SHIFT) & INFO_PERMAP_MASK;
441
442 if (dreq)
443 info |= INFO_S_DREQ;
444 else
445 info &= ~INFO_S_DREQ;
446
447 if (width == BCM_DMA_128BIT)
448 info |= INFO_S_WIDTH;
449 else
450 info &= ~INFO_S_WIDTH;
451
452 if (inc_addr == BCM_DMA_INC_ADDR)
453 info |= INFO_S_INC;
454 else
455 info &= ~INFO_S_INC;
456
457 sc->sc_dma_ch[ch].cb->info = info;
458
459 return (0);
460 }
461
462 /*
463 * Setup DMA destination parameters
464 * ch - channel number
465 * dreq - hardware DREQ # or BCM_DMA_DREQ_NONE if
466 * destination is physical memory
467 * inc_addr - BCM_DMA_INC_ADDR if source address
468 * should be increased after each access or
469 * BCM_DMA_SAME_ADDR if address should remain
470 * the same
471 * width - size of write operation, BCM_DMA_32BIT
472 * for 32bit bursts, BCM_DMA_128BIT for 128 bits
473 *
474 * Returns 0 on success, -1 otherwise
475 */
476 int
bcm_dma_setup_dst(int ch,int dreq,int inc_addr,int width)477 bcm_dma_setup_dst(int ch, int dreq, int inc_addr, int width)
478 {
479 struct bcm_dma_softc *sc = bcm_dma_sc;
480 uint32_t info;
481
482 if (ch < 0 || ch >= BCM_DMA_CH_MAX)
483 return (-1);
484
485 if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED))
486 return (-1);
487
488 info = sc->sc_dma_ch[ch].cb->info;
489 info &= ~INFO_PERMAP_MASK;
490 info |= (dreq << INFO_PERMAP_SHIFT) & INFO_PERMAP_MASK;
491
492 if (dreq)
493 info |= INFO_D_DREQ;
494 else
495 info &= ~INFO_D_DREQ;
496
497 if (width == BCM_DMA_128BIT)
498 info |= INFO_D_WIDTH;
499 else
500 info &= ~INFO_D_WIDTH;
501
502 if (inc_addr == BCM_DMA_INC_ADDR)
503 info |= INFO_D_INC;
504 else
505 info &= ~INFO_D_INC;
506
507 sc->sc_dma_ch[ch].cb->info = info;
508
509 return (0);
510 }
511
512 #ifdef DEBUG
513 void
bcm_dma_cb_dump(struct bcm_dma_cb * cb)514 bcm_dma_cb_dump(struct bcm_dma_cb *cb)
515 {
516
517 printf("DMA CB ");
518 printf("INFO: %8.8x ", cb->info);
519 printf("SRC: %8.8x ", cb->src);
520 printf("DST: %8.8x ", cb->dst);
521 printf("LEN: %8.8x ", cb->len);
522 printf("\n");
523 printf("STRIDE: %8.8x ", cb->stride);
524 printf("NEXT: %8.8x ", cb->next);
525 printf("RSVD1: %8.8x ", cb->rsvd1);
526 printf("RSVD2: %8.8x ", cb->rsvd2);
527 printf("\n");
528 }
529
530 void
bcm_dma_reg_dump(int ch)531 bcm_dma_reg_dump(int ch)
532 {
533 struct bcm_dma_softc *sc = bcm_dma_sc;
534 int i;
535 uint32_t reg;
536
537 if (sc == NULL)
538 return;
539
540 if (ch < 0 || ch >= BCM_DMA_CH_MAX)
541 return;
542
543 printf("DMA%d: ", ch);
544 for (i = 0; i < MAX_REG; i++) {
545 reg = bus_read_4(sc->sc_mem, BCM_DMA_CH(ch) + i*4);
546 printf("%8.8x ", reg);
547 }
548 printf("\n");
549 }
550 #endif
551
552 /*
553 * Start DMA transaction
554 * ch - channel number
555 * src, dst - source and destination address in
556 * ARM physical memory address space.
557 * len - amount of bytes to be transferred
558 *
559 * Returns 0 on success, -1 otherwise
560 */
561 int
bcm_dma_start(int ch,vm_paddr_t src,vm_paddr_t dst,int len)562 bcm_dma_start(int ch, vm_paddr_t src, vm_paddr_t dst, int len)
563 {
564 struct bcm_dma_softc *sc = bcm_dma_sc;
565 struct bcm_dma_cb *cb;
566
567 if (sc == NULL)
568 return (-1);
569
570 if (ch < 0 || ch >= BCM_DMA_CH_MAX)
571 return (-1);
572
573 if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED))
574 return (-1);
575
576 cb = sc->sc_dma_ch[ch].cb;
577 cb->src = ARMC_TO_VCBUS(src);
578 cb->dst = ARMC_TO_VCBUS(dst);
579
580 cb->len = len;
581
582 bus_dmamap_sync(sc->sc_dma_tag,
583 sc->sc_dma_ch[ch].dma_map, BUS_DMASYNC_PREWRITE);
584
585 bus_write_4(sc->sc_mem, BCM_DMA_CBADDR(ch),
586 sc->sc_dma_ch[ch].vc_cb);
587 bus_write_4(sc->sc_mem, BCM_DMA_CS(ch), CS_ACTIVE);
588
589 #ifdef DEBUG
590 bcm_dma_cb_dump(sc->sc_dma_ch[ch].cb);
591 bcm_dma_reg_dump(ch);
592 #endif
593
594 return (0);
595 }
596
597 /*
598 * Get length requested for DMA transaction
599 * ch - channel number
600 *
601 * Returns size of transaction, 0 if channel is invalid
602 */
603 uint32_t
bcm_dma_length(int ch)604 bcm_dma_length(int ch)
605 {
606 struct bcm_dma_softc *sc = bcm_dma_sc;
607 struct bcm_dma_cb *cb;
608
609 if (sc == NULL)
610 return (0);
611
612 if (ch < 0 || ch >= BCM_DMA_CH_MAX)
613 return (0);
614
615 if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED))
616 return (0);
617
618 cb = sc->sc_dma_ch[ch].cb;
619
620 return (cb->len);
621 }
622
623 static void
bcm_dma_intr(void * arg)624 bcm_dma_intr(void *arg)
625 {
626 struct bcm_dma_softc *sc = bcm_dma_sc;
627 struct bcm_dma_ch *ch = (struct bcm_dma_ch *)arg;
628 uint32_t cs, debug;
629
630 /* my interrupt? */
631 cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch->ch));
632
633 /*
634 * Is it an active channel? Our diagnostics could be better here, but
635 * it's not necessarily an easy task to resolve a rid/resource to an
636 * actual irq number. We'd want to do this to set a flag indicating
637 * whether the irq is shared or not, so we know to complain.
638 */
639 if (!(ch->flags & BCM_DMA_CH_USED))
640 return;
641
642 /* Again, we can't complain here. The same logic applies. */
643 if (!(cs & (CS_INT | CS_ERR)))
644 return;
645
646 if (cs & CS_ERR) {
647 debug = bus_read_4(sc->sc_mem, BCM_DMA_DEBUG(ch->ch));
648 device_printf(sc->sc_dev, "DMA error %d on CH%d\n",
649 debug & DEBUG_ERROR_MASK, ch->ch);
650 bus_write_4(sc->sc_mem, BCM_DMA_DEBUG(ch->ch),
651 debug & DEBUG_ERROR_MASK);
652 bcm_dma_reset(sc->sc_dev, ch->ch);
653 }
654
655 if (cs & CS_INT) {
656 /* acknowledge interrupt */
657 bus_write_4(sc->sc_mem, BCM_DMA_CS(ch->ch),
658 CS_INT | CS_END);
659
660 /* Prepare for possible access to len field */
661 bus_dmamap_sync(sc->sc_dma_tag, ch->dma_map,
662 BUS_DMASYNC_POSTWRITE);
663
664 /* save callback function and argument */
665 if (ch->intr_func)
666 ch->intr_func(ch->ch, ch->intr_arg);
667 }
668 }
669
670 static int
bcm_dma_probe(device_t dev)671 bcm_dma_probe(device_t dev)
672 {
673
674 if (!ofw_bus_status_okay(dev))
675 return (ENXIO);
676
677 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
678 return (ENXIO);
679
680 device_set_desc(dev, "BCM2835 DMA Controller");
681 return (BUS_PROBE_DEFAULT);
682 }
683
684 static int
bcm_dma_attach(device_t dev)685 bcm_dma_attach(device_t dev)
686 {
687 struct bcm_dma_softc *sc = device_get_softc(dev);
688 phandle_t node;
689 int rid, err = 0;
690 int i;
691
692 sc->sc_dev = dev;
693
694 if (bcm_dma_sc)
695 return (ENXIO);
696
697 for (i = 0; i < BCM_DMA_CH_MAX; i++) {
698 sc->sc_irq[i] = NULL;
699 sc->sc_intrhand[i] = NULL;
700 }
701
702 /* Get DMA channel mask. */
703 node = ofw_bus_get_node(sc->sc_dev);
704 if (OF_getencprop(node, "brcm,dma-channel-mask", &bcm_dma_channel_mask,
705 sizeof(bcm_dma_channel_mask)) == -1 &&
706 OF_getencprop(node, "broadcom,channels", &bcm_dma_channel_mask,
707 sizeof(bcm_dma_channel_mask)) == -1) {
708 device_printf(dev, "could not get channel mask property\n");
709 return (ENXIO);
710 }
711
712 /* Mask out channels used by GPU. */
713 bcm_dma_channel_mask &= ~BCM_DMA_CH_GPU_MASK;
714
715 /* DMA0 - DMA14 */
716 rid = 0;
717 sc->sc_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
718 if (sc->sc_mem == NULL) {
719 device_printf(dev, "could not allocate memory resource\n");
720 return (ENXIO);
721 }
722
723 /* IRQ DMA0 - DMA11 XXX NOT USE DMA12(spurious?) */
724 for (rid = 0; rid < BCM_DMA_CH_MAX; rid++) {
725 if ((bcm_dma_channel_mask & (1 << rid)) == 0)
726 continue;
727
728 sc->sc_irq[rid] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
729 RF_ACTIVE | RF_SHAREABLE);
730 if (sc->sc_irq[rid] == NULL) {
731 device_printf(dev, "cannot allocate interrupt\n");
732 err = ENXIO;
733 goto fail;
734 }
735 if (bus_setup_intr(dev, sc->sc_irq[rid], INTR_TYPE_MISC | INTR_MPSAFE,
736 NULL, bcm_dma_intr, &sc->sc_dma_ch[rid],
737 &sc->sc_intrhand[rid])) {
738 device_printf(dev, "cannot setup interrupt handler\n");
739 err = ENXIO;
740 goto fail;
741 }
742 }
743
744 mtx_init(&sc->sc_mtx, "bcmdma", "bcmdma", MTX_DEF);
745 bcm_dma_sc = sc;
746
747 err = bcm_dma_init(dev);
748 if (err)
749 goto fail;
750
751 return (err);
752
753 fail:
754 if (sc->sc_mem)
755 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem);
756
757 for (i = 0; i < BCM_DMA_CH_MAX; i++) {
758 if (sc->sc_intrhand[i])
759 bus_teardown_intr(dev, sc->sc_irq[i], sc->sc_intrhand[i]);
760 if (sc->sc_irq[i])
761 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq[i]);
762 }
763
764 return (err);
765 }
766
767 static device_method_t bcm_dma_methods[] = {
768 DEVMETHOD(device_probe, bcm_dma_probe),
769 DEVMETHOD(device_attach, bcm_dma_attach),
770 { 0, 0 }
771 };
772
773 static driver_t bcm_dma_driver = {
774 "bcm_dma",
775 bcm_dma_methods,
776 sizeof(struct bcm_dma_softc),
777 };
778
779 EARLY_DRIVER_MODULE(bcm_dma, simplebus, bcm_dma_driver, 0, 0,
780 BUS_PASS_SUPPORTDEV + BUS_PASS_ORDER_MIDDLE);
781 MODULE_VERSION(bcm_dma, 1);
782