1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2001-2024, Intel Corporation 5 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 6 * Copyright (c) 2021-2024 Rubicon Communications, LLC (Netgate) 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include "opt_ddb.h" 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_rss.h" 34 35 #ifdef HAVE_KERNEL_OPTION_HEADERS 36 #include "opt_device_polling.h" 37 #endif 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #ifdef DDB 42 #include <sys/types.h> 43 #include <ddb/ddb.h> 44 #endif 45 #include <sys/buf_ring.h> 46 #include <sys/bus.h> 47 #include <sys/endian.h> 48 #include <sys/kernel.h> 49 #include <sys/kthread.h> 50 #include <sys/malloc.h> 51 #include <sys/mbuf.h> 52 #include <sys/module.h> 53 #include <sys/rman.h> 54 #include <sys/smp.h> 55 #include <sys/socket.h> 56 #include <sys/sockio.h> 57 #include <sys/sysctl.h> 58 #include <sys/taskqueue.h> 59 #include <sys/eventhandler.h> 60 #include <machine/bus.h> 61 #include <machine/resource.h> 62 63 #include <net/bpf.h> 64 #include <net/ethernet.h> 65 #include <net/if.h> 66 #include <net/if_var.h> 67 #include <net/if_arp.h> 68 #include <net/if_dl.h> 69 #include <net/if_media.h> 70 #include <net/iflib.h> 71 72 #include <net/if_types.h> 73 #include <net/if_vlan_var.h> 74 75 #include <netinet/in_systm.h> 76 #include <netinet/in.h> 77 #include <netinet/if_ether.h> 78 #include <netinet/ip.h> 79 #include <netinet/ip6.h> 80 #include <netinet/tcp.h> 81 #include <netinet/udp.h> 82 83 #include <machine/in_cksum.h> 84 #include <dev/led/led.h> 85 #include <dev/pci/pcivar.h> 86 #include <dev/pci/pcireg.h> 87 88 #include "igc_api.h" 89 #include "igc_i225.h" 90 #include "ifdi_if.h" 91 92 93 #ifndef _IGC_H_DEFINED_ 94 #define _IGC_H_DEFINED_ 95 96 97 /* Tunables */ 98 99 /* 100 * IGC_MAX_TXD: Maximum number of Transmit Descriptors 101 * Valid Range: 128-4096 102 * Default Value: 1024 103 * This value is the number of transmit descriptors allocated by the driver. 104 * Increasing this value allows the driver to queue more transmits. Each 105 * descriptor is 16 bytes. 106 * Since TDLEN should be multiple of 128bytes, the number of transmit 107 * desscriptors should meet the following condition. 108 * (num_tx_desc * sizeof(struct igc_tx_desc)) % 128 == 0 109 */ 110 #define IGC_MIN_TXD 128 111 #define IGC_MAX_TXD 4096 112 #define IGC_DEFAULT_TXD 1024 113 #define IGC_DEFAULT_MULTI_TXD 4096 114 #define IGC_MAX_TXD 4096 115 116 /* 117 * IGC_MAX_RXD - Maximum number of receive Descriptors 118 * Valid Range: 128-4096 119 * Default Value: 1024 120 * This value is the number of receive descriptors allocated by the driver. 121 * Increasing this value allows the driver to buffer more incoming packets. 122 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 123 * descriptor. The maximum MTU size is 16110. 124 * Since TDLEN should be multiple of 128bytes, the number of transmit 125 * desscriptors should meet the following condition. 126 * (num_tx_desc * sizeof(struct igc_tx_desc)) % 128 == 0 127 */ 128 #define IGC_MIN_RXD 128 129 #define IGC_MAX_RXD 4096 130 #define IGC_DEFAULT_RXD 1024 131 #define IGC_DEFAULT_MULTI_RXD 4096 132 #define IGC_MAX_RXD 4096 133 134 /* 135 * This parameter controls whether or not autonegotation is enabled. 136 * 0 - Disable autonegotiation 137 * 1 - Enable autonegotiation 138 */ 139 #define DO_AUTO_NEG true 140 141 /* Tunables -- End */ 142 143 #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 144 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 145 ADVERTISE_1000_FULL | ADVERTISE_2500_FULL) 146 147 #define AUTO_ALL_MODES 0 148 149 /* 150 * Micellaneous constants 151 */ 152 #define MAX_NUM_MULTICAST_ADDRESSES 128 153 #define IGC_FC_PAUSE_TIME 0x0680 154 155 #define IGC_TXPBSIZE 20408 156 #define IGC_PKTTYPE_MASK 0x0000FFF0 157 #define IGC_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coalesce Flush */ 158 159 #define IGC_RX_PTHRESH 8 160 #define IGC_RX_HTHRESH 8 161 #define IGC_RX_WTHRESH 4 162 163 #define IGC_TX_PTHRESH 8 164 #define IGC_TX_HTHRESH 1 165 166 /* Define the interrupt rates and EITR helpers */ 167 #define IGC_INTS_4K 4000 168 #define IGC_INTS_20K 20000 169 #define IGC_INTS_70K 70000 170 #define IGC_INTS_DEFAULT 8000 171 #define IGC_EITR_DIVIDEND 1000000 172 #define IGC_EITR_SHIFT 2 173 #define IGC_QVECTOR_MASK 0x7FFC 174 #define IGC_INTS_TO_EITR(i) (((IGC_EITR_DIVIDEND/i) & IGC_QVECTOR_MASK) << \ 175 IGC_EITR_SHIFT) 176 177 /* 178 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 179 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 180 * also optimize cache line size effect. H/W supports up to cache line size 128. 181 */ 182 #define IGC_DBA_ALIGN 128 183 184 #define IGC_MSIX_BAR 3 185 186 /* Defines for printing debug information */ 187 #define DEBUG_INIT 0 188 #define DEBUG_IOCTL 0 189 #define DEBUG_HW 0 190 191 #define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 192 #define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 193 #define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 194 #define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 195 #define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 196 #define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 197 #define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 198 #define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 199 #define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 200 201 #define IGC_MAX_SCATTER 40 202 #define IGC_VFTA_SIZE 128 203 #define IGC_TSO_SIZE 65535 204 #define IGC_TSO_SEG_SIZE 4096 /* Max dma segment size */ 205 #define IGC_CSUM_OFFLOAD (CSUM_IP | CSUM_IP_UDP | CSUM_IP_TCP | \ 206 CSUM_IP_SCTP | CSUM_IP6_UDP | CSUM_IP6_TCP | \ 207 CSUM_IP6_SCTP) /* Offload bits in mbuf flag */ 208 209 struct igc_softc; 210 211 struct igc_int_delay_info { 212 struct igc_softc *sc; /* Back-pointer to the softc struct */ 213 int offset; /* Register offset to read/write */ 214 int value; /* Current value in usecs */ 215 }; 216 217 /* 218 * The transmit ring, one per tx queue 219 */ 220 struct tx_ring { 221 struct igc_softc *sc; 222 struct igc_tx_desc *tx_base; 223 uint64_t tx_paddr; 224 qidx_t *tx_rsq; 225 uint8_t me; 226 qidx_t tx_rs_cidx; 227 qidx_t tx_rs_pidx; 228 qidx_t tx_cidx_processed; 229 /* Interrupt resources */ 230 void *tag; 231 struct resource *res; 232 233 /* Soft stats */ 234 unsigned long tx_irq; 235 unsigned long tx_packets; 236 unsigned long tx_bytes; 237 238 239 /* Saved csum offloading context information */ 240 int csum_flags; 241 int csum_lhlen; 242 int csum_iphlen; 243 244 int csum_thlen; 245 int csum_mss; 246 int csum_pktlen; 247 248 uint32_t csum_txd_upper; 249 uint32_t csum_txd_lower; /* last field */ 250 }; 251 252 /* 253 * The Receive ring, one per rx queue 254 */ 255 struct rx_ring { 256 struct igc_softc *sc; 257 struct igc_rx_queue *que; 258 u32 me; 259 u32 payload; 260 union igc_rx_desc_extended *rx_base; 261 uint64_t rx_paddr; 262 263 /* Interrupt resources */ 264 void *tag; 265 struct resource *res; 266 267 /* Soft stats */ 268 unsigned long rx_irq; 269 unsigned long rx_discarded; 270 unsigned long rx_packets; 271 unsigned long rx_bytes; 272 273 /* Next requested EITR latency */ 274 u8 rx_nextlatency; 275 }; 276 277 struct igc_tx_queue { 278 struct igc_softc *sc; 279 u32 msix; 280 u32 eims; /* This queue's EIMS bit */ 281 u32 me; 282 struct tx_ring txr; 283 }; 284 285 struct igc_rx_queue { 286 struct igc_softc *sc; 287 u32 me; 288 u32 msix; 289 u32 eims; 290 u32 eitr_setting; 291 struct rx_ring rxr; 292 u64 irqs; 293 struct if_irq que_irq; 294 }; 295 296 /* Our softc structure */ 297 struct igc_softc { 298 if_t ifp; 299 struct igc_hw hw; 300 301 if_softc_ctx_t shared; 302 if_ctx_t ctx; 303 #define tx_num_queues shared->isc_ntxqsets 304 #define rx_num_queues shared->isc_nrxqsets 305 #define intr_type shared->isc_intr 306 /* FreeBSD operating-system-specific structures. */ 307 struct igc_osdep osdep; 308 device_t dev; 309 struct cdev *led_dev; 310 311 struct igc_tx_queue *tx_queues; 312 struct igc_rx_queue *rx_queues; 313 struct if_irq irq; 314 315 struct resource *memory; 316 struct resource *flash; 317 struct resource *ioport; 318 319 struct resource *res; 320 void *tag; 321 u32 linkvec; 322 u32 ivars; 323 324 struct ifmedia *media; 325 int msix; 326 int if_flags; 327 int igc_insert_vlan_header; 328 u32 ims; 329 330 u32 flags; 331 /* Task for FAST handling */ 332 struct grouptask link_task; 333 334 u32 txd_cmd; 335 336 u32 rx_mbuf_sz; 337 338 int enable_aim; 339 340 /* Management and WOL features */ 341 u32 wol; 342 343 /* Multicast array memory */ 344 u8 *mta; 345 346 /* Info about the interface */ 347 u16 link_active; 348 u16 fc; 349 u16 link_speed; 350 u16 link_duplex; 351 u32 smartspeed; 352 u32 dmac; 353 u32 pba; 354 int link_mask; 355 356 u64 que_mask; 357 358 struct igc_fw_version fw_ver; 359 360 struct igc_int_delay_info tx_int_delay; 361 struct igc_int_delay_info tx_abs_int_delay; 362 struct igc_int_delay_info rx_int_delay; 363 struct igc_int_delay_info rx_abs_int_delay; 364 struct igc_int_delay_info tx_itr; 365 366 /* Misc stats maintained by the driver */ 367 unsigned long dropped_pkts; 368 unsigned long link_irq; 369 unsigned long rx_overruns; 370 unsigned long watchdog_events; 371 372 struct igc_hw_stats stats; 373 u16 vf_ifp; 374 }; 375 376 void igc_dump_rs(struct igc_softc *); 377 378 #define IGC_RSSRK_SIZE 4 379 #define IGC_RSSRK_VAL(key, i) (key[(i) * IGC_RSSRK_SIZE] | \ 380 key[(i) * IGC_RSSRK_SIZE + 1] << 8 | \ 381 key[(i) * IGC_RSSRK_SIZE + 2] << 16 | \ 382 key[(i) * IGC_RSSRK_SIZE + 3] << 24) 383 #endif /* _IGC_H_DEFINED_ */ 384