1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright (c) 1999-2000 by Sun Microsystems, Inc. 24 * All rights reserved. 25 */ 26 27 #ifndef _SYS_1394_IEEE1394_H 28 #define _SYS_1394_IEEE1394_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 /* 33 * ieee1394.h 34 * This file contains various defines that go with IEEE 1394 35 */ 36 37 #ifdef __cplusplus 38 extern "C" { 39 #endif 40 41 42 /* 43 * IEEE1394_MAX_NODES defines the maximum number of nodes 44 * that can be addressed on a single 1394 bus. There are 45 * a 63 physical nodes that can be present and 1 broadcast 46 * node id. The range of 1394 nodeid's are 47 * 0 ... (IEEE1394_MAX_NODES - 1) 48 */ 49 #define IEEE1394_MAX_NODES 64 50 51 /* The node id for broadcast writes */ 52 #define IEEE1394_BROADCAST_NODEID 63 53 54 /* Maximum number of ports per node */ 55 #define IEEE1394_MAX_NUM_PORTS 16 56 57 #define IEEE1394_BUS_NUM_MASK 0x0000FFC0 58 #define IEEE1394_LOCAL_BUS 0x3FF 59 60 #define IEEE1394_NODE_NUM_MASK 0x0000003F 61 #define IEEE1394_NODE_NUM(DATA) ((DATA) & IEEE1394_NODE_NUM_MASK) 62 63 #define IEEE1394_BUS_CYCLES_PER_SEC 8000 64 65 /* IEEE 1394 Bus related definitions */ 66 #define IEEE1394_ADDR_NODE_ID_MASK 0xFFFF000000000000 67 #define IEEE1394_ADDR_NODE_ID_SHIFT 48 68 #define IEEE1394_ADDR_NODE_ID(ADDR) \ 69 (((ADDR) & IEEE1394_ADDR_NODE_ID_MASK) >> \ 70 IEEE1394_ADDR_NODE_ID_SHIFT) 71 72 #define IEEE1394_ADDR_BUS_ID_MASK 0xFFC0000000000000 73 #define IEEE1394_ADDR_BUS_ID_SHIFT 54 74 #define IEEE1394_ADDR_BUS_ID(ADDR) \ 75 (((ADDR) & IEEE1394_ADDR_BUS_ID_MASK) >> \ 76 IEEE1394_ADDR_BUS_ID_SHIFT) 77 78 #define IEEE1394_ADDR_PHY_ID_MASK 0x003F000000000000 79 #define IEEE1394_ADDR_PHY_ID_SHIFT 48 80 #define IEEE1394_ADDR_PHY_ID(ADDR) \ 81 (((ADDR) & IEEE1394_ADDR_PHY_ID_MASK) >> \ 82 IEEE1394_ADDR_PHY_ID_SHIFT) 83 84 #define IEEE1394_ADDR_OFFSET_MASK 0x0000FFFFFFFFFFFF 85 86 /* IEEE 1394 data sizes */ 87 #define IEEE1394_QUADLET (sizeof (uint32_t)) 88 #define IEEE1394_OCTLET (sizeof (uint64_t)) 89 90 /* Still need to look at these */ 91 /* TCODES - packet transaction codes (as defined in 1394-1995 6.2.4.5) */ 92 #define IEEE1394_TCODE_WRITE_QUADLET 0x0 93 #define IEEE1394_TCODE_WRITE_BLOCK 0x1 94 #define IEEE1394_TCODE_WRITE_RESP 0x2 95 #define IEEE1394_TCODE_RES1 0x3 96 #define IEEE1394_TCODE_READ_QUADLET 0x4 97 #define IEEE1394_TCODE_READ_BLOCK 0x5 98 #define IEEE1394_TCODE_READ_QUADLET_RESP 0x6 99 #define IEEE1394_TCODE_READ_BLOCK_RESP 0x7 100 #define IEEE1394_TCODE_CYCLE_START 0x8 101 #define IEEE1394_TCODE_LOCK 0x9 102 #define IEEE1394_TCODE_ISOCH 0xA 103 #define IEEE1394_TCODE_LOCK_RESP 0xB 104 #define IEEE1394_TCODE_RES2 0xC 105 #define IEEE1394_TCODE_RES3 0xD 106 #define IEEE1394_TCODE_PHY 0xE 107 #define IEEE1394_TCODE_RES4 0xF 108 109 #define IEEE1394_RESP_COMPLETE 0x0 110 #define IEEE1394_RESP_CONFLICT_ERROR 0x4 111 #define IEEE1394_RESP_DATA_ERROR 0x5 112 #define IEEE1394_RESP_TYPE_ERROR 0x6 113 #define IEEE1394_RESP_ADDRESS_ERROR 0x7 114 115 #define IEEE1394_ISOCH_HDR_QUAD_SZ 3 116 117 /* Self ID packet definitions */ 118 #define IEEE1394_SELFID_PCKT_ID_MASK 0xC0000000 119 #define IEEE1394_SELFID_PCKT_ID_SHIFT 30 120 #define IEEE1394_SELFID_PCKT_ID_VALID 0x2 121 #define IEEE1394_SELFID_ISVALID(S_PKT) \ 122 (~((S_PKT)->spkt_data ^ (S_PKT)->spkt_inverse) ? 0 : 1) 123 124 #define IEEE1394_SELFID_PHYID_MASK 0x3F000000 125 #define IEEE1394_SELFID_PHYID_SHIFT 24 126 #define IEEE1394_SELFID_PHYID(S_PKT) \ 127 (((S_PKT)->spkt_data & IEEE1394_SELFID_PHYID_MASK) >> \ 128 IEEE1394_SELFID_PHYID_SHIFT) 129 130 /* SelfID PKT #0 */ 131 #define IEEE1394_SELFID_L_MASK 0x00400000 132 #define IEEE1394_SELFID_L_SHIFT 22 133 #define IEEE1394_SELFID_ISLINKON(S_PKT) \ 134 (((S_PKT)->spkt_data & IEEE1394_SELFID_L_MASK) >> \ 135 IEEE1394_SELFID_L_SHIFT) 136 137 #define IEEE1394_SELFID_GAP_CNT_MASK 0x003F0000 138 #define IEEE1394_SELFID_GAP_CNT_SHIFT 16 139 #define IEEE1394_SELFID_GAP_CNT(S_PKT) \ 140 (((S_PKT)->spkt_data & IEEE1394_SELFID_GAP_CNT_MASK) >> \ 141 IEEE1394_SELFID_GAP_CNT_SHIFT) 142 143 #define IEEE1394_SELFID_SP_MASK 0x0000C000 144 #define IEEE1394_SELFID_SP_SHIFT 14 145 146 #define IEEE1394_SELFID_DEL_MASK (0x00003000) 147 #define IEEE1394_SELFID_DEL_SHIFT 12 148 #define IEEE1394_SELFID_DELAY(S_PKT) \ 149 (((S_PKT)->spkt_data & IEEE1394_SELFID_DEL_MASK) >> \ 150 IEEE1394_SELFID_DEL_SHIFT) 151 152 #define IEEE1394_SELFID_C_MASK 0x00000800 153 #define IEEE1394_SELFID_C_SHIFT 11 154 #define IEEE1394_SELFID_ISCONTENDER(S_PKT) \ 155 (((S_PKT)->spkt_data & IEEE1394_SELFID_C_MASK) >> \ 156 IEEE1394_SELFID_C_SHIFT) 157 158 #define IEEE1394_SELFID_PWR_MASK 0x00000700 159 #define IEEE1394_SELFID_PWR_SHIFT 8 160 #define IEEE1394_SELFID_POWER(S_PKT) \ 161 (((S_PKT)->spkt_data & IEEE1394_SELFID_PWR_MASK) >> \ 162 IEEE1394_SELFID_PWR_SHIFT) 163 164 #define IEEE1394_SELFID_PORT_TO_CHILD 0x3 165 #define IEEE1394_SELFID_PORT_TO_PARENT 0x2 166 #define IEEE1394_SELFID_PORT_NOT_CONNECTED 0x1 167 #define IEEE1394_SELFID_PORT_NO_PORT 0x0 168 169 #define IEEE1394_SELFID_I_MASK 0x00000002 170 #define IEEE1394_SELFID_I_SHIFT 1 171 #define IEEE1394_SELFID_INITIATED_RESET(S_PKT) \ 172 (((S_PKT)->spkt_data & IEEE1394_SELFID_I_MASK) >> \ 173 IEEE1394_SELFID_I_SHIFT) 174 175 #define IEEE1394_SELFID_M_MASK 0x00000001 176 #define IEEE1394_SELFID_M_SHIFT 0 177 #define IEEE1394_SELFID_ISMORE(S_PKT) \ 178 (((S_PKT)->spkt_data & IEEE1394_SELFID_M_MASK) >> \ 179 IEEE1394_SELFID_M_SHIFT) 180 181 #define IEEE1394_SELFID_PORT_OFFSET_FIRST 6 182 183 /* SelfID PKT #1 (n=0) */ 184 #define IEEE1394_SELFID_N_MASK 0x00700000 185 #define IEEE1394_SELFID_N_SHIFT 20 186 #define IEEE1394_SELFID_PKT_NUM(S_PKT) \ 187 (((S_PKT)->spkt_data & IEEE1394_SELFID_N_MASK) >> \ 188 IEEE1394_SELFID_N_SHIFT) 189 190 #define IEEE1394_SELFID_PORT_OFFSET_OTHERS 16 191 192 /* PHY Config Packet definitions */ 193 #define IEEE1394_PHY_CONFIG_T_BIT_MASK 0x00400000 194 #define IEEE1394_PHY_CONFIG_T_BIT_SHIFT 22 195 #define IEEE1394_PHY_CONFIG_GAP_CNT_MASK 0x003F0000 196 #define IEEE1394_PHY_CONFIG_GAP_CNT_SHIFT 16 197 198 #define IEEE1394_PHY_CONFIG_R_BIT_MASK 0x00800000 199 #define IEEE1394_PHY_CONFIG_R_BIT_SHIFT 23 200 #define IEEE1394_PHY_CONFIG_ROOT_HOLD_MASK 0x3F000000 201 #define IEEE1394_PHY_CONFIG_ROOT_HOLD_SHIFT 24 202 203 204 /* 205 * CSR Registers and register fields. 206 */ 207 /* CSR Register Addresses (IEEE1394-1995 8.3.2.2) */ 208 #define IEEE1394_CSR_STATE_CLEAR 0xFFFFF0000000 209 #define IEEE1394_CSR_STATE_SET 0xFFFFF0000004 210 #define IEEE1394_CSR_NODE_IDS 0xFFFFF0000008 211 #define IEEE1394_CSR_RESET_START 0xFFFFF000000C 212 #define IEEE1394_CSR_SPLIT_TIMEOUT_HI 0xFFFFF0000018 213 #define IEEE1394_CSR_SPLIT_TIMEOUT_LO 0xFFFFF000001C 214 #define IEEE1394_CSR_ARG_HI 0xFFFFF0000020 215 #define IEEE1394_CSR_ARG_LO 0xFFFFF0000024 216 #define IEEE1394_CSR_TEST_START 0xFFFFF0000028 217 #define IEEE1394_CSR_TEST_STATUS 0xFFFFF000002C 218 219 /* Optional Register Addresses */ 220 #define IEEE1394_CSR_INTERRUPT_TARGET 0xFFFFF0000050 221 #define IEEE1394_CSR_INTERRUPT_MASK 0xFFFFF0000054 222 #define IEEE1394_CSR_CLOCK_VALUE 0xFFFFF0000058 223 #define IEEE1394_CSR_CLOCK_VALUE_SZ 0x28 224 #define IEEE1394_CSR_MESSAGE_REQUEST 0xFFFFF0000080 225 #define IEEE1394_CSR_MESSAGE_REQUEST_SZ 0x80 226 227 /* Serial Bus CSR Register Addresss (IEEE1394-1995 8.3.2.3) */ 228 #define IEEE1394_SCSR_CYCLE_TIME 0xFFFFF0000200 229 #define IEEE1394_SCSR_BUS_TIME 0xFFFFF0000204 230 #define IEEE1394_SCSR_PWRFAIL_IMMINENT 0xFFFFF0000208 231 #define IEEE1394_SCSR_PWRSRC 0xFFFFF000020C 232 #define IEEE1394_SCSR_BUSY_TIMEOUT 0xFFFFF0000210 233 #define IEEE1394_SCSR_BUSMGR_ID 0xFFFFF000021C 234 #define IEEE1394_SCSR_BANDWIDTH_AVAIL 0xFFFFF0000220 235 #define IEEE1394_SCSR_CHANS_AVAIL_HI 0xFFFFF0000224 236 #define IEEE1394_SCSR_CHANS_AVAIL_LO 0xFFFFF0000228 237 238 /* Config ROM Address */ 239 #define IEEE1394_CONFIG_ROM_ADDR 0xFFFFF0000400 240 #define IEEE1394_CONFIG_ROM_SZ 0x400 241 #define IEEE1394_CONFIG_ROM_QUAD_SZ 0x100 242 243 /* Unit CSR Register Addresses */ 244 #define IEEE1394_UCSR_TOPOLOGY_MAP 0xFFFFF0001000 245 #define IEEE1394_UCSR_TOPOLOGY_MAP_SZ 0x400 246 #define IEEE1394_UCSR_SPEED_MAP 0xFFFFF0002000 247 #define IEEE1394_UCSR_SPEED_MAP_SZ 0x1000 248 249 /* Boundary for "reserved" CSR registers */ 250 #define IEEE1394_UCSR_RESERVED_BOUNDARY 0xFFFFF0010000 251 252 #define IEEE1394_CSR_OFFSET_MASK 0x00000000FFFF 253 254 /* 1394 Bus Speeds */ 255 #define IEEE1394_S100 0 256 #define IEEE1394_S200 1 257 #define IEEE1394_S400 2 258 #define IEEE1394_S800 3 259 #define IEEE1394_S1600 4 260 #define IEEE1394_S3200 5 261 262 /* IEEE 1394 Bandwidth bounds */ 263 #define IEEE1394_BANDWIDTH_MIN 0 264 #define IEEE1394_BANDWIDTH_MAX 0x1333 265 266 /* Speed Map specific defines */ 267 #define IEEE1394_SPEED_MAP_CRC_LEN 0x03F1 268 #define IEEE1394_SPEED_MAP_LEN_MASK 0x0000FFFF 269 #define IEEE1394_SPEED_MAP_LEN_SHIFT 16 270 #define IEEE1394_SPEED_MAP_DATA_LEN 0x0FBE 271 272 /* Topology Map specific defines */ 273 #define IEEE1394_TOP_MAP_LEN_MASK 0x0000FFFF 274 #define IEEE1394_TOP_MAP_LEN_SHIFT 16 275 276 /* Config ROM specific defines */ 277 #define IEEE1394_CFG_ROM_CRC_VALUE_MASK 0x0000FFFF 278 #define IEEE1394_CFG_ROM_CRC_LEN_SHIFT 16 279 #define IEEE1394_CFG_ROM_CRC_LEN_MASK 0xFF 280 #define IEEE1394_CFG_ROM_LEN_SHIFT 16 281 282 /* CRC16 defines */ 283 #define IEEE1394_CRC16_MASK 0xFFFF 284 285 /* Bit positions in the STATE register */ 286 #define IEEE1394_CSR_STATE_CMSTR 0x00000100 287 #define IEEE1394_CSR_STATE_DREQ 0x00000040 288 #define IEEE1394_CSR_STATE_ABDICATE 0x00000400 289 290 /* Positions in the BUS_INFO_BLOCK */ 291 #define IEEE1394_BIB_LNK_SPD_MASK 0x00000007 292 #define IEEE1394_BIB_LNK_SPD_SHIFT 0 293 #define IEEE1394_BIB_GEN_MASK 0x000000F0 294 #define IEEE1394_BIB_GEN_SHIFT 4 295 #define IEEE1394_BIB_MROM_MASK 0x00000300 296 #define IEEE1394_BIB_MROM_SHIFT 8 297 #define IEEE1394_BIB_IRMC_MASK 0x80000000 298 #define IEEE1394_BIB_IRMC_SHIFT 31 299 #define IEEE1394_BIB_BMC_MASK 0x10000000 300 #define IEEE1394_BIB_BMC_SHIFT 28 301 #define IEEE1394_BIB_CMC_MASK 0x40000000 302 #define IEEE1394_BIB_CMC_SHIFT 30 303 #define IEEE1394_BIB_MAXREC_MASK 0x0000F000 304 #define IEEE1394_BIB_MAXREC_SHIFT 12 305 306 #define IEEE1394_BIB_QUAD_SZ 5 307 #define IEEE1394_BIB_SZ 0x14 308 309 /* Bus Manager specific defines */ 310 #define IEEE1394_BM_IRM_TIMEOUT 625000 311 #define IEEE1394_BM_INCUMBENT_TIMEOUT 125000 312 #ifdef __cplusplus 313 } 314 #endif 315 316 #endif /* _SYS_1394_IEEE1394_H */ 317