1 /*-
2 * ichsmb_pci.c
3 *
4 * Author: Archie Cobbs <archie@freebsd.org>
5 * Copyright (c) 2000 Whistle Communications, Inc.
6 * All rights reserved.
7 * Author: Archie Cobbs <archie@freebsd.org>
8 *
9 * Subject to the following obligations and disclaimer of warranty, use and
10 * redistribution of this software, in source or object code forms, with or
11 * without modifications are expressly permitted by Whistle Communications;
12 * provided, however, that:
13 * 1. Any and all reproductions of the source or object code must include the
14 * copyright notice above and the following disclaimer of warranties; and
15 * 2. No rights are granted, in any manner or form, to use Whistle
16 * Communications, Inc. trademarks, including the mark "WHISTLE
17 * COMMUNICATIONS" on advertising, endorsements, or otherwise except as
18 * such appears in the above copyright notice or in the software.
19 *
20 * THIS SOFTWARE IS BEING PROVIDED BY WHISTLE COMMUNICATIONS "AS IS", AND
21 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, WHISTLE COMMUNICATIONS MAKES NO
22 * REPRESENTATIONS OR WARRANTIES, EXPRESS OR IMPLIED, REGARDING THIS SOFTWARE,
23 * INCLUDING WITHOUT LIMITATION, ANY AND ALL IMPLIED WARRANTIES OF
24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
25 * WHISTLE COMMUNICATIONS DOES NOT WARRANT, GUARANTEE, OR MAKE ANY
26 * REPRESENTATIONS REGARDING THE USE OF, OR THE RESULTS OF THE USE OF THIS
27 * SOFTWARE IN TERMS OF ITS CORRECTNESS, ACCURACY, RELIABILITY OR OTHERWISE.
28 * IN NO EVENT SHALL WHISTLE COMMUNICATIONS BE LIABLE FOR ANY DAMAGES
29 * RESULTING FROM OR ARISING OUT OF ANY USE OF THIS SOFTWARE, INCLUDING
30 * WITHOUT LIMITATION, ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
31 * PUNITIVE, OR CONSEQUENTIAL DAMAGES, PROCUREMENT OF SUBSTITUTE GOODS OR
32 * SERVICES, LOSS OF USE, DATA OR PROFITS, HOWEVER CAUSED AND UNDER ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
35 * THIS SOFTWARE, EVEN IF WHISTLE COMMUNICATIONS IS ADVISED OF THE POSSIBILITY
36 * OF SUCH DAMAGE.
37 */
38
39 #include <sys/cdefs.h>
40 /*
41 * Support for the SMBus controller logical device which is part of the
42 * Intel 81801AA/AB/BA/CA/DC/EB (ICH/ICH[02345]) I/O controller hub chips.
43 */
44
45 #include <sys/param.h>
46 #include <sys/systm.h>
47 #include <sys/kernel.h>
48 #include <sys/module.h>
49 #include <sys/errno.h>
50 #include <sys/lock.h>
51 #include <sys/mutex.h>
52 #include <sys/syslog.h>
53 #include <sys/bus.h>
54
55 #include <machine/bus.h>
56 #include <sys/rman.h>
57 #include <machine/resource.h>
58
59 #include <dev/pci/pcivar.h>
60 #include <dev/pci/pcireg.h>
61
62 #include <dev/smbus/smbconf.h>
63
64 #include <dev/ichsmb/ichsmb_var.h>
65 #include <dev/ichsmb/ichsmb_reg.h>
66
67 /* PCI unique identifiers */
68 #define PCI_VENDOR_INTEL 0x8086
69 #define ID_82801AA 0x2413
70 #define ID_82801AB 0x2423
71 #define ID_82801BA 0x2443
72 #define ID_82801CA 0x2483
73 #define ID_82801DC 0x24C3
74 #define ID_82801EB 0x24D3
75 #define ID_82801FB 0x266A
76 #define ID_82801GB 0x27da
77 #define ID_82801H 0x283e
78 #define ID_82801I 0x2930
79 #define ID_EP80579 0x5032
80 #define ID_82801JI 0x3a30
81 #define ID_82801JD 0x3a60
82 #define ID_PCH 0x3b30
83 #define ID_6300ESB 0x25a4
84 #define ID_631xESB 0x269b
85 #define ID_DH89XXCC 0x2330
86 #define ID_PATSBURG 0x1d22
87 #define ID_CPT 0x1c22
88 #define ID_PPT 0x1e22
89 #define ID_AVOTON 0x1f3c
90 #define ID_COLETOCRK 0x23B0
91 #define ID_LPT 0x8c22
92 #define ID_LPTLP 0x9c22
93 #define ID_WCPT 0x8ca2
94 #define ID_WCPTLP 0x9ca2
95 #define ID_BAYTRAIL 0x0f12
96 #define ID_BRASWELL 0x2292
97 #define ID_WELLSBURG 0x8d22
98 #define ID_SRPT 0xa123
99 #define ID_SRPTLP 0x9d23
100 #define ID_DENVERTON 0x19df
101 #define ID_BROXTON 0x5ad4
102 #define ID_LEWISBURG 0xa1a3
103 #define ID_LEWISBURG2 0xa223
104 #define ID_KABYLAKE 0xa2a3
105 #define ID_CANNONLAKE 0xa323
106 #define ID_COMETLAKE 0x02a3
107 #define ID_COMETLAKE2 0x06a3
108 #define ID_TIGERLAKE 0xa0a3
109 #define ID_TIGERLAKE2 0x43a3
110 #define ID_GEMINILAKE 0x31d4
111 #define ID_CEDARFORK 0x18df
112 #define ID_ICELAKE 0x34a3
113 #define ID_ALDERLAKE 0x7aa3
114 #define ID_ALDERLAKE2 0x51a3
115 #define ID_ALDERLAKE3 0x54a3
116 #define ID_METEORLAKE 0x7e22
117 #define ID_METEORLAKE2 0x7f23
118 #define ID_METEORLAKE3 0xae22
119
120 static const struct pci_device_table ichsmb_devices[] = {
121 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801AA),
122 PCI_DESCR("Intel 82801AA (ICH) SMBus controller") },
123 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801AB),
124 PCI_DESCR("Intel 82801AB (ICH0) SMBus controller") },
125 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801BA),
126 PCI_DESCR("Intel 82801BA (ICH2) SMBus controller") },
127 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801CA),
128 PCI_DESCR("Intel 82801CA (ICH3) SMBus controller") },
129 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801DC),
130 PCI_DESCR("Intel 82801DC (ICH4) SMBus controller") },
131 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801EB),
132 PCI_DESCR("Intel 82801EB (ICH5) SMBus controller") },
133 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801FB),
134 PCI_DESCR("Intel 82801FB (ICH6) SMBus controller") },
135 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801GB),
136 PCI_DESCR("Intel 82801GB (ICH7) SMBus controller") },
137 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801H),
138 PCI_DESCR("Intel 82801H (ICH8) SMBus controller") },
139 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801I),
140 PCI_DESCR("Intel 82801I (ICH9) SMBus controller") },
141 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801GB),
142 PCI_DESCR("Intel 82801GB (ICH7) SMBus controller") },
143 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801H),
144 PCI_DESCR("Intel 82801H (ICH8) SMBus controller") },
145 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801I),
146 PCI_DESCR("Intel 82801I (ICH9) SMBus controller") },
147 { PCI_DEV(PCI_VENDOR_INTEL, ID_EP80579),
148 PCI_DESCR("Intel EP80579 SMBus controller") },
149 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801JI),
150 PCI_DESCR("Intel 82801JI (ICH10) SMBus controller") },
151 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801JD),
152 PCI_DESCR("Intel 82801JD (ICH10) SMBus controller") },
153 { PCI_DEV(PCI_VENDOR_INTEL, ID_PCH),
154 PCI_DESCR("Intel PCH SMBus controller") },
155 { PCI_DEV(PCI_VENDOR_INTEL, ID_6300ESB),
156 PCI_DESCR("Intel 6300ESB (ICH) SMBus controller") },
157 { PCI_DEV(PCI_VENDOR_INTEL, ID_631xESB),
158 PCI_DESCR("Intel 631xESB/6321ESB (ESB2) SMBus controller") },
159 { PCI_DEV(PCI_VENDOR_INTEL, ID_DH89XXCC),
160 PCI_DESCR("Intel DH89xxCC SMBus controller") },
161 { PCI_DEV(PCI_VENDOR_INTEL, ID_PATSBURG),
162 PCI_DESCR("Intel Patsburg SMBus controller") },
163 { PCI_DEV(PCI_VENDOR_INTEL, ID_CPT),
164 PCI_DESCR("Intel Cougar Point SMBus controller") },
165 { PCI_DEV(PCI_VENDOR_INTEL, ID_PPT),
166 PCI_DESCR("Intel Panther Point SMBus controller") },
167 { PCI_DEV(PCI_VENDOR_INTEL, ID_AVOTON),
168 PCI_DESCR("Intel Avoton SMBus controller") },
169 { PCI_DEV(PCI_VENDOR_INTEL, ID_LPT),
170 PCI_DESCR("Intel Lynx Point SMBus controller") },
171 { PCI_DEV(PCI_VENDOR_INTEL, ID_LPTLP),
172 PCI_DESCR("Intel Lynx Point-LP SMBus controller") },
173 { PCI_DEV(PCI_VENDOR_INTEL, ID_WCPT),
174 PCI_DESCR("Intel Wildcat Point SMBus controller") },
175 { PCI_DEV(PCI_VENDOR_INTEL, ID_WCPTLP),
176 PCI_DESCR("Intel Wildcat Point-LP SMBus controller") },
177 { PCI_DEV(PCI_VENDOR_INTEL, ID_BAYTRAIL),
178 PCI_DESCR("Intel Baytrail SMBus controller") },
179 { PCI_DEV(PCI_VENDOR_INTEL, ID_BRASWELL),
180 PCI_DESCR("Intel Braswell SMBus controller") },
181 { PCI_DEV(PCI_VENDOR_INTEL, ID_COLETOCRK),
182 PCI_DESCR("Intel Coleto Creek SMBus controller") },
183 { PCI_DEV(PCI_VENDOR_INTEL, ID_WELLSBURG),
184 PCI_DESCR("Intel Wellsburg SMBus controller") },
185 { PCI_DEV(PCI_VENDOR_INTEL, ID_SRPT),
186 PCI_DESCR("Intel Sunrise Point-H SMBus controller") },
187 { PCI_DEV(PCI_VENDOR_INTEL, ID_SRPTLP),
188 PCI_DESCR("Intel Sunrise Point-LP SMBus controller") },
189 { PCI_DEV(PCI_VENDOR_INTEL, ID_DENVERTON),
190 PCI_DESCR("Intel Denverton SMBus controller") },
191 { PCI_DEV(PCI_VENDOR_INTEL, ID_BROXTON),
192 PCI_DESCR("Intel Broxton SMBus controller") },
193 { PCI_DEV(PCI_VENDOR_INTEL, ID_LEWISBURG),
194 PCI_DESCR("Intel Lewisburg SMBus controller") },
195 { PCI_DEV(PCI_VENDOR_INTEL, ID_LEWISBURG2),
196 PCI_DESCR("Intel Lewisburg SMBus controller") },
197 { PCI_DEV(PCI_VENDOR_INTEL, ID_KABYLAKE),
198 PCI_DESCR("Intel Kaby Lake SMBus controller") },
199 { PCI_DEV(PCI_VENDOR_INTEL, ID_CANNONLAKE),
200 PCI_DESCR("Intel Cannon Lake SMBus controller") },
201 { PCI_DEV(PCI_VENDOR_INTEL, ID_COMETLAKE),
202 PCI_DESCR("Intel Comet Lake SMBus controller") },
203 { PCI_DEV(PCI_VENDOR_INTEL, ID_COMETLAKE2),
204 PCI_DESCR("Intel Comet Lake SMBus controller") },
205 { PCI_DEV(PCI_VENDOR_INTEL, ID_TIGERLAKE),
206 PCI_DESCR("Intel Tiger Lake SMBus controller") },
207 { PCI_DEV(PCI_VENDOR_INTEL, ID_TIGERLAKE2),
208 PCI_DESCR("Intel Tiger Lake SMBus controller") },
209 { PCI_DEV(PCI_VENDOR_INTEL, ID_GEMINILAKE),
210 PCI_DESCR("Intel Gemini Lake SMBus controller") },
211 { PCI_DEV(PCI_VENDOR_INTEL, ID_CEDARFORK),
212 PCI_DESCR("Intel Cedar Fork SMBus controller") },
213 { PCI_DEV(PCI_VENDOR_INTEL, ID_ICELAKE),
214 PCI_DESCR("Intel Ice Lake SMBus controller") },
215 { PCI_DEV(PCI_VENDOR_INTEL, ID_ALDERLAKE),
216 PCI_DESCR("Intel Alder Lake SMBus controller") },
217 { PCI_DEV(PCI_VENDOR_INTEL, ID_ALDERLAKE2),
218 PCI_DESCR("Intel Alder Lake SMBus controller") },
219 { PCI_DEV(PCI_VENDOR_INTEL, ID_ALDERLAKE3),
220 PCI_DESCR("Intel Alder Lake SMBus controller") },
221 { PCI_DEV(PCI_VENDOR_INTEL, ID_METEORLAKE),
222 PCI_DESCR("Intel Meteor Lake SMBus controller") },
223 { PCI_DEV(PCI_VENDOR_INTEL, ID_METEORLAKE2),
224 PCI_DESCR("Intel Meteor Lake SMBus controller") },
225 { PCI_DEV(PCI_VENDOR_INTEL, ID_METEORLAKE3),
226 PCI_DESCR("Intel Meteor Lake SMBus controller") },
227 };
228
229 /* Internal functions */
230 static int ichsmb_pci_probe(device_t dev);
231 static int ichsmb_pci_attach(device_t dev);
232 /*Use generic one for now*/
233 #if 0
234 static int ichsmb_pci_detach(device_t dev);
235 #endif
236
237 /* Device methods */
238 static device_method_t ichsmb_pci_methods[] = {
239 /* Device interface */
240 DEVMETHOD(device_probe, ichsmb_pci_probe),
241 DEVMETHOD(device_attach, ichsmb_pci_attach),
242 DEVMETHOD(device_detach, ichsmb_detach),
243
244 /* SMBus methods */
245 DEVMETHOD(smbus_callback, ichsmb_callback),
246 DEVMETHOD(smbus_quick, ichsmb_quick),
247 DEVMETHOD(smbus_sendb, ichsmb_sendb),
248 DEVMETHOD(smbus_recvb, ichsmb_recvb),
249 DEVMETHOD(smbus_writeb, ichsmb_writeb),
250 DEVMETHOD(smbus_writew, ichsmb_writew),
251 DEVMETHOD(smbus_readb, ichsmb_readb),
252 DEVMETHOD(smbus_readw, ichsmb_readw),
253 DEVMETHOD(smbus_pcall, ichsmb_pcall),
254 DEVMETHOD(smbus_bwrite, ichsmb_bwrite),
255 DEVMETHOD(smbus_bread, ichsmb_bread),
256
257 DEVMETHOD_END
258 };
259
260 static driver_t ichsmb_pci_driver = {
261 "ichsmb",
262 ichsmb_pci_methods,
263 sizeof(struct ichsmb_softc)
264 };
265
266 DRIVER_MODULE(ichsmb, pci, ichsmb_pci_driver, 0, 0);
267
268 static int
ichsmb_pci_probe(device_t dev)269 ichsmb_pci_probe(device_t dev)
270 {
271 const struct pci_device_table *tbl;
272
273 tbl = PCI_MATCH(dev, ichsmb_devices);
274 if (tbl == NULL)
275 return (ENXIO);
276
277 device_set_desc(dev, tbl->descr);
278 return (ichsmb_probe(dev));
279 }
280
281 static int
ichsmb_pci_attach(device_t dev)282 ichsmb_pci_attach(device_t dev)
283 {
284 const sc_p sc = device_get_softc(dev);
285 int error;
286
287 /* Initialize private state */
288 bzero(sc, sizeof(*sc));
289 sc->ich_cmd = -1;
290 sc->dev = dev;
291
292 /* Allocate an I/O range */
293 sc->io_rid = ICH_SMB_BASE;
294 sc->io_res = bus_alloc_resource_anywhere(dev, SYS_RES_IOPORT,
295 &sc->io_rid, 16, RF_ACTIVE);
296 if (sc->io_res == NULL)
297 sc->io_res = bus_alloc_resource_anywhere(dev, SYS_RES_IOPORT,
298 &sc->io_rid, 32, RF_ACTIVE);
299 if (sc->io_res == NULL) {
300 device_printf(dev, "can't map I/O\n");
301 error = ENXIO;
302 goto fail;
303 }
304
305 /* Allocate interrupt */
306 sc->irq_rid = 0;
307 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
308 &sc->irq_rid, RF_ACTIVE | RF_SHAREABLE);
309 if (sc->irq_res == NULL) {
310 device_printf(dev, "can't get IRQ\n");
311 error = ENXIO;
312 goto fail;
313 }
314
315 /* Enable device */
316 pci_write_config(dev, ICH_HOSTC, ICH_HOSTC_HST_EN, 1);
317
318 /* Done */
319 error = ichsmb_attach(dev);
320 if (error)
321 goto fail;
322 return (0);
323
324 fail:
325 /* Attach failed, release resources */
326 ichsmb_release_resources(sc);
327 return (error);
328 }
329
330
331 MODULE_DEPEND(ichsmb, pci, 1, 1, 1);
332 MODULE_DEPEND(ichsmb, smbus, SMBUS_MINVER, SMBUS_PREFVER, SMBUS_MAXVER);
333 MODULE_VERSION(ichsmb, 1);
334 PCI_PNP_INFO(ichsmb_devices);
335