1 /*-
2 * ichsmb_pci.c
3 *
4 * Author: Archie Cobbs <archie@freebsd.org>
5 * Copyright (c) 2000 Whistle Communications, Inc.
6 * All rights reserved.
7 * Author: Archie Cobbs <archie@freebsd.org>
8 *
9 * Subject to the following obligations and disclaimer of warranty, use and
10 * redistribution of this software, in source or object code forms, with or
11 * without modifications are expressly permitted by Whistle Communications;
12 * provided, however, that:
13 * 1. Any and all reproductions of the source or object code must include the
14 * copyright notice above and the following disclaimer of warranties; and
15 * 2. No rights are granted, in any manner or form, to use Whistle
16 * Communications, Inc. trademarks, including the mark "WHISTLE
17 * COMMUNICATIONS" on advertising, endorsements, or otherwise except as
18 * such appears in the above copyright notice or in the software.
19 *
20 * THIS SOFTWARE IS BEING PROVIDED BY WHISTLE COMMUNICATIONS "AS IS", AND
21 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, WHISTLE COMMUNICATIONS MAKES NO
22 * REPRESENTATIONS OR WARRANTIES, EXPRESS OR IMPLIED, REGARDING THIS SOFTWARE,
23 * INCLUDING WITHOUT LIMITATION, ANY AND ALL IMPLIED WARRANTIES OF
24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
25 * WHISTLE COMMUNICATIONS DOES NOT WARRANT, GUARANTEE, OR MAKE ANY
26 * REPRESENTATIONS REGARDING THE USE OF, OR THE RESULTS OF THE USE OF THIS
27 * SOFTWARE IN TERMS OF ITS CORRECTNESS, ACCURACY, RELIABILITY OR OTHERWISE.
28 * IN NO EVENT SHALL WHISTLE COMMUNICATIONS BE LIABLE FOR ANY DAMAGES
29 * RESULTING FROM OR ARISING OUT OF ANY USE OF THIS SOFTWARE, INCLUDING
30 * WITHOUT LIMITATION, ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
31 * PUNITIVE, OR CONSEQUENTIAL DAMAGES, PROCUREMENT OF SUBSTITUTE GOODS OR
32 * SERVICES, LOSS OF USE, DATA OR PROFITS, HOWEVER CAUSED AND UNDER ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
35 * THIS SOFTWARE, EVEN IF WHISTLE COMMUNICATIONS IS ADVISED OF THE POSSIBILITY
36 * OF SUCH DAMAGE.
37 */
38
39 #include <sys/cdefs.h>
40 /*
41 * Support for the SMBus controller logical device which is part of the
42 * Intel 81801AA/AB/BA/CA/DC/EB (ICH/ICH[02345]) I/O controller hub chips.
43 */
44
45 #include <sys/param.h>
46 #include <sys/systm.h>
47 #include <sys/kernel.h>
48 #include <sys/module.h>
49 #include <sys/errno.h>
50 #include <sys/lock.h>
51 #include <sys/mutex.h>
52 #include <sys/syslog.h>
53 #include <sys/bus.h>
54
55 #include <machine/bus.h>
56 #include <sys/rman.h>
57 #include <machine/resource.h>
58
59 #include <dev/pci/pcivar.h>
60 #include <dev/pci/pcireg.h>
61
62 #include <dev/smbus/smbconf.h>
63
64 #include <dev/ichsmb/ichsmb_var.h>
65 #include <dev/ichsmb/ichsmb_reg.h>
66
67 /* PCI unique identifiers */
68 #define PCI_VENDOR_INTEL 0x8086
69 #define ID_82801AA 0x2413
70 #define ID_82801AB 0x2423
71 #define ID_82801BA 0x2443
72 #define ID_82801CA 0x2483
73 #define ID_82801DC 0x24C3
74 #define ID_82801EB 0x24D3
75 #define ID_82801FB 0x266A
76 #define ID_82801GB 0x27da
77 #define ID_82801H 0x283e
78 #define ID_82801I 0x2930
79 #define ID_EP80579 0x5032
80 #define ID_82801JI 0x3a30
81 #define ID_82801JD 0x3a60
82 #define ID_PCH 0x3b30
83 #define ID_6300ESB 0x25a4
84 #define ID_631xESB 0x269b
85 #define ID_DH89XXCC 0x2330
86 #define ID_PATSBURG 0x1d22
87 #define ID_CPT 0x1c22
88 #define ID_PPT 0x1e22
89 #define ID_AVOTON 0x1f3c
90 #define ID_COLETOCRK 0x23B0
91 #define ID_LPT 0x8c22
92 #define ID_LPTLP 0x9c22
93 #define ID_WCPT 0x8ca2
94 #define ID_WCPTLP 0x9ca2
95 #define ID_BAYTRAIL 0x0f12
96 #define ID_BRASWELL 0x2292
97 #define ID_WELLSBURG 0x8d22
98 #define ID_SRPT 0xa123
99 #define ID_SRPTLP 0x9d23
100 #define ID_DENVERTON 0x19df
101 #define ID_BROXTON 0x5ad4
102 #define ID_LEWISBURG 0xa1a3
103 #define ID_LEWISBURG2 0xa223
104 #define ID_KABYLAKE 0xa2a3
105 #define ID_CANNONLAKE 0xa323
106 #define ID_COMETLAKE 0x02a3
107 #define ID_COMETLAKE2 0x06a3
108 #define ID_TIGERLAKE 0xa0a3
109 #define ID_TIGERLAKE2 0x43a3
110 #define ID_ELKHARTLAKE 0x4b23
111 #define ID_GEMINILAKE 0x31d4
112 #define ID_CEDARFORK 0x18df
113 #define ID_ICELAKE 0x34a3
114 #define ID_ALDERLAKE 0x7aa3
115 #define ID_ALDERLAKE2 0x51a3
116 #define ID_ALDERLAKE3 0x54a3
117 #define ID_METEORLAKE 0x7e22
118 #define ID_METEORLAKE2 0x7f23
119 #define ID_METEORLAKE3 0xae22
120
121 static const struct pci_device_table ichsmb_devices[] = {
122 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801AA),
123 PCI_DESCR("Intel 82801AA (ICH) SMBus controller") },
124 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801AB),
125 PCI_DESCR("Intel 82801AB (ICH0) SMBus controller") },
126 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801BA),
127 PCI_DESCR("Intel 82801BA (ICH2) SMBus controller") },
128 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801CA),
129 PCI_DESCR("Intel 82801CA (ICH3) SMBus controller") },
130 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801DC),
131 PCI_DESCR("Intel 82801DC (ICH4) SMBus controller") },
132 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801EB),
133 PCI_DESCR("Intel 82801EB (ICH5) SMBus controller") },
134 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801FB),
135 PCI_DESCR("Intel 82801FB (ICH6) SMBus controller") },
136 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801GB),
137 PCI_DESCR("Intel 82801GB (ICH7) SMBus controller") },
138 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801H),
139 PCI_DESCR("Intel 82801H (ICH8) SMBus controller") },
140 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801I),
141 PCI_DESCR("Intel 82801I (ICH9) SMBus controller") },
142 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801GB),
143 PCI_DESCR("Intel 82801GB (ICH7) SMBus controller") },
144 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801H),
145 PCI_DESCR("Intel 82801H (ICH8) SMBus controller") },
146 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801I),
147 PCI_DESCR("Intel 82801I (ICH9) SMBus controller") },
148 { PCI_DEV(PCI_VENDOR_INTEL, ID_EP80579),
149 PCI_DESCR("Intel EP80579 SMBus controller") },
150 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801JI),
151 PCI_DESCR("Intel 82801JI (ICH10) SMBus controller") },
152 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801JD),
153 PCI_DESCR("Intel 82801JD (ICH10) SMBus controller") },
154 { PCI_DEV(PCI_VENDOR_INTEL, ID_PCH),
155 PCI_DESCR("Intel PCH SMBus controller") },
156 { PCI_DEV(PCI_VENDOR_INTEL, ID_6300ESB),
157 PCI_DESCR("Intel 6300ESB (ICH) SMBus controller") },
158 { PCI_DEV(PCI_VENDOR_INTEL, ID_631xESB),
159 PCI_DESCR("Intel 631xESB/6321ESB (ESB2) SMBus controller") },
160 { PCI_DEV(PCI_VENDOR_INTEL, ID_DH89XXCC),
161 PCI_DESCR("Intel DH89xxCC SMBus controller") },
162 { PCI_DEV(PCI_VENDOR_INTEL, ID_PATSBURG),
163 PCI_DESCR("Intel Patsburg SMBus controller") },
164 { PCI_DEV(PCI_VENDOR_INTEL, ID_CPT),
165 PCI_DESCR("Intel Cougar Point SMBus controller") },
166 { PCI_DEV(PCI_VENDOR_INTEL, ID_PPT),
167 PCI_DESCR("Intel Panther Point SMBus controller") },
168 { PCI_DEV(PCI_VENDOR_INTEL, ID_AVOTON),
169 PCI_DESCR("Intel Avoton SMBus controller") },
170 { PCI_DEV(PCI_VENDOR_INTEL, ID_LPT),
171 PCI_DESCR("Intel Lynx Point SMBus controller") },
172 { PCI_DEV(PCI_VENDOR_INTEL, ID_LPTLP),
173 PCI_DESCR("Intel Lynx Point-LP SMBus controller") },
174 { PCI_DEV(PCI_VENDOR_INTEL, ID_WCPT),
175 PCI_DESCR("Intel Wildcat Point SMBus controller") },
176 { PCI_DEV(PCI_VENDOR_INTEL, ID_WCPTLP),
177 PCI_DESCR("Intel Wildcat Point-LP SMBus controller") },
178 { PCI_DEV(PCI_VENDOR_INTEL, ID_BAYTRAIL),
179 PCI_DESCR("Intel Baytrail SMBus controller") },
180 { PCI_DEV(PCI_VENDOR_INTEL, ID_BRASWELL),
181 PCI_DESCR("Intel Braswell SMBus controller") },
182 { PCI_DEV(PCI_VENDOR_INTEL, ID_COLETOCRK),
183 PCI_DESCR("Intel Coleto Creek SMBus controller") },
184 { PCI_DEV(PCI_VENDOR_INTEL, ID_WELLSBURG),
185 PCI_DESCR("Intel Wellsburg SMBus controller") },
186 { PCI_DEV(PCI_VENDOR_INTEL, ID_SRPT),
187 PCI_DESCR("Intel Sunrise Point-H SMBus controller") },
188 { PCI_DEV(PCI_VENDOR_INTEL, ID_SRPTLP),
189 PCI_DESCR("Intel Sunrise Point-LP SMBus controller") },
190 { PCI_DEV(PCI_VENDOR_INTEL, ID_DENVERTON),
191 PCI_DESCR("Intel Denverton SMBus controller") },
192 { PCI_DEV(PCI_VENDOR_INTEL, ID_BROXTON),
193 PCI_DESCR("Intel Broxton SMBus controller") },
194 { PCI_DEV(PCI_VENDOR_INTEL, ID_LEWISBURG),
195 PCI_DESCR("Intel Lewisburg SMBus controller") },
196 { PCI_DEV(PCI_VENDOR_INTEL, ID_LEWISBURG2),
197 PCI_DESCR("Intel Lewisburg SMBus controller") },
198 { PCI_DEV(PCI_VENDOR_INTEL, ID_KABYLAKE),
199 PCI_DESCR("Intel Kaby Lake SMBus controller") },
200 { PCI_DEV(PCI_VENDOR_INTEL, ID_CANNONLAKE),
201 PCI_DESCR("Intel Cannon Lake SMBus controller") },
202 { PCI_DEV(PCI_VENDOR_INTEL, ID_COMETLAKE),
203 PCI_DESCR("Intel Comet Lake SMBus controller") },
204 { PCI_DEV(PCI_VENDOR_INTEL, ID_COMETLAKE2),
205 PCI_DESCR("Intel Comet Lake SMBus controller") },
206 { PCI_DEV(PCI_VENDOR_INTEL, ID_TIGERLAKE),
207 PCI_DESCR("Intel Tiger Lake SMBus controller") },
208 { PCI_DEV(PCI_VENDOR_INTEL, ID_TIGERLAKE2),
209 PCI_DESCR("Intel Tiger Lake SMBus controller") },
210 { PCI_DEV(PCI_VENDOR_INTEL, ID_ELKHARTLAKE),
211 PCI_DESCR("Intel Elkhart Lake SMBus controller") },
212 { PCI_DEV(PCI_VENDOR_INTEL, ID_GEMINILAKE),
213 PCI_DESCR("Intel Gemini Lake SMBus controller") },
214 { PCI_DEV(PCI_VENDOR_INTEL, ID_CEDARFORK),
215 PCI_DESCR("Intel Cedar Fork SMBus controller") },
216 { PCI_DEV(PCI_VENDOR_INTEL, ID_ICELAKE),
217 PCI_DESCR("Intel Ice Lake SMBus controller") },
218 { PCI_DEV(PCI_VENDOR_INTEL, ID_ALDERLAKE),
219 PCI_DESCR("Intel Alder Lake SMBus controller") },
220 { PCI_DEV(PCI_VENDOR_INTEL, ID_ALDERLAKE2),
221 PCI_DESCR("Intel Alder Lake SMBus controller") },
222 { PCI_DEV(PCI_VENDOR_INTEL, ID_ALDERLAKE3),
223 PCI_DESCR("Intel Alder Lake SMBus controller") },
224 { PCI_DEV(PCI_VENDOR_INTEL, ID_METEORLAKE),
225 PCI_DESCR("Intel Meteor Lake SMBus controller") },
226 { PCI_DEV(PCI_VENDOR_INTEL, ID_METEORLAKE2),
227 PCI_DESCR("Intel Meteor Lake SMBus controller") },
228 { PCI_DEV(PCI_VENDOR_INTEL, ID_METEORLAKE3),
229 PCI_DESCR("Intel Meteor Lake SMBus controller") },
230 };
231
232 /* Internal functions */
233 static int ichsmb_pci_probe(device_t dev);
234 static int ichsmb_pci_attach(device_t dev);
235 /*Use generic one for now*/
236 #if 0
237 static int ichsmb_pci_detach(device_t dev);
238 #endif
239
240 /* Device methods */
241 static device_method_t ichsmb_pci_methods[] = {
242 /* Device interface */
243 DEVMETHOD(device_probe, ichsmb_pci_probe),
244 DEVMETHOD(device_attach, ichsmb_pci_attach),
245 DEVMETHOD(device_detach, ichsmb_detach),
246
247 /* SMBus methods */
248 DEVMETHOD(smbus_callback, ichsmb_callback),
249 DEVMETHOD(smbus_quick, ichsmb_quick),
250 DEVMETHOD(smbus_sendb, ichsmb_sendb),
251 DEVMETHOD(smbus_recvb, ichsmb_recvb),
252 DEVMETHOD(smbus_writeb, ichsmb_writeb),
253 DEVMETHOD(smbus_writew, ichsmb_writew),
254 DEVMETHOD(smbus_readb, ichsmb_readb),
255 DEVMETHOD(smbus_readw, ichsmb_readw),
256 DEVMETHOD(smbus_pcall, ichsmb_pcall),
257 DEVMETHOD(smbus_bwrite, ichsmb_bwrite),
258 DEVMETHOD(smbus_bread, ichsmb_bread),
259
260 DEVMETHOD_END
261 };
262
263 static driver_t ichsmb_pci_driver = {
264 "ichsmb",
265 ichsmb_pci_methods,
266 sizeof(struct ichsmb_softc)
267 };
268
269 DRIVER_MODULE(ichsmb, pci, ichsmb_pci_driver, 0, 0);
270
271 static int
ichsmb_pci_probe(device_t dev)272 ichsmb_pci_probe(device_t dev)
273 {
274 const struct pci_device_table *tbl;
275
276 tbl = PCI_MATCH(dev, ichsmb_devices);
277 if (tbl == NULL)
278 return (ENXIO);
279
280 device_set_desc(dev, tbl->descr);
281 return (ichsmb_probe(dev));
282 }
283
284 static int
ichsmb_pci_attach(device_t dev)285 ichsmb_pci_attach(device_t dev)
286 {
287 const sc_p sc = device_get_softc(dev);
288 int error;
289
290 /* Initialize private state */
291 bzero(sc, sizeof(*sc));
292 sc->ich_cmd = -1;
293 sc->dev = dev;
294
295 /* Allocate an I/O range */
296 sc->io_rid = ICH_SMB_BASE;
297 sc->io_res = bus_alloc_resource_anywhere(dev, SYS_RES_IOPORT,
298 &sc->io_rid, 16, RF_ACTIVE);
299 if (sc->io_res == NULL)
300 sc->io_res = bus_alloc_resource_anywhere(dev, SYS_RES_IOPORT,
301 &sc->io_rid, 32, RF_ACTIVE);
302 if (sc->io_res == NULL) {
303 device_printf(dev, "can't map I/O\n");
304 error = ENXIO;
305 goto fail;
306 }
307
308 /* Allocate interrupt */
309 sc->irq_rid = 0;
310 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
311 &sc->irq_rid, RF_ACTIVE | RF_SHAREABLE);
312 if (sc->irq_res == NULL) {
313 device_printf(dev, "can't get IRQ\n");
314 error = ENXIO;
315 goto fail;
316 }
317
318 /* Enable device */
319 pci_write_config(dev, ICH_HOSTC, ICH_HOSTC_HST_EN, 1);
320
321 /* Done */
322 error = ichsmb_attach(dev);
323 if (error)
324 goto fail;
325 return (0);
326
327 fail:
328 /* Attach failed, release resources */
329 ichsmb_release_resources(sc);
330 return (error);
331 }
332
333
334 MODULE_DEPEND(ichsmb, pci, 1, 1, 1);
335 MODULE_DEPEND(ichsmb, smbus, SMBUS_MINVER, SMBUS_PREFVER, SMBUS_MAXVER);
336 MODULE_VERSION(ichsmb, 1);
337 PCI_PNP_INFO(ichsmb_devices);
338