1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2007-2022 Intel Corporation */ 3 #ifndef _ICP_QAT_FW_INIT_ADMIN_H_ 4 #define _ICP_QAT_FW_INIT_ADMIN_H_ 5 6 #include "icp_qat_fw.h" 7 8 enum icp_qat_fw_init_admin_cmd_id { 9 ICP_QAT_FW_INIT_ME = 0, 10 ICP_QAT_FW_TRNG_ENABLE = 1, 11 ICP_QAT_FW_TRNG_DISABLE = 2, 12 ICP_QAT_FW_CONSTANTS_CFG = 3, 13 ICP_QAT_FW_STATUS_GET = 4, 14 ICP_QAT_FW_COUNTERS_GET = 5, 15 ICP_QAT_FW_LOOPBACK = 6, 16 ICP_QAT_FW_HEARTBEAT_SYNC = 7, 17 ICP_QAT_FW_HEARTBEAT_GET = 8, 18 ICP_QAT_FW_COMP_CAPABILITY_GET = 9, 19 ICP_QAT_FW_CRYPTO_CAPABILITY_GET = 10, 20 ICP_QAT_FW_HEARTBEAT_TIMER_SET = 13, 21 ICP_QAT_FW_RL_SLA_CONFIG = 14, 22 ICP_QAT_FW_RL_INIT = 15, 23 ICP_QAT_FW_RL_DU_START = 16, 24 ICP_QAT_FW_RL_DU_STOP = 17, 25 ICP_QAT_FW_TIMER_GET = 19, 26 ICP_QAT_FW_CNV_STATS_GET = 20, 27 ICP_QAT_FW_PKE_REPLAY_STATS_GET = 21 28 }; 29 30 enum icp_qat_fw_init_admin_resp_status { 31 ICP_QAT_FW_INIT_RESP_STATUS_SUCCESS = 0, 32 ICP_QAT_FW_INIT_RESP_STATUS_FAIL = 1, 33 ICP_QAT_FW_INIT_RESP_STATUS_UNSUPPORTED = 4 34 }; 35 36 enum icp_qat_fw_cnv_error_type { 37 CNV_ERR_TYPE_NO_ERROR = 0, 38 CNV_ERR_TYPE_CHECKSUM_ERROR, 39 CNV_ERR_TYPE_DECOMP_PRODUCED_LENGTH_ERROR, 40 CNV_ERR_TYPE_DECOMPRESSION_ERROR, 41 CNV_ERR_TYPE_TRANSLATION_ERROR, 42 CNV_ERR_TYPE_DECOMP_CONSUMED_LENGTH_ERROR, 43 CNV_ERR_TYPE_UNKNOWN_ERROR 44 }; 45 46 #define CNV_ERROR_TYPE_GET(latest_error) \ 47 ({ \ 48 __typeof__(latest_error) _lerror = latest_error; \ 49 (_lerror >> 12) > CNV_ERR_TYPE_UNKNOWN_ERROR ? \ 50 CNV_ERR_TYPE_UNKNOWN_ERROR : \ 51 (enum icp_qat_fw_cnv_error_type)(_lerror >> 12); \ 52 }) 53 #define CNV_ERROR_LENGTH_DELTA_GET(latest_error) \ 54 ({ \ 55 __typeof__(latest_error) _lerror = latest_error; \ 56 ((s16)((_lerror & 0x0FFF) | (_lerror & 0x0800 ? 0xF000 : 0))); \ 57 }) 58 #define CNV_ERROR_DECOMP_STATUS_GET(latest_error) ((s8)(latest_error & 0xFF)) 59 60 struct icp_qat_fw_init_admin_req { 61 u16 init_cfg_sz; 62 u8 resrvd1; 63 u8 cmd_id; 64 u32 max_req_duration; 65 u64 opaque_data; 66 67 union { 68 /* ICP_QAT_FW_INIT_ME */ 69 struct { 70 u64 resrvd2; 71 u16 ibuf_size_in_kb; 72 u16 resrvd3; 73 u32 resrvd4; 74 }; 75 /* ICP_QAT_FW_CONSTANTS_CFG */ 76 struct { 77 u64 init_cfg_ptr; 78 u64 resrvd5; 79 }; 80 /* ICP_QAT_FW_HEARTBEAT_TIMER_SET */ 81 struct { 82 u64 hb_cfg_ptr; 83 u32 heartbeat_ticks; 84 u32 resrvd6; 85 }; 86 /* ICP_QAT_FW_RL_SLA_CONFIG */ 87 struct { 88 u32 credit_per_sla; 89 u8 service_id; 90 u8 vf_id; 91 u8 resrvd7; 92 u8 resrvd8; 93 u32 resrvd9; 94 u32 resrvd10; 95 }; 96 /* ICP_QAT_FW_RL_INIT */ 97 struct { 98 u32 rl_period; 99 u8 config; 100 u8 resrvd11; 101 u8 num_me; 102 u8 resrvd12; 103 u8 pke_svc_arb_map; 104 u8 bulk_crypto_svc_arb_map; 105 u8 compression_svc_arb_map; 106 u8 resrvd13; 107 u32 resrvd14; 108 }; 109 /* ICP_QAT_FW_RL_DU_STOP */ 110 struct { 111 u64 cfg_ptr; 112 u32 resrvd15; 113 u32 resrvd16; 114 }; 115 }; 116 } __packed; 117 118 struct icp_qat_fw_init_admin_resp { 119 u8 flags; 120 u8 resrvd1; 121 u8 status; 122 u8 cmd_id; 123 union { 124 u32 resrvd2; 125 u32 ras_event_count; 126 /* ICP_QAT_FW_STATUS_GET */ 127 struct { 128 u16 version_minor_num; 129 u16 version_major_num; 130 }; 131 /* ICP_QAT_FW_COMP_CAPABILITY_GET */ 132 u32 extended_features; 133 /* ICP_QAT_FW_CNV_STATS_GET */ 134 struct { 135 u16 error_count; 136 u16 latest_error; 137 }; 138 }; 139 u64 opaque_data; 140 union { 141 u32 resrvd3[4]; 142 /* ICP_QAT_FW_STATUS_GET */ 143 struct { 144 u32 version_patch_num; 145 u8 context_id; 146 u8 ae_id; 147 u16 resrvd4; 148 u64 resrvd5; 149 }; 150 /* ICP_QAT_FW_COMP_CAPABILITY_GET */ 151 struct { 152 u16 compression_algos; 153 u16 checksum_algos; 154 u32 deflate_capabilities; 155 u32 resrvd6; 156 u32 deprecated; 157 }; 158 /* ICP_QAT_FW_CRYPTO_CAPABILITY_GET */ 159 struct { 160 u32 cipher_algos; 161 u32 hash_algos; 162 u16 keygen_algos; 163 u16 other; 164 u16 public_key_algos; 165 u16 prime_algos; 166 }; 167 /* ICP_QAT_FW_RL_DU_STOP */ 168 struct { 169 u32 resrvd7; 170 u8 granularity; 171 u8 resrvd8; 172 u16 resrvd9; 173 u32 total_du_time; 174 u32 resrvd10; 175 }; 176 /* ICP_QAT_FW_TIMER_GET */ 177 struct { 178 u64 timestamp; 179 u64 resrvd11; 180 }; 181 /* ICP_QAT_FW_COUNTERS_GET */ 182 struct { 183 u64 req_rec_count; 184 u64 resp_sent_count; 185 }; 186 /* ICP_QAT_FW_PKE_REPLAY_STATS_GET */ 187 struct { 188 u32 successful_count; 189 u32 unsuccessful_count; 190 u64 resrvd12; 191 }; 192 }; 193 } __packed; 194 195 enum icp_qat_fw_init_admin_init_flag { ICP_QAT_FW_INIT_FLAG_PKE_DISABLED = 0 }; 196 197 struct icp_qat_fw_init_admin_hb_cnt { 198 u16 resp_heartbeat_cnt; 199 u16 req_heartbeat_cnt; 200 }; 201 202 #define ICP_QAT_FW_COMN_HEARTBEAT_OK 0 203 #define ICP_QAT_FW_COMN_HEARTBEAT_BLOCKED 1 204 #define ICP_QAT_FW_COMN_HEARTBEAT_FLAG_BITPOS 0 205 #define ICP_QAT_FW_COMN_HEARTBEAT_FLAG_MASK 0x1 206 #define ICP_QAT_FW_COMN_STATUS_RESRVD_FLD_MASK 0xFE 207 #define ICP_QAT_FW_COMN_HEARTBEAT_HDR_FLAG_GET(hdr_t) \ 208 ICP_QAT_FW_COMN_HEARTBEAT_FLAG_GET(hdr_t.flags) 209 210 #define ICP_QAT_FW_COMN_HEARTBEAT_HDR_FLAG_SET(hdr_t, val) \ 211 ICP_QAT_FW_COMN_HEARTBEAT_FLAG_SET(hdr_t, val) 212 213 #define ICP_QAT_FW_COMN_HEARTBEAT_FLAG_GET(flags) \ 214 QAT_FIELD_GET(flags, \ 215 ICP_QAT_FW_COMN_HEARTBEAT_FLAG_BITPOS, \ 216 ICP_QAT_FW_COMN_HEARTBEAT_FLAG_MASK) 217 #endif 218