1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2023, Intel Corporation. */
3
4 #ifndef _ICE_TYPE_H_
5 #define _ICE_TYPE_H_
6
7 #define ICE_BYTES_PER_WORD 2
8 #define ICE_BYTES_PER_DWORD 4
9 #define ICE_CHNL_MAX_TC 16
10
11 #include "ice_hw_autogen.h"
12 #include "ice_devids.h"
13 #include "ice_osdep.h"
14 #include "ice_controlq.h"
15 #include "ice_lan_tx_rx.h"
16 #include "ice_flex_type.h"
17 #include "ice_protocol_type.h"
18 #include "ice_sbq_cmd.h"
19 #include "ice_vlan_mode.h"
20 #include "ice_fwlog.h"
21 #include <linux/wait.h>
22 #include <net/dscp.h>
23
ice_is_tc_ena(unsigned long bitmap,u8 tc)24 static inline bool ice_is_tc_ena(unsigned long bitmap, u8 tc)
25 {
26 return test_bit(tc, &bitmap);
27 }
28
round_up_64bit(u64 a,u32 b)29 static inline u64 round_up_64bit(u64 a, u32 b)
30 {
31 return div64_long(((a) + (b) / 2), (b));
32 }
33
ice_round_to_num(u32 N,u32 R)34 static inline u32 ice_round_to_num(u32 N, u32 R)
35 {
36 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) :
37 ((((N) + (R) - 1) / (R)) * (R)));
38 }
39
40 /* Driver always calls main vsi_handle first */
41 #define ICE_MAIN_VSI_HANDLE 0
42
43 /* debug masks - set these bits in hw->debug_mask to control output */
44 #define ICE_DBG_INIT BIT_ULL(1)
45 #define ICE_DBG_FW_LOG BIT_ULL(3)
46 #define ICE_DBG_LINK BIT_ULL(4)
47 #define ICE_DBG_PHY BIT_ULL(5)
48 #define ICE_DBG_QCTX BIT_ULL(6)
49 #define ICE_DBG_NVM BIT_ULL(7)
50 #define ICE_DBG_LAN BIT_ULL(8)
51 #define ICE_DBG_FLOW BIT_ULL(9)
52 #define ICE_DBG_SW BIT_ULL(13)
53 #define ICE_DBG_SCHED BIT_ULL(14)
54 #define ICE_DBG_RDMA BIT_ULL(15)
55 #define ICE_DBG_PKG BIT_ULL(16)
56 #define ICE_DBG_RES BIT_ULL(17)
57 #define ICE_DBG_PTP BIT_ULL(19)
58 #define ICE_DBG_AQ_MSG BIT_ULL(24)
59 #define ICE_DBG_AQ_DESC BIT_ULL(25)
60 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26)
61 #define ICE_DBG_AQ_CMD BIT_ULL(27)
62 #define ICE_DBG_AQ (ICE_DBG_AQ_MSG | \
63 ICE_DBG_AQ_DESC | \
64 ICE_DBG_AQ_DESC_BUF | \
65 ICE_DBG_AQ_CMD)
66 #define ICE_DBG_PARSER BIT_ULL(28)
67
68 #define ICE_DBG_USER BIT_ULL(31)
69
70 enum ice_aq_res_ids {
71 ICE_NVM_RES_ID = 1,
72 ICE_SPD_RES_ID,
73 ICE_CHANGE_LOCK_RES_ID,
74 ICE_GLOBAL_CFG_LOCK_RES_ID
75 };
76
77 enum ice_fec_stats_types {
78 ICE_FEC_CORR_LOW,
79 ICE_FEC_CORR_HIGH,
80 ICE_FEC_UNCORR_LOW,
81 ICE_FEC_UNCORR_HIGH,
82 ICE_FEC_MAX
83 };
84
85 /* FW update timeout definitions are in milliseconds */
86 #define ICE_NVM_TIMEOUT 180000
87 #define ICE_CHANGE_LOCK_TIMEOUT 1000
88 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 5000
89
90 enum ice_aq_res_access_type {
91 ICE_RES_READ = 1,
92 ICE_RES_WRITE
93 };
94
95 struct ice_driver_ver {
96 u8 major_ver;
97 u8 minor_ver;
98 u8 build_ver;
99 u8 subbuild_ver;
100 u8 driver_string[32];
101 };
102
103 enum ice_fc_mode {
104 ICE_FC_NONE = 0,
105 ICE_FC_RX_PAUSE,
106 ICE_FC_TX_PAUSE,
107 ICE_FC_FULL,
108 ICE_FC_PFC,
109 ICE_FC_DFLT
110 };
111
112 enum ice_phy_cache_mode {
113 ICE_FC_MODE = 0,
114 ICE_SPEED_MODE,
115 ICE_FEC_MODE
116 };
117
118 enum ice_fec_mode {
119 ICE_FEC_NONE = 0,
120 ICE_FEC_RS,
121 ICE_FEC_BASER,
122 ICE_FEC_AUTO
123 };
124
125 struct ice_phy_cache_mode_data {
126 union {
127 enum ice_fec_mode curr_user_fec_req;
128 enum ice_fc_mode curr_user_fc_req;
129 u16 curr_user_speed_req;
130 } data;
131 };
132
133 enum ice_set_fc_aq_failures {
134 ICE_SET_FC_AQ_FAIL_NONE = 0,
135 ICE_SET_FC_AQ_FAIL_GET,
136 ICE_SET_FC_AQ_FAIL_SET,
137 ICE_SET_FC_AQ_FAIL_UPDATE
138 };
139
140 /* Various MAC types */
141 enum ice_mac_type {
142 ICE_MAC_UNKNOWN = 0,
143 ICE_MAC_E810,
144 ICE_MAC_E830,
145 ICE_MAC_GENERIC,
146 ICE_MAC_GENERIC_3K_E825,
147 };
148
149 /* Media Types */
150 enum ice_media_type {
151 ICE_MEDIA_UNKNOWN = 0,
152 ICE_MEDIA_FIBER,
153 ICE_MEDIA_BASET,
154 ICE_MEDIA_BACKPLANE,
155 ICE_MEDIA_DA,
156 };
157
158 enum ice_vsi_type {
159 ICE_VSI_PF = 0,
160 ICE_VSI_VF = 1,
161 ICE_VSI_CTRL = 3, /* equates to ICE_VSI_PF with 1 queue pair */
162 ICE_VSI_CHNL = 4,
163 ICE_VSI_LB = 6,
164 ICE_VSI_SF = 9,
165 };
166
167 struct ice_link_status {
168 /* Refer to ice_aq_phy_type for bits definition */
169 u64 phy_type_low;
170 u64 phy_type_high;
171 u8 topo_media_conflict;
172 u16 max_frame_size;
173 u16 link_speed;
174 u16 req_speeds;
175 u8 link_cfg_err;
176 u8 lse_ena; /* Link Status Event notification */
177 u8 link_info;
178 u8 an_info;
179 u8 ext_info;
180 u8 fec_info;
181 u8 pacing;
182 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of
183 * ice_aqc_get_phy_caps structure
184 */
185 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
186 };
187
188 /* Different reset sources for which a disable queue AQ call has to be made in
189 * order to clean the Tx scheduler as a part of the reset
190 */
191 enum ice_disq_rst_src {
192 ICE_NO_RESET = 0,
193 ICE_VM_RESET,
194 ICE_VF_RESET,
195 };
196
197 /* PHY info such as phy_type, etc... */
198 struct ice_phy_info {
199 struct ice_link_status link_info;
200 struct ice_link_status link_info_old;
201 u64 phy_type_low;
202 u64 phy_type_high;
203 enum ice_media_type media_type;
204 u8 get_link_info;
205 /* Please refer to struct ice_aqc_get_link_status_data to get
206 * detail of enable bit in curr_user_speed_req
207 */
208 u16 curr_user_speed_req;
209 enum ice_fec_mode curr_user_fec_req;
210 enum ice_fc_mode curr_user_fc_req;
211 struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg;
212 };
213
214 /* protocol enumeration for filters */
215 enum ice_fltr_ptype {
216 /* NONE - used for undef/error */
217 ICE_FLTR_PTYPE_NONF_NONE = 0,
218 ICE_FLTR_PTYPE_NONF_ETH,
219 ICE_FLTR_PTYPE_NONF_IPV4_UDP,
220 ICE_FLTR_PTYPE_NONF_IPV4_TCP,
221 ICE_FLTR_PTYPE_NONF_IPV4_SCTP,
222 ICE_FLTR_PTYPE_NONF_IPV4_OTHER,
223 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP,
224 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP,
225 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_ICMP,
226 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_OTHER,
227 ICE_FLTR_PTYPE_NONF_IPV6_GTPU_IPV6_OTHER,
228 ICE_FLTR_PTYPE_NONF_IPV4_L2TPV3,
229 ICE_FLTR_PTYPE_NONF_IPV6_L2TPV3,
230 ICE_FLTR_PTYPE_NONF_IPV4_ESP,
231 ICE_FLTR_PTYPE_NONF_IPV6_ESP,
232 ICE_FLTR_PTYPE_NONF_IPV4_AH,
233 ICE_FLTR_PTYPE_NONF_IPV6_AH,
234 ICE_FLTR_PTYPE_NONF_IPV4_NAT_T_ESP,
235 ICE_FLTR_PTYPE_NONF_IPV6_NAT_T_ESP,
236 ICE_FLTR_PTYPE_NONF_IPV4_PFCP_NODE,
237 ICE_FLTR_PTYPE_NONF_IPV4_PFCP_SESSION,
238 ICE_FLTR_PTYPE_NONF_IPV6_PFCP_NODE,
239 ICE_FLTR_PTYPE_NONF_IPV6_PFCP_SESSION,
240 ICE_FLTR_PTYPE_NON_IP_L2,
241 ICE_FLTR_PTYPE_FRAG_IPV4,
242 ICE_FLTR_PTYPE_NONF_IPV6_UDP,
243 ICE_FLTR_PTYPE_NONF_IPV6_TCP,
244 ICE_FLTR_PTYPE_NONF_IPV6_SCTP,
245 ICE_FLTR_PTYPE_NONF_IPV6_OTHER,
246 ICE_FLTR_PTYPE_MAX,
247 };
248
249 enum ice_fd_hw_seg {
250 ICE_FD_HW_SEG_NON_TUN = 0,
251 ICE_FD_HW_SEG_TUN,
252 ICE_FD_HW_SEG_MAX,
253 };
254
255 /* 1 ICE_VSI_PF + 1 ICE_VSI_CTRL + ICE_CHNL_MAX_TC */
256 #define ICE_MAX_FDIR_VSI_PER_FILTER (2 + ICE_CHNL_MAX_TC)
257
258 struct ice_fd_hw_prof {
259 struct ice_flow_seg_info *fdir_seg[ICE_FD_HW_SEG_MAX];
260 int cnt;
261 u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER][ICE_FD_HW_SEG_MAX];
262 u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER];
263 u64 prof_id[ICE_FD_HW_SEG_MAX];
264 };
265
266 /* Common HW capabilities for SW use */
267 struct ice_hw_common_caps {
268 u32 valid_functions;
269 /* DCB capabilities */
270 u32 active_tc_bitmap;
271 u32 maxtc;
272
273 /* Tx/Rx queues */
274 u16 num_rxq; /* Number/Total Rx queues */
275 u16 rxq_first_id; /* First queue ID for Rx queues */
276 u16 num_txq; /* Number/Total Tx queues */
277 u16 txq_first_id; /* First queue ID for Tx queues */
278
279 /* MSI-X vectors */
280 u16 num_msix_vectors;
281 u16 msix_vector_first_id;
282
283 /* Max MTU for function or device */
284 u16 max_mtu;
285
286 /* Virtualization support */
287 u8 sr_iov_1_1; /* SR-IOV enabled */
288
289 /* RSS related capabilities */
290 u16 rss_table_size; /* 512 for PFs and 64 for VFs */
291 u8 rss_table_entry_width; /* RSS Entry width in bits */
292
293 u8 dcb;
294 u8 ieee_1588;
295 u8 rdma;
296 u8 roce_lag;
297 u8 sriov_lag;
298
299 bool nvm_update_pending_nvm;
300 bool nvm_update_pending_orom;
301 bool nvm_update_pending_netlist;
302 #define ICE_NVM_PENDING_NVM_IMAGE BIT(0)
303 #define ICE_NVM_PENDING_OROM BIT(1)
304 #define ICE_NVM_PENDING_NETLIST BIT(2)
305 bool nvm_unified_update;
306 #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3)
307 /* PCIe reset avoidance */
308 bool pcie_reset_avoidance;
309 /* Post update reset restriction */
310 bool reset_restrict_support;
311 bool tx_sched_topo_comp_mode_en;
312 };
313
314 /* IEEE 1588 TIME_SYNC specific info */
315 /* Function specific definitions */
316 #define ICE_TS_FUNC_ENA_M BIT(0)
317 #define ICE_TS_SRC_TMR_OWND_M BIT(1)
318 #define ICE_TS_TMR_ENA_M BIT(2)
319 #define ICE_TS_TMR_IDX_OWND_S 4
320 #define ICE_TS_TMR_IDX_OWND_M BIT(4)
321 #define ICE_TS_CLK_FREQ_S 16
322 #define ICE_TS_CLK_FREQ_M ICE_M(0x7, ICE_TS_CLK_FREQ_S)
323 #define ICE_TS_CLK_SRC_S 20
324 #define ICE_TS_CLK_SRC_M BIT(20)
325 #define ICE_TS_TMR_IDX_ASSOC_S 24
326 #define ICE_TS_TMR_IDX_ASSOC_M BIT(24)
327
328 /* TIME_REF clock rate specification */
329 enum ice_time_ref_freq {
330 ICE_TIME_REF_FREQ_25_000 = 0,
331 ICE_TIME_REF_FREQ_122_880 = 1,
332 ICE_TIME_REF_FREQ_125_000 = 2,
333 ICE_TIME_REF_FREQ_153_600 = 3,
334 ICE_TIME_REF_FREQ_156_250 = 4,
335 ICE_TIME_REF_FREQ_245_760 = 5,
336
337 NUM_ICE_TIME_REF_FREQ,
338
339 ICE_TIME_REF_FREQ_INVALID = -1,
340 };
341
342 /* Clock source specification */
343 enum ice_clk_src {
344 ICE_CLK_SRC_TCXO = 0, /* Temperature compensated oscillator */
345 ICE_CLK_SRC_TIME_REF = 1, /* Use TIME_REF reference clock */
346
347 NUM_ICE_CLK_SRC
348 };
349
350 struct ice_ts_func_info {
351 /* Function specific info */
352 enum ice_time_ref_freq time_ref;
353 u8 clk_freq;
354 u8 clk_src;
355 u8 tmr_index_assoc;
356 u8 ena;
357 u8 tmr_index_owned;
358 u8 src_tmr_owned;
359 u8 tmr_ena;
360 };
361
362 /* Device specific definitions */
363 #define ICE_TS_TMR0_OWNR_M 0x7
364 #define ICE_TS_TMR0_OWND_M BIT(3)
365 #define ICE_TS_TMR1_OWNR_S 4
366 #define ICE_TS_TMR1_OWNR_M ICE_M(0x7, ICE_TS_TMR1_OWNR_S)
367 #define ICE_TS_TMR1_OWND_M BIT(7)
368 #define ICE_TS_DEV_ENA_M BIT(24)
369 #define ICE_TS_TMR0_ENA_M BIT(25)
370 #define ICE_TS_TMR1_ENA_M BIT(26)
371 #define ICE_TS_LL_TX_TS_READ_M BIT(28)
372 #define ICE_TS_LL_TX_TS_INT_READ_M BIT(29)
373 #define ICE_TS_LL_PHY_TMR_UPDATE_M BIT(30)
374
375 struct ice_ts_dev_info {
376 /* Device specific info */
377 u32 ena_ports;
378 u32 tmr_own_map;
379 u32 tmr0_owner;
380 u32 tmr1_owner;
381 u8 tmr0_owned;
382 u8 tmr1_owned;
383 u8 ena;
384 u8 tmr0_ena;
385 u8 tmr1_ena;
386 u8 ts_ll_read;
387 u8 ts_ll_int_read;
388 u8 ll_phy_tmr_update;
389 };
390
391 #define ICE_NAC_TOPO_PRIMARY_M BIT(0)
392 #define ICE_NAC_TOPO_DUAL_M BIT(1)
393 #define ICE_NAC_TOPO_ID_M GENMASK(0xF, 0)
394
395 struct ice_nac_topology {
396 u32 mode;
397 u8 id;
398 };
399
400 /* Function specific capabilities */
401 struct ice_hw_func_caps {
402 struct ice_hw_common_caps common_cap;
403 u32 num_allocd_vfs; /* Number of allocated VFs */
404 u32 vf_base_id; /* Logical ID of the first VF */
405 u32 guar_num_vsi;
406 u32 fd_fltr_guar; /* Number of filters guaranteed */
407 u32 fd_fltr_best_effort; /* Number of best effort filters */
408 struct ice_ts_func_info ts_func_info;
409 };
410
411 #define ICE_SENSOR_SUPPORT_E810_INT_TEMP_BIT 0
412
413 /* Device wide capabilities */
414 struct ice_hw_dev_caps {
415 struct ice_hw_common_caps common_cap;
416 u32 num_vfs_exposed; /* Total number of VFs exposed */
417 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
418 u32 num_flow_director_fltr; /* Number of FD filters available */
419 struct ice_ts_dev_info ts_dev_info;
420 u32 num_funcs;
421 struct ice_nac_topology nac_topo;
422 /* bitmap of supported sensors
423 * bit 0 - internal temperature sensor
424 * bit 31:1 - Reserved
425 */
426 u32 supported_sensors;
427 };
428
429 /* MAC info */
430 struct ice_mac_info {
431 u8 lan_addr[ETH_ALEN];
432 u8 perm_addr[ETH_ALEN];
433 };
434
435 /* Reset types used to determine which kind of reset was requested. These
436 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register.
437 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register
438 * because its reset source is different than the other types listed.
439 */
440 enum ice_reset_req {
441 ICE_RESET_POR = 0,
442 ICE_RESET_INVAL = 0,
443 ICE_RESET_CORER = 1,
444 ICE_RESET_GLOBR = 2,
445 ICE_RESET_EMPR = 3,
446 ICE_RESET_PFR = 4,
447 };
448
449 /* Bus parameters */
450 struct ice_bus_info {
451 u16 device;
452 u8 func;
453 };
454
455 /* Flow control (FC) parameters */
456 struct ice_fc_info {
457 enum ice_fc_mode current_mode; /* FC mode in effect */
458 enum ice_fc_mode req_mode; /* FC mode requested by caller */
459 };
460
461 /* Option ROM version information */
462 struct ice_orom_info {
463 u8 major; /* Major version of OROM */
464 u8 patch; /* Patch version of OROM */
465 u16 build; /* Build version of OROM */
466 };
467
468 /* NVM version information */
469 struct ice_nvm_info {
470 u32 eetrack;
471 u8 major;
472 u8 minor;
473 };
474
475 /* netlist version information */
476 struct ice_netlist_info {
477 u32 major; /* major high/low */
478 u32 minor; /* minor high/low */
479 u32 type; /* type high/low */
480 u32 rev; /* revision high/low */
481 u32 hash; /* SHA-1 hash word */
482 u16 cust_ver; /* customer version */
483 };
484
485 /* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules
486 * of the flash image.
487 */
488 enum ice_flash_bank {
489 ICE_INVALID_FLASH_BANK,
490 ICE_1ST_FLASH_BANK,
491 ICE_2ND_FLASH_BANK,
492 };
493
494 /* Enumeration of which flash bank is desired to read from, either the active
495 * bank or the inactive bank. Used to abstract 1st and 2nd bank notion from
496 * code which just wants to read the active or inactive flash bank.
497 */
498 enum ice_bank_select {
499 ICE_ACTIVE_FLASH_BANK,
500 ICE_INACTIVE_FLASH_BANK,
501 };
502
503 /* information for accessing NVM, OROM, and Netlist flash banks */
504 struct ice_bank_info {
505 u32 nvm_ptr; /* Pointer to 1st NVM bank */
506 u32 nvm_size; /* Size of NVM bank */
507 u32 orom_ptr; /* Pointer to 1st OROM bank */
508 u32 orom_size; /* Size of OROM bank */
509 u32 netlist_ptr; /* Pointer to 1st Netlist bank */
510 u32 netlist_size; /* Size of Netlist bank */
511 u32 active_css_hdr_len; /* Active CSS header length */
512 u32 inactive_css_hdr_len; /* Inactive CSS header length */
513 enum ice_flash_bank nvm_bank; /* Active NVM bank */
514 enum ice_flash_bank orom_bank; /* Active OROM bank */
515 enum ice_flash_bank netlist_bank; /* Active Netlist bank */
516 };
517
518 /* Flash Chip Information */
519 struct ice_flash_info {
520 struct ice_orom_info orom; /* Option ROM version info */
521 struct ice_nvm_info nvm; /* NVM version information */
522 struct ice_netlist_info netlist;/* Netlist version info */
523 struct ice_bank_info banks; /* Flash Bank information */
524 u16 sr_words; /* Shadow RAM size in words */
525 u32 flash_size; /* Size of available flash in bytes */
526 u8 blank_nvm_mode; /* is NVM empty (no FW present) */
527 };
528
529 struct ice_link_default_override_tlv {
530 u8 options;
531 #define ICE_LINK_OVERRIDE_OPT_M 0x3F
532 #define ICE_LINK_OVERRIDE_STRICT_MODE BIT(0)
533 #define ICE_LINK_OVERRIDE_EPCT_DIS BIT(1)
534 #define ICE_LINK_OVERRIDE_PORT_DIS BIT(2)
535 #define ICE_LINK_OVERRIDE_EN BIT(3)
536 #define ICE_LINK_OVERRIDE_AUTO_LINK_DIS BIT(4)
537 #define ICE_LINK_OVERRIDE_EEE_EN BIT(5)
538 u8 phy_config;
539 #define ICE_LINK_OVERRIDE_PHY_CFG_S 8
540 #define ICE_LINK_OVERRIDE_PHY_CFG_M (0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S)
541 #define ICE_LINK_OVERRIDE_PAUSE_M 0x3
542 #define ICE_LINK_OVERRIDE_LESM_EN BIT(6)
543 #define ICE_LINK_OVERRIDE_AUTO_FEC_EN BIT(7)
544 u8 fec_options;
545 #define ICE_LINK_OVERRIDE_FEC_OPT_M 0xFF
546 u8 rsvd1;
547 u64 phy_type_low;
548 u64 phy_type_high;
549 };
550
551 #define ICE_NVM_VER_LEN 32
552
553 /* Max number of port to queue branches w.r.t topology */
554 #define ICE_MAX_TRAFFIC_CLASS 8
555 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
556
557 #define ice_for_each_traffic_class(_i) \
558 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++)
559
560 /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects
561 * to driver defined policy for default aggregator
562 */
563 #define ICE_INVAL_TEID 0xFFFFFFFF
564 #define ICE_DFLT_AGG_ID 0
565
566 struct ice_sched_node {
567 struct ice_sched_node *parent;
568 struct ice_sched_node *sibling; /* next sibling in the same layer */
569 struct ice_sched_node **children;
570 struct ice_aqc_txsched_elem_data info;
571 char *name;
572 struct devlink_rate *rate_node;
573 u64 tx_max;
574 u64 tx_share;
575 u32 agg_id; /* aggregator group ID */
576 u32 id;
577 u32 tx_priority;
578 u32 tx_weight;
579 u16 vsi_handle;
580 u8 in_use; /* suspended or in use */
581 u8 tx_sched_layer; /* Logical Layer (1-9) */
582 u8 num_children;
583 u8 tc_num;
584 u8 owner;
585 #define ICE_SCHED_NODE_OWNER_LAN 0
586 #define ICE_SCHED_NODE_OWNER_RDMA 2
587 };
588
589 /* Access Macros for Tx Sched Elements data */
590 #define ICE_TXSCHED_GET_NODE_TEID(x) le32_to_cpu((x)->info.node_teid)
591
592 /* The aggregator type determines if identifier is for a VSI group,
593 * aggregator group, aggregator of queues, or queue group.
594 */
595 enum ice_agg_type {
596 ICE_AGG_TYPE_UNKNOWN = 0,
597 ICE_AGG_TYPE_VSI,
598 ICE_AGG_TYPE_AGG, /* aggregator */
599 ICE_AGG_TYPE_Q,
600 ICE_AGG_TYPE_QG
601 };
602
603 /* Rate limit types */
604 enum ice_rl_type {
605 ICE_UNKNOWN_BW = 0,
606 ICE_MIN_BW, /* for CIR profile */
607 ICE_MAX_BW, /* for EIR profile */
608 ICE_SHARED_BW /* for shared profile */
609 };
610
611 #define ICE_SCHED_MIN_BW 500 /* in Kbps */
612 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */
613 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */
614 #define ICE_SCHED_DFLT_RL_PROF_ID 0
615 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF
616 #define ICE_SCHED_DFLT_BW_WT 4
617 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF
618 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */
619
620 #define ICE_MAX_PORT_PER_PCI_DEV 8
621
622 /* Data structure for saving BW information */
623 enum ice_bw_type {
624 ICE_BW_TYPE_PRIO,
625 ICE_BW_TYPE_CIR,
626 ICE_BW_TYPE_CIR_WT,
627 ICE_BW_TYPE_EIR,
628 ICE_BW_TYPE_EIR_WT,
629 ICE_BW_TYPE_SHARED,
630 ICE_BW_TYPE_CNT /* This must be last */
631 };
632
633 struct ice_bw {
634 u32 bw;
635 u16 bw_alloc;
636 };
637
638 struct ice_bw_type_info {
639 DECLARE_BITMAP(bw_t_bitmap, ICE_BW_TYPE_CNT);
640 u8 generic;
641 struct ice_bw cir_bw;
642 struct ice_bw eir_bw;
643 u32 shared_bw;
644 };
645
646 /* VSI queue context structure for given TC */
647 struct ice_q_ctx {
648 u16 q_handle;
649 u32 q_teid;
650 /* bw_t_info saves queue BW information */
651 struct ice_bw_type_info bw_t_info;
652 };
653
654 /* VSI type list entry to locate corresponding VSI/aggregator nodes */
655 struct ice_sched_vsi_info {
656 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
657 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];
658 struct list_head list_entry;
659 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS];
660 u16 max_rdmaq[ICE_MAX_TRAFFIC_CLASS];
661 /* bw_t_info saves VSI BW information */
662 struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS];
663 };
664
665 /* driver defines the policy */
666 struct ice_sched_tx_policy {
667 u16 max_num_vsis;
668 u8 max_num_lan_qs_per_tc[ICE_MAX_TRAFFIC_CLASS];
669 u8 rdma_ena;
670 };
671
672 /* CEE or IEEE 802.1Qaz ETS Configuration data */
673 struct ice_dcb_ets_cfg {
674 u8 willing;
675 u8 cbs;
676 u8 maxtcs;
677 u8 prio_table[ICE_MAX_TRAFFIC_CLASS];
678 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS];
679 u8 tsatable[ICE_MAX_TRAFFIC_CLASS];
680 };
681
682 /* CEE or IEEE 802.1Qaz PFC Configuration data */
683 struct ice_dcb_pfc_cfg {
684 u8 willing;
685 u8 mbc;
686 u8 pfccap;
687 u8 pfcena;
688 };
689
690 /* CEE or IEEE 802.1Qaz Application Priority data */
691 struct ice_dcb_app_priority_table {
692 u16 prot_id;
693 u8 priority;
694 u8 selector;
695 };
696
697 #define ICE_MAX_USER_PRIORITY 8
698 #define ICE_DCBX_MAX_APPS 64
699 #define ICE_LLDPDU_SIZE 1500
700 #define ICE_TLV_STATUS_OPER 0x1
701 #define ICE_TLV_STATUS_SYNC 0x2
702 #define ICE_TLV_STATUS_ERR 0x4
703 #define ICE_APP_PROT_ID_ISCSI_860 0x035c
704 #define ICE_APP_SEL_ETHTYPE 0x1
705 #define ICE_APP_SEL_TCPIP 0x2
706 #define ICE_CEE_APP_SEL_ETHTYPE 0x0
707 #define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR 0x134
708 #define ICE_CEE_APP_SEL_TCPIP 0x1
709
710 struct ice_dcbx_cfg {
711 u32 numapps;
712 u32 tlv_status; /* CEE mode TLV status */
713 struct ice_dcb_ets_cfg etscfg;
714 struct ice_dcb_ets_cfg etsrec;
715 struct ice_dcb_pfc_cfg pfc;
716 #define ICE_QOS_MODE_VLAN 0x0
717 #define ICE_QOS_MODE_DSCP 0x1
718 u8 pfc_mode;
719 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS];
720 /* when DSCP mapping defined by user set its bit to 1 */
721 DECLARE_BITMAP(dscp_mapped, DSCP_MAX);
722 /* array holding DSCP -> UP/TC values for DSCP L3 QoS mode */
723 u8 dscp_map[DSCP_MAX];
724 u8 dcbx_mode;
725 #define ICE_DCBX_MODE_CEE 0x1
726 #define ICE_DCBX_MODE_IEEE 0x2
727 u8 app_mode;
728 #define ICE_DCBX_APPS_NON_WILLING 0x1
729 };
730
731 struct ice_qos_cfg {
732 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */
733 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */
734 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */
735 u8 dcbx_status : 3; /* see ICE_DCBX_STATUS_DIS */
736 u8 is_sw_lldp : 1;
737 };
738
739 struct ice_port_info {
740 struct ice_sched_node *root; /* Root Node per Port */
741 struct ice_hw *hw; /* back pointer to HW instance */
742 u32 last_node_teid; /* scheduler last node info */
743 u16 sw_id; /* Initial switch ID belongs to port */
744 u16 pf_vf_num;
745 u8 port_state;
746 u8 local_fwd_mode;
747 #define ICE_SCHED_PORT_STATE_INIT 0x0
748 #define ICE_SCHED_PORT_STATE_READY 0x1
749 u8 lport;
750 #define ICE_LPORT_MASK 0xff
751 struct ice_fc_info fc;
752 struct ice_mac_info mac;
753 struct ice_phy_info phy;
754 struct mutex sched_lock; /* protect access to TXSched tree */
755 struct ice_sched_node *
756 sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM];
757 /* List contain profile ID(s) and other params per layer */
758 struct list_head rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
759 struct ice_qos_cfg qos_cfg;
760 struct xarray sched_node_ids;
761 u8 is_vf:1;
762 u8 is_custom_tx_enabled:1;
763 };
764
765 struct ice_switch_info {
766 struct list_head vsi_list_map_head;
767 struct ice_sw_recipe *recp_list;
768 u16 prof_res_bm_init;
769 u16 max_used_prof_index;
770 u16 rule_cnt;
771 u8 recp_cnt;
772
773 DECLARE_BITMAP(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS);
774 };
775
776 /* Enum defining the different states of the mailbox snapshot in the
777 * PF-VF mailbox overflow detection algorithm. The snapshot can be in
778 * states:
779 * 1. ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT - generate a new static snapshot
780 * within the mailbox buffer.
781 * 2. ICE_MAL_VF_DETECT_STATE_TRAVERSE - iterate through the mailbox snaphot
782 * 3. ICE_MAL_VF_DETECT_STATE_DETECT - track the messages sent per VF via the
783 * mailbox and mark any VFs sending more messages than the threshold limit set.
784 * 4. ICE_MAL_VF_DETECT_STATE_INVALID - Invalid mailbox state set to 0xFFFFFFFF.
785 */
786 enum ice_mbx_snapshot_state {
787 ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT = 0,
788 ICE_MAL_VF_DETECT_STATE_TRAVERSE,
789 ICE_MAL_VF_DETECT_STATE_DETECT,
790 ICE_MAL_VF_DETECT_STATE_INVALID = 0xFFFFFFFF,
791 };
792
793 /* Structure to hold information of the static snapshot and the mailbox
794 * buffer data used to generate and track the snapshot.
795 * 1. state: the state of the mailbox snapshot in the malicious VF
796 * detection state handler ice_mbx_vf_state_handler()
797 * 2. head: head of the mailbox snapshot in a circular mailbox buffer
798 * 3. tail: tail of the mailbox snapshot in a circular mailbox buffer
799 * 4. num_iterations: number of messages traversed in circular mailbox buffer
800 * 5. num_msg_proc: number of messages processed in mailbox
801 * 6. num_pending_arq: number of pending asynchronous messages
802 * 7. max_num_msgs_mbx: maximum messages in mailbox for currently
803 * serviced work item or interrupt.
804 */
805 struct ice_mbx_snap_buffer_data {
806 enum ice_mbx_snapshot_state state;
807 u32 head;
808 u32 tail;
809 u32 num_iterations;
810 u16 num_msg_proc;
811 u16 num_pending_arq;
812 u16 max_num_msgs_mbx;
813 };
814
815 /* Structure used to track a single VF's messages on the mailbox:
816 * 1. list_entry: linked list entry node
817 * 2. msg_count: the number of asynchronous messages sent by this VF
818 * 3. malicious: whether this VF has been detected as malicious before
819 */
820 struct ice_mbx_vf_info {
821 struct list_head list_entry;
822 u32 msg_count;
823 u8 malicious : 1;
824 };
825
826 /* Structure to hold data relevant to the captured static snapshot
827 * of the PF-VF mailbox.
828 */
829 struct ice_mbx_snapshot {
830 struct ice_mbx_snap_buffer_data mbx_buf;
831 struct list_head mbx_vf;
832 };
833
834 /* Structure to hold data to be used for capturing or updating a
835 * static snapshot.
836 * 1. num_msg_proc: number of messages processed in mailbox
837 * 2. num_pending_arq: number of pending asynchronous messages
838 * 3. max_num_msgs_mbx: maximum messages in mailbox for currently
839 * serviced work item or interrupt.
840 * 4. async_watermark_val: An upper threshold set by caller to determine
841 * if the pending arq count is large enough to assume that there is
842 * the possibility of a mailicious VF.
843 */
844 struct ice_mbx_data {
845 u16 num_msg_proc;
846 u16 num_pending_arq;
847 u16 max_num_msgs_mbx;
848 u16 async_watermark_val;
849 };
850
851 #define ICE_PORTS_PER_QUAD 4
852 #define ICE_GET_QUAD_NUM(port) ((port) / ICE_PORTS_PER_QUAD)
853
854 #define ATQBAL_FLAGS_INTR_IN_PROGRESS BIT(0)
855
856 struct ice_e810_params {
857 /* The wait queue lock also protects the low latency interface */
858 wait_queue_head_t atqbal_wq;
859 unsigned int atqbal_flags;
860 };
861
862 struct ice_eth56g_params {
863 u8 num_phys;
864 bool onestep_ena;
865 bool sfd_ena;
866 u32 peer_delay;
867 };
868
869 union ice_phy_params {
870 struct ice_e810_params e810;
871 struct ice_eth56g_params eth56g;
872 };
873
874 /* Global Link Topology */
875 enum ice_global_link_topo {
876 ICE_LINK_TOPO_UP_TO_2_LINKS,
877 ICE_LINK_TOPO_UP_TO_4_LINKS,
878 ICE_LINK_TOPO_UP_TO_8_LINKS,
879 ICE_LINK_TOPO_RESERVED,
880 };
881
882 struct ice_ptp_hw {
883 union ice_phy_params phy;
884 u8 num_lports;
885 u8 ports_per_phy;
886 };
887
888 /* Port hardware description */
889 struct ice_hw {
890 u8 __iomem *hw_addr;
891 void *back;
892 struct ice_aqc_layer_props *layer_info;
893 struct ice_port_info *port_info;
894 /* PSM clock frequency for calculating RL profile params */
895 u32 psm_clk_freq;
896 u64 debug_mask; /* bitmap for debug mask */
897 enum ice_mac_type mac_type;
898
899 u16 fd_ctr_base; /* FD counter base index */
900
901 /* pci info */
902 u16 device_id;
903 u16 vendor_id;
904 u16 subsystem_device_id;
905 u16 subsystem_vendor_id;
906 u8 revision_id;
907
908 u8 pf_id; /* device profile info */
909 u8 logical_pf_id;
910
911 u16 max_burst_size; /* driver sets this value */
912
913 u8 recp_reuse:1; /* indicates whether FW supports recipe reuse */
914
915 /* Tx Scheduler values */
916 u8 num_tx_sched_layers;
917 u8 num_tx_sched_phys_layers;
918 u8 flattened_layers;
919 u8 max_cgds;
920 u8 sw_entry_point_layer;
921 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];
922 struct list_head agg_list; /* lists all aggregator */
923
924 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];
925 u8 evb_veb; /* true for VEB, false for VEPA */
926 u8 reset_ongoing; /* true if HW is in reset, false otherwise */
927 struct ice_bus_info bus;
928 struct ice_flash_info flash;
929 struct ice_hw_dev_caps dev_caps; /* device capabilities */
930 struct ice_hw_func_caps func_caps; /* function capabilities */
931
932 struct ice_switch_info *switch_info; /* switch filter lists */
933
934 /* Control Queue info */
935 struct ice_ctl_q_info adminq;
936 struct ice_ctl_q_info sbq;
937 struct ice_ctl_q_info mailboxq;
938
939 u8 api_branch; /* API branch version */
940 u8 api_maj_ver; /* API major version */
941 u8 api_min_ver; /* API minor version */
942 u8 api_patch; /* API patch version */
943 u8 fw_branch; /* firmware branch version */
944 u8 fw_maj_ver; /* firmware major version */
945 u8 fw_min_ver; /* firmware minor version */
946 u8 fw_patch; /* firmware patch version */
947 u32 fw_build; /* firmware build number */
948
949 struct ice_fwlog_cfg fwlog_cfg;
950 bool fwlog_supported; /* does hardware support FW logging? */
951 struct ice_fwlog_ring fwlog_ring;
952
953 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
954 * register. Used for determining the ITR/INTRL granularity during
955 * initialization.
956 */
957 #define ICE_MAX_AGG_BW_200G 0x0
958 #define ICE_MAX_AGG_BW_100G 0X1
959 #define ICE_MAX_AGG_BW_50G 0x2
960 #define ICE_MAX_AGG_BW_25G 0x3
961 /* ITR granularity for different speeds */
962 #define ICE_ITR_GRAN_ABOVE_25 2
963 #define ICE_ITR_GRAN_MAX_25 4
964 /* ITR granularity in 1 us */
965 u8 itr_gran;
966 /* INTRL granularity for different speeds */
967 #define ICE_INTRL_GRAN_ABOVE_25 4
968 #define ICE_INTRL_GRAN_MAX_25 8
969 /* INTRL granularity in 1 us */
970 u8 intrl_gran;
971
972 struct ice_ptp_hw ptp;
973 s8 lane_num;
974
975 /* Active package version (currently active) */
976 struct ice_pkg_ver active_pkg_ver;
977 u32 pkg_seg_id;
978 u32 pkg_sign_type;
979 u32 active_track_id;
980 u8 pkg_has_signing_seg:1;
981 u8 active_pkg_name[ICE_PKG_NAME_SIZE];
982 u8 active_pkg_in_nvm;
983
984 /* Driver's package ver - (from the Ice Metadata section) */
985 struct ice_pkg_ver pkg_ver;
986 u8 pkg_name[ICE_PKG_NAME_SIZE];
987
988 /* Driver's Ice segment format version and ID (from the Ice seg) */
989 struct ice_pkg_ver ice_seg_fmt_ver;
990 u8 ice_seg_id[ICE_SEG_ID_SIZE];
991
992 /* Pointer to the ice segment */
993 struct ice_seg *seg;
994
995 /* Pointer to allocated copy of pkg memory */
996 u8 *pkg_copy;
997 u32 pkg_size;
998
999 /* tunneling info */
1000 struct mutex tnl_lock;
1001 struct ice_tunnel_table tnl;
1002
1003 struct udp_tunnel_nic_shared udp_tunnel_shared;
1004 struct udp_tunnel_nic_info udp_tunnel_nic;
1005
1006 /* dvm boost update information */
1007 struct ice_dvm_table dvm_upd;
1008
1009 /* HW block tables */
1010 struct ice_blk_info blk[ICE_BLK_COUNT];
1011 struct mutex fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */
1012 struct list_head fl_profs[ICE_BLK_COUNT];
1013
1014 /* Flow Director filter info */
1015 int fdir_active_fltr;
1016
1017 struct mutex fdir_fltr_lock; /* protect Flow Director */
1018 struct list_head fdir_list_head;
1019
1020 /* Book-keeping of side-band filter count per flow-type.
1021 * This is used to detect and handle input set changes for
1022 * respective flow-type.
1023 */
1024 u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX];
1025
1026 struct ice_fd_hw_prof **fdir_prof;
1027 DECLARE_BITMAP(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX);
1028 struct mutex rss_locks; /* protect RSS configuration */
1029 struct list_head rss_list_head;
1030 struct ice_mbx_snapshot mbx_snapshot;
1031 DECLARE_BITMAP(hw_ptype, ICE_FLOW_PTYPE_MAX);
1032 u8 dvm_ena;
1033 u16 io_expander_handle;
1034 u8 cgu_part_number;
1035 };
1036
1037 /* Statistics collected by each port, VSI, VEB, and S-channel */
1038 struct ice_eth_stats {
1039 u64 rx_bytes; /* gorc */
1040 u64 rx_unicast; /* uprc */
1041 u64 rx_multicast; /* mprc */
1042 u64 rx_broadcast; /* bprc */
1043 u64 rx_discards; /* rdpc */
1044 u64 rx_unknown_protocol; /* rupp */
1045 u64 tx_bytes; /* gotc */
1046 u64 tx_unicast; /* uptc */
1047 u64 tx_multicast; /* mptc */
1048 u64 tx_broadcast; /* bptc */
1049 u64 tx_discards; /* tdpc */
1050 u64 tx_errors; /* tepc */
1051 };
1052
1053 #define ICE_MAX_UP 8
1054
1055 /* Statistics collected by the MAC */
1056 struct ice_hw_port_stats {
1057 /* eth stats collected by the port */
1058 struct ice_eth_stats eth;
1059 /* additional port specific stats */
1060 u64 tx_dropped_link_down; /* tdold */
1061 u64 crc_errors; /* crcerrs */
1062 u64 illegal_bytes; /* illerrc */
1063 u64 error_bytes; /* errbc */
1064 u64 mac_local_faults; /* mlfc */
1065 u64 mac_remote_faults; /* mrfc */
1066 u64 link_xon_rx; /* lxonrxc */
1067 u64 link_xoff_rx; /* lxoffrxc */
1068 u64 link_xon_tx; /* lxontxc */
1069 u64 link_xoff_tx; /* lxofftxc */
1070 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1071 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1072 u64 priority_xon_tx[8]; /* pxontxc[8] */
1073 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1074 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1075 u64 rx_size_64; /* prc64 */
1076 u64 rx_size_127; /* prc127 */
1077 u64 rx_size_255; /* prc255 */
1078 u64 rx_size_511; /* prc511 */
1079 u64 rx_size_1023; /* prc1023 */
1080 u64 rx_size_1522; /* prc1522 */
1081 u64 rx_size_big; /* prc9522 */
1082 u64 rx_undersize; /* ruc */
1083 u64 rx_fragments; /* rfc */
1084 u64 rx_oversize; /* roc */
1085 u64 rx_jabber; /* rjc */
1086 u64 tx_size_64; /* ptc64 */
1087 u64 tx_size_127; /* ptc127 */
1088 u64 tx_size_255; /* ptc255 */
1089 u64 tx_size_511; /* ptc511 */
1090 u64 tx_size_1023; /* ptc1023 */
1091 u64 tx_size_1522; /* ptc1522 */
1092 u64 tx_size_big; /* ptc9522 */
1093 /* flow director stats */
1094 u32 fd_sb_status;
1095 u64 fd_sb_match;
1096 };
1097
1098 enum ice_sw_fwd_act_type {
1099 ICE_FWD_TO_VSI = 0,
1100 ICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */
1101 ICE_FWD_TO_Q,
1102 ICE_FWD_TO_QGRP,
1103 ICE_DROP_PACKET,
1104 ICE_MIRROR_PACKET,
1105 ICE_NOP,
1106 ICE_INVAL_ACT
1107 };
1108
1109 struct ice_aq_get_set_rss_lut_params {
1110 u8 *lut; /* input RSS LUT for set and output RSS LUT for get */
1111 enum ice_lut_size lut_size; /* size of the LUT buffer */
1112 enum ice_lut_type lut_type; /* type of the LUT (i.e. VSI, PF, Global) */
1113 u16 vsi_handle; /* software VSI handle */
1114 u8 global_lut_id; /* only valid when lut_type is global */
1115 };
1116
1117 /* Checksum and Shadow RAM pointers */
1118 #define ICE_SR_NVM_CTRL_WORD 0x00
1119 #define ICE_SR_BOOT_CFG_PTR 0x132
1120 #define ICE_SR_NVM_WOL_CFG 0x19
1121 #define ICE_NVM_OROM_VER_OFF 0x02
1122 #define ICE_SR_PBA_BLOCK_PTR 0x16
1123 #define ICE_SR_NVM_DEV_STARTER_VER 0x18
1124 #define ICE_SR_NVM_EETRACK_LO 0x2D
1125 #define ICE_SR_NVM_EETRACK_HI 0x2E
1126 #define ICE_NVM_VER_LO_SHIFT 0
1127 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT)
1128 #define ICE_NVM_VER_HI_SHIFT 12
1129 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT)
1130 #define ICE_OROM_VER_PATCH_SHIFT 0
1131 #define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT)
1132 #define ICE_OROM_VER_BUILD_SHIFT 8
1133 #define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT)
1134 #define ICE_OROM_VER_SHIFT 24
1135 #define ICE_OROM_VER_MASK (0xffU << ICE_OROM_VER_SHIFT)
1136 #define ICE_SR_PFA_PTR 0x40
1137 #define ICE_SR_1ST_NVM_BANK_PTR 0x42
1138 #define ICE_SR_NVM_BANK_SIZE 0x43
1139 #define ICE_SR_1ST_OROM_BANK_PTR 0x44
1140 #define ICE_SR_OROM_BANK_SIZE 0x45
1141 #define ICE_SR_NETLIST_BANK_PTR 0x46
1142 #define ICE_SR_NETLIST_BANK_SIZE 0x47
1143 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800
1144
1145 /* CSS Header words */
1146 #define ICE_NVM_CSS_HDR_LEN_L 0x02
1147 #define ICE_NVM_CSS_HDR_LEN_H 0x03
1148 #define ICE_NVM_CSS_SREV_L 0x14
1149 #define ICE_NVM_CSS_SREV_H 0x15
1150
1151 /* Length of Authentication header section in words */
1152 #define ICE_NVM_AUTH_HEADER_LEN 0x08
1153
1154 /* The Link Topology Netlist section is stored as a series of words. It is
1155 * stored in the NVM as a TLV, with the first two words containing the type
1156 * and length.
1157 */
1158 #define ICE_NETLIST_LINK_TOPO_MOD_ID 0x011B
1159 #define ICE_NETLIST_TYPE_OFFSET 0x0000
1160 #define ICE_NETLIST_LEN_OFFSET 0x0001
1161
1162 /* The Link Topology section follows the TLV header. When reading the netlist
1163 * using ice_read_netlist_module, we need to account for the 2-word TLV
1164 * header.
1165 */
1166 #define ICE_NETLIST_LINK_TOPO_OFFSET(n) ((n) + 2)
1167
1168 #define ICE_LINK_TOPO_MODULE_LEN ICE_NETLIST_LINK_TOPO_OFFSET(0x0000)
1169 #define ICE_LINK_TOPO_NODE_COUNT ICE_NETLIST_LINK_TOPO_OFFSET(0x0001)
1170
1171 #define ICE_LINK_TOPO_NODE_COUNT_M ICE_M(0x3FF, 0)
1172
1173 /* The Netlist ID Block is located after all of the Link Topology nodes. */
1174 #define ICE_NETLIST_ID_BLK_SIZE 0x30
1175 #define ICE_NETLIST_ID_BLK_OFFSET(n) ICE_NETLIST_LINK_TOPO_OFFSET(0x0004 + 2 * (n))
1176
1177 /* netlist ID block field offsets (word offsets) */
1178 #define ICE_NETLIST_ID_BLK_MAJOR_VER_LOW 0x02
1179 #define ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH 0x03
1180 #define ICE_NETLIST_ID_BLK_MINOR_VER_LOW 0x04
1181 #define ICE_NETLIST_ID_BLK_MINOR_VER_HIGH 0x05
1182 #define ICE_NETLIST_ID_BLK_TYPE_LOW 0x06
1183 #define ICE_NETLIST_ID_BLK_TYPE_HIGH 0x07
1184 #define ICE_NETLIST_ID_BLK_REV_LOW 0x08
1185 #define ICE_NETLIST_ID_BLK_REV_HIGH 0x09
1186 #define ICE_NETLIST_ID_BLK_SHA_HASH_WORD(n) (0x0A + (n))
1187 #define ICE_NETLIST_ID_BLK_CUST_VER 0x2F
1188
1189 /* Auxiliary field, mask, and shift definition for Shadow RAM and NVM Flash */
1190 #define ICE_SR_CTRL_WORD_1_S 0x06
1191 #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S)
1192 #define ICE_SR_CTRL_WORD_VALID 0x1
1193 #define ICE_SR_CTRL_WORD_OROM_BANK BIT(3)
1194 #define ICE_SR_CTRL_WORD_NETLIST_BANK BIT(4)
1195 #define ICE_SR_CTRL_WORD_NVM_BANK BIT(5)
1196
1197 #define ICE_SR_NVM_PTR_4KB_UNITS BIT(15)
1198
1199 /* Link override related */
1200 #define ICE_SR_PFA_LINK_OVERRIDE_WORDS 10
1201 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS 4
1202 #define ICE_SR_PFA_LINK_OVERRIDE_OFFSET 2
1203 #define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET 1
1204 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET 2
1205 #define ICE_FW_API_LINK_OVERRIDE_MAJ 1
1206 #define ICE_FW_API_LINK_OVERRIDE_MIN 5
1207 #define ICE_FW_API_LINK_OVERRIDE_PATCH 2
1208
1209 #define ICE_SR_WORDS_IN_1KB 512
1210
1211 /* AQ API version for LLDP_FILTER_CONTROL */
1212 #define ICE_FW_API_LLDP_FLTR_MAJ 1
1213 #define ICE_FW_API_LLDP_FLTR_MIN 7
1214 #define ICE_FW_API_LLDP_FLTR_PATCH 1
1215
1216 /* AQ API version for report default configuration */
1217 #define ICE_FW_API_REPORT_DFLT_CFG_MAJ 1
1218 #define ICE_FW_API_REPORT_DFLT_CFG_MIN 7
1219 #define ICE_FW_API_REPORT_DFLT_CFG_PATCH 3
1220
1221 /* AQ API version for Health Status support */
1222 #define ICE_FW_API_HEALTH_REPORT_MAJ 1
1223 #define ICE_FW_API_HEALTH_REPORT_MIN 7
1224 #define ICE_FW_API_HEALTH_REPORT_PATCH 6
1225
1226 #endif /* _ICE_TYPE_H_ */
1227