1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #ifndef _ICE_ADMINQ_CMD_H_ 5 #define _ICE_ADMINQ_CMD_H_ 6 7 #include <linux/net/intel/libie/adminq.h> 8 9 /* This header file defines the Admin Queue commands, error codes and 10 * descriptor format. It is shared between Firmware and Software. 11 */ 12 13 #define ICE_MAX_VSI 768 14 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9 15 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728 16 17 #define ICE_RXQ_CTX_SIZE_DWORDS 8 18 #define ICE_RXQ_CTX_SZ (ICE_RXQ_CTX_SIZE_DWORDS * sizeof(u32)) 19 20 typedef struct __packed { u8 buf[ICE_RXQ_CTX_SZ]; } ice_rxq_ctx_buf_t; 21 22 /* The Tx queue context is 40 bytes, and includes some internal state. The 23 * Admin Queue buffers don't include the internal state, so only include the 24 * first 22 bytes of the context. 25 */ 26 #define ICE_TXQ_CTX_SZ 22 27 28 typedef struct __packed { u8 buf[ICE_TXQ_CTX_SZ]; } ice_txq_ctx_buf_t; 29 30 #define ICE_TXQ_CTX_FULL_SIZE_DWORDS 10 31 #define ICE_TXQ_CTX_FULL_SZ \ 32 (ICE_TXQ_CTX_FULL_SIZE_DWORDS * sizeof(u32)) 33 34 typedef struct __packed { u8 buf[ICE_TXQ_CTX_FULL_SZ]; } ice_txq_ctx_buf_full_t; 35 36 /* Queue Shutdown (direct 0x0003) */ 37 struct ice_aqc_q_shutdown { 38 u8 driver_unloading; 39 #define ICE_AQC_DRIVER_UNLOADING BIT(0) 40 u8 reserved[15]; 41 }; 42 43 /* Manage MAC address, read command - indirect (0x0107) 44 * This struct is also used for the response 45 */ 46 struct ice_aqc_manage_mac_read { 47 __le16 flags; /* Zeroed by device driver */ 48 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4) 49 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5) 50 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6) 51 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7) 52 #define ICE_AQC_MAN_MAC_READ_S 4 53 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S) 54 u8 rsvd[2]; 55 u8 num_addr; /* Used in response */ 56 u8 rsvd1[3]; 57 __le32 addr_high; 58 __le32 addr_low; 59 }; 60 61 /* Response buffer format for manage MAC read command */ 62 struct ice_aqc_manage_mac_read_resp { 63 u8 lport_num; 64 u8 addr_type; 65 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0 66 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1 67 u8 mac_addr[ETH_ALEN]; 68 }; 69 70 /* Manage MAC address, write command - direct (0x0108) */ 71 struct ice_aqc_manage_mac_write { 72 u8 rsvd; 73 u8 flags; 74 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0) 75 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1) 76 #define ICE_AQC_MAN_MAC_WR_S 6 77 #define ICE_AQC_MAN_MAC_WR_M ICE_M(3, ICE_AQC_MAN_MAC_WR_S) 78 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0 79 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S) 80 /* byte stream in network order */ 81 u8 mac_addr[ETH_ALEN]; 82 __le32 addr_high; 83 __le32 addr_low; 84 }; 85 86 /* Clear PXE Command and response (direct 0x0110) */ 87 struct ice_aqc_clear_pxe { 88 u8 rx_cnt; 89 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2 90 u8 reserved[15]; 91 }; 92 93 /* Get switch configuration (0x0200) */ 94 struct ice_aqc_get_sw_cfg { 95 /* Reserved for command and copy of request flags for response */ 96 __le16 flags; 97 /* First desc in case of command and next_elem in case of response 98 * In case of response, if it is not zero, means all the configuration 99 * was not returned and new command shall be sent with this value in 100 * the 'first desc' field 101 */ 102 __le16 element; 103 /* Reserved for command, only used for response */ 104 __le16 num_elems; 105 __le16 rsvd; 106 __le32 addr_high; 107 __le32 addr_low; 108 }; 109 110 /* Each entry in the response buffer is of the following type: */ 111 struct ice_aqc_get_sw_cfg_resp_elem { 112 /* VSI/Port Number */ 113 __le16 vsi_port_num; 114 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0 115 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \ 116 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S) 117 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14 118 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S) 119 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0 120 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1 121 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2 122 123 /* SWID VSI/Port belongs to */ 124 __le16 swid; 125 126 /* Bit 14..0 : PF/VF number VSI belongs to 127 * Bit 15 : VF indication bit 128 */ 129 __le16 pf_vf_num; 130 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0 131 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \ 132 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S) 133 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) 134 }; 135 136 /* Loopback port parameter mode values. */ 137 enum ice_local_fwd_mode { 138 ICE_LOCAL_FWD_MODE_ENABLED = 0, 139 ICE_LOCAL_FWD_MODE_DISABLED = 1, 140 ICE_LOCAL_FWD_MODE_PRIORITIZED = 2, 141 }; 142 143 /* Set Port parameters, (direct, 0x0203) */ 144 struct ice_aqc_set_port_params { 145 __le16 cmd_flags; 146 #define ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA BIT(2) 147 __le16 bad_frame_vsi; 148 __le16 swid; 149 #define ICE_AQC_PORT_SWID_VALID BIT(15) 150 #define ICE_AQC_PORT_SWID_M 0xFF 151 u8 local_fwd_mode; 152 #define ICE_AQC_SET_P_PARAMS_LOCAL_FWD_MODE_VALID BIT(2) 153 u8 reserved[9]; 154 }; 155 156 /* These resource type defines are used for all switch resource 157 * commands where a resource type is required, such as: 158 * Get Resource Allocation command (indirect 0x0204) 159 * Allocate Resources command (indirect 0x0208) 160 * Free Resources command (indirect 0x0209) 161 * Get Allocated Resource Descriptors Command (indirect 0x020A) 162 * Share Resource command (indirect 0x020B) 163 */ 164 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03 165 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04 166 #define ICE_AQC_RES_TYPE_RECIPE 0x05 167 #define ICE_AQC_RES_TYPE_SWID 0x07 168 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21 169 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22 170 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23 171 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58 172 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59 173 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60 174 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61 175 176 #define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7) 177 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12) 178 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13) 179 #define ICE_AQC_RES_TYPE_FLAG_SUBSCRIBE_SHARED BIT(14) 180 #define ICE_AQC_RES_TYPE_FLAG_SUBSCRIBE_CTL BIT(15) 181 182 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00 183 184 #define ICE_AQC_RES_TYPE_S 0 185 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S) 186 187 /* Allocate Resources command (indirect 0x0208) 188 * Free Resources command (indirect 0x0209) 189 * Share Resource command (indirect 0x020B) 190 */ 191 struct ice_aqc_alloc_free_res_cmd { 192 __le16 num_entries; /* Number of Resource entries */ 193 u8 reserved[6]; 194 __le32 addr_high; 195 __le32 addr_low; 196 }; 197 198 /* Resource descriptor */ 199 struct ice_aqc_res_elem { 200 union { 201 __le16 sw_resp; 202 __le16 flu_resp; 203 } e; 204 }; 205 206 /* Buffer for Allocate/Free Resources commands */ 207 struct ice_aqc_alloc_free_res_elem { 208 __le16 res_type; /* Types defined above cmd 0x0204 */ 209 #define ICE_AQC_RES_TYPE_SHARED_S 7 210 #define ICE_AQC_RES_TYPE_SHARED_M (0x1 << ICE_AQC_RES_TYPE_SHARED_S) 211 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8 212 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \ 213 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S) 214 __le16 num_elems; 215 struct ice_aqc_res_elem elem[]; 216 }; 217 218 /* Request buffer for Set VLAN Mode AQ command (indirect 0x020C) */ 219 struct ice_aqc_set_vlan_mode { 220 u8 reserved; 221 u8 l2tag_prio_tagging; 222 #define ICE_AQ_VLAN_PRIO_TAG_S 0 223 #define ICE_AQ_VLAN_PRIO_TAG_M (0x7 << ICE_AQ_VLAN_PRIO_TAG_S) 224 #define ICE_AQ_VLAN_PRIO_TAG_NOT_SUPPORTED 0x0 225 #define ICE_AQ_VLAN_PRIO_TAG_STAG 0x1 226 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_CTAG 0x2 227 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_VLAN 0x3 228 #define ICE_AQ_VLAN_PRIO_TAG_INNER_CTAG 0x4 229 #define ICE_AQ_VLAN_PRIO_TAG_MAX 0x4 230 #define ICE_AQ_VLAN_PRIO_TAG_ERROR 0x7 231 u8 l2tag_reserved[64]; 232 u8 rdma_packet; 233 #define ICE_AQ_VLAN_RDMA_TAG_S 0 234 #define ICE_AQ_VLAN_RDMA_TAG_M (0x3F << ICE_AQ_VLAN_RDMA_TAG_S) 235 #define ICE_AQ_SVM_VLAN_RDMA_PKT_FLAG_SETTING 0x10 236 #define ICE_AQ_DVM_VLAN_RDMA_PKT_FLAG_SETTING 0x1A 237 u8 rdma_reserved[2]; 238 u8 mng_vlan_prot_id; 239 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_OUTER 0x10 240 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_INNER 0x11 241 u8 prot_id_reserved[30]; 242 }; 243 244 /* Response buffer for Get VLAN Mode AQ command (indirect 0x020D) */ 245 struct ice_aqc_get_vlan_mode { 246 u8 vlan_mode; 247 #define ICE_AQ_VLAN_MODE_DVM_ENA BIT(0) 248 u8 l2tag_prio_tagging; 249 u8 reserved[98]; 250 }; 251 252 /* Add VSI (indirect 0x0210) 253 * Update VSI (indirect 0x0211) 254 * Get VSI (indirect 0x0212) 255 * Free VSI (indirect 0x0213) 256 */ 257 struct ice_aqc_add_get_update_free_vsi { 258 __le16 vsi_num; 259 #define ICE_AQ_VSI_NUM_S 0 260 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S) 261 #define ICE_AQ_VSI_IS_VALID BIT(15) 262 __le16 cmd_flags; 263 #define ICE_AQ_VSI_KEEP_ALLOC 0x1 264 u8 vf_id; 265 u8 reserved; 266 __le16 vsi_flags; 267 #define ICE_AQ_VSI_TYPE_S 0 268 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S) 269 #define ICE_AQ_VSI_TYPE_VF 0x0 270 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1 271 #define ICE_AQ_VSI_TYPE_PF 0x2 272 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3 273 __le32 addr_high; 274 __le32 addr_low; 275 }; 276 277 /* Response descriptor for: 278 * Add VSI (indirect 0x0210) 279 * Update VSI (indirect 0x0211) 280 * Free VSI (indirect 0x0213) 281 */ 282 struct ice_aqc_add_update_free_vsi_resp { 283 __le16 vsi_num; 284 __le16 ext_status; 285 __le16 vsi_used; 286 __le16 vsi_free; 287 __le32 addr_high; 288 __le32 addr_low; 289 }; 290 291 struct ice_aqc_vsi_props { 292 __le16 valid_sections; 293 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0) 294 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1) 295 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2) 296 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3) 297 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4) 298 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5) 299 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6) 300 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7) 301 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8) 302 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11) 303 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12) 304 /* switch section */ 305 u8 sw_id; 306 u8 sw_flags; 307 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5) 308 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6) 309 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) 310 u8 sw_flags2; 311 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0 312 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) 313 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) 314 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) 315 u8 veb_stat_id; 316 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0 317 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) 318 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) 319 /* security section */ 320 u8 sec_flags; 321 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) 322 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) 323 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 324 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) 325 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) 326 u8 sec_reserved; 327 /* VLAN section */ 328 __le16 port_based_inner_vlan; /* VLANS include priority bits */ 329 u8 inner_vlan_reserved[2]; 330 u8 inner_vlan_flags; 331 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_S 0 332 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_TX_MODE_S) 333 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1 334 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED 0x2 335 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL 0x3 336 #define ICE_AQ_VSI_INNER_VLAN_INSERT_PVID BIT(2) 337 #define ICE_AQ_VSI_INNER_VLAN_EMODE_S 3 338 #define ICE_AQ_VSI_INNER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 339 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH 0x0U 340 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_UP 0x1U 341 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR 0x2U 342 #define ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING 0x3U 343 u8 inner_vlan_reserved2[3]; 344 /* ingress egress up sections */ 345 __le32 ingress_table; /* bitmap, 3 bits per up */ 346 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0 347 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) 348 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3 349 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) 350 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6 351 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) 352 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9 353 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) 354 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12 355 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) 356 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15 357 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) 358 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18 359 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) 360 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21 361 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) 362 __le32 egress_table; /* same defines as for ingress table */ 363 /* outer tags section */ 364 __le16 port_based_outer_vlan; 365 u8 outer_vlan_flags; 366 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_S 0 367 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_EMODE_S) 368 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH 0x0 369 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_UP 0x1 370 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW 0x2 371 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING 0x3 372 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 373 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) 374 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 375 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 376 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 377 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 378 #define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT BIT(4) 379 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S 5 380 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) 381 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1 382 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTTAGGED 0x2 383 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL 0x3 384 #define ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC BIT(7) 385 u8 outer_vlan_reserved; 386 /* queue mapping section */ 387 __le16 mapping_flags; 388 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 389 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) 390 __le16 q_mapping[16]; 391 #define ICE_AQ_VSI_Q_S 0 392 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) 393 __le16 tc_mapping[8]; 394 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0 395 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) 396 #define ICE_AQ_VSI_TC_Q_NUM_S 11 397 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) 398 /* queueing option section */ 399 u8 q_opt_rss; 400 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 401 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) 402 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 403 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 404 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 405 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 406 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) 407 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 408 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M GENMASK(7, 6) 409 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_TPLZ 0x0U 410 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_SYM_TPLZ 0x1U 411 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_XOR 0x2U 412 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_JHASH 0x3U 413 u8 q_opt_tc; 414 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 415 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) 416 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) 417 u8 q_opt_flags; 418 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) 419 u8 q_opt_reserved[3]; 420 /* outer up section */ 421 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 422 /* section 10 */ 423 __le16 sect_10_reserved; 424 /* flow director section */ 425 __le16 fd_options; 426 #define ICE_AQ_VSI_FD_ENABLE BIT(0) 427 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) 428 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) 429 __le16 max_fd_fltr_dedicated; 430 __le16 max_fd_fltr_shared; 431 __le16 fd_def_q; 432 #define ICE_AQ_VSI_FD_DEF_Q_S 0 433 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) 434 #define ICE_AQ_VSI_FD_DEF_GRP_S 12 435 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) 436 __le16 fd_report_opt; 437 #define ICE_AQ_VSI_FD_REPORT_Q_S 0 438 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) 439 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 440 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) 441 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15) 442 /* PASID section */ 443 __le32 pasid_id; 444 #define ICE_AQ_VSI_PASID_ID_S 0 445 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) 446 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31) 447 u8 reserved[24]; 448 }; 449 450 #define ICE_MAX_NUM_RECIPES 64 451 452 /* Add/Get Recipe (indirect 0x0290/0x0292) */ 453 struct ice_aqc_add_get_recipe { 454 __le16 num_sub_recipes; /* Input in Add cmd, Output in Get cmd */ 455 __le16 return_index; /* Input, used for Get cmd only */ 456 u8 reserved[4]; 457 __le32 addr_high; 458 __le32 addr_low; 459 }; 460 461 struct ice_aqc_recipe_content { 462 u8 rid; 463 #define ICE_AQ_RECIPE_ID_S 0 464 #define ICE_AQ_RECIPE_ID_M (0x3F << ICE_AQ_RECIPE_ID_S) 465 #define ICE_AQ_RECIPE_ID_IS_ROOT BIT(7) 466 #define ICE_AQ_SW_ID_LKUP_IDX 0 467 u8 lkup_indx[5]; 468 #define ICE_AQ_RECIPE_LKUP_DATA_S 0 469 #define ICE_AQ_RECIPE_LKUP_DATA_M (0x3F << ICE_AQ_RECIPE_LKUP_DATA_S) 470 #define ICE_AQ_RECIPE_LKUP_IGNORE BIT(7) 471 #define ICE_AQ_SW_ID_LKUP_MASK 0x00FF 472 __le16 mask[5]; 473 u8 result_indx; 474 #define ICE_AQ_RECIPE_RESULT_DATA_S 0 475 #define ICE_AQ_RECIPE_RESULT_DATA_M (0x3F << ICE_AQ_RECIPE_RESULT_DATA_S) 476 #define ICE_AQ_RECIPE_RESULT_EN BIT(7) 477 u8 rsvd0[3]; 478 u8 act_ctrl_join_priority; 479 u8 act_ctrl_fwd_priority; 480 #define ICE_AQ_RECIPE_FWD_PRIORITY_S 0 481 #define ICE_AQ_RECIPE_FWD_PRIORITY_M (0xF << ICE_AQ_RECIPE_FWD_PRIORITY_S) 482 u8 act_ctrl; 483 #define ICE_AQ_RECIPE_ACT_NEED_PASS_L2 BIT(0) 484 #define ICE_AQ_RECIPE_ACT_ALLOW_PASS_L2 BIT(1) 485 #define ICE_AQ_RECIPE_ACT_INV_ACT BIT(2) 486 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_S 4 487 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_M (0x3 << ICE_AQ_RECIPE_ACT_PRUNE_INDX_S) 488 u8 rsvd1; 489 __le32 dflt_act; 490 #define ICE_AQ_RECIPE_DFLT_ACT_S 0 491 #define ICE_AQ_RECIPE_DFLT_ACT_M (0x7FFFF << ICE_AQ_RECIPE_DFLT_ACT_S) 492 #define ICE_AQ_RECIPE_DFLT_ACT_VALID BIT(31) 493 }; 494 495 struct ice_aqc_recipe_data_elem { 496 u8 recipe_indx; 497 u8 resp_bits; 498 #define ICE_AQ_RECIPE_WAS_UPDATED BIT(0) 499 u8 rsvd0[2]; 500 u8 recipe_bitmap[8]; 501 u8 rsvd1[4]; 502 struct ice_aqc_recipe_content content; 503 u8 rsvd2[20]; 504 }; 505 506 /* Set/Get Recipes to Profile Association (direct 0x0291/0x0293) */ 507 struct ice_aqc_recipe_to_profile { 508 __le16 profile_id; 509 u8 rsvd[6]; 510 __le64 recipe_assoc; 511 }; 512 static_assert(sizeof(struct ice_aqc_recipe_to_profile) == 16); 513 514 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3) 515 */ 516 struct ice_aqc_sw_rules { 517 /* ops: add switch rules, referring the number of rules. 518 * ops: update switch rules, referring the number of filters 519 * ops: remove switch rules, referring the entry index. 520 * ops: get switch rules, referring to the number of filters. 521 */ 522 __le16 num_rules_fltr_entry_index; 523 u8 reserved[6]; 524 __le32 addr_high; 525 __le32 addr_low; 526 }; 527 528 /* Add switch rule response: 529 * Content of return buffer is same as the input buffer. The status field and 530 * LUT index are updated as part of the response 531 */ 532 struct ice_aqc_sw_rules_elem_hdr { 533 __le16 type; /* Switch rule type, one of T_... */ 534 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0 535 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1 536 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2 537 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3 538 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4 539 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5 540 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6 541 __le16 status; 542 } __packed __aligned(sizeof(__le16)); 543 544 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry 545 * This structures describes the lookup rules and associated actions. "index" 546 * is returned as part of a response to a successful Add command, and can be 547 * used to identify the rule for Update/Get/Remove commands. 548 */ 549 struct ice_sw_rule_lkup_rx_tx { 550 struct ice_aqc_sw_rules_elem_hdr hdr; 551 552 __le16 recipe_id; 553 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10 554 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */ 555 __le16 src; 556 __le32 act; 557 558 /* Bit 0:1 - Action type */ 559 #define ICE_SINGLE_ACT_TYPE_S 0x00 560 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S) 561 562 /* Bit 2 - Loop back enable 563 * Bit 3 - LAN enable 564 */ 565 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2) 566 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3) 567 568 /* Action type = 0 - Forward to VSI or VSI list */ 569 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0 570 571 #define ICE_SINGLE_ACT_VSI_ID_S 4 572 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S) 573 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4 574 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S) 575 /* This bit needs to be set if action is forward to VSI list */ 576 #define ICE_SINGLE_ACT_VSI_LIST BIT(14) 577 #define ICE_SINGLE_ACT_VALID_BIT BIT(17) 578 #define ICE_SINGLE_ACT_DROP BIT(18) 579 580 /* Action type = 1 - Forward to Queue of Queue group */ 581 #define ICE_SINGLE_ACT_TO_Q 0x1 582 #define ICE_SINGLE_ACT_Q_INDEX_S 4 583 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S) 584 #define ICE_SINGLE_ACT_Q_REGION_S 15 585 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S) 586 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18) 587 588 /* Action type = 2 - Prune */ 589 #define ICE_SINGLE_ACT_PRUNE 0x2 590 #define ICE_SINGLE_ACT_EGRESS BIT(15) 591 #define ICE_SINGLE_ACT_INGRESS BIT(16) 592 #define ICE_SINGLE_ACT_PRUNET BIT(17) 593 /* Bit 18 should be set to 0 for this action */ 594 595 /* Action type = 2 - Pointer */ 596 #define ICE_SINGLE_ACT_PTR 0x2 597 #define ICE_SINGLE_ACT_PTR_VAL_S 4 598 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S) 599 /* Bit 18 should be set to 1 */ 600 #define ICE_SINGLE_ACT_PTR_BIT BIT(18) 601 602 /* Action type = 3 - Other actions. Last two bits 603 * are other action identifier 604 */ 605 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3 606 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17 607 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \ 608 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S) 609 610 /* Bit 17:18 - Defines other actions */ 611 /* Other action = 0 - Mirror VSI */ 612 #define ICE_SINGLE_OTHER_ACT_MIRROR 0 613 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4 614 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \ 615 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S) 616 617 /* Other action = 3 - Set Stat count */ 618 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3 619 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4 620 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \ 621 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S) 622 623 __le16 index; /* The index of the rule in the lookup table */ 624 /* Length and values of the header to be matched per recipe or 625 * lookup-type 626 */ 627 __le16 hdr_len; 628 u8 hdr_data[]; 629 } __packed __aligned(sizeof(__le16)); 630 631 /* Add/Update/Remove large action command/response entry 632 * "index" is returned as part of a response to a successful Add command, and 633 * can be used to identify the action for Update/Get/Remove commands. 634 */ 635 struct ice_sw_rule_lg_act { 636 struct ice_aqc_sw_rules_elem_hdr hdr; 637 638 __le16 index; /* Index in large action table */ 639 __le16 size; 640 /* Max number of large actions */ 641 #define ICE_MAX_LG_ACT 4 642 /* Bit 0:1 - Action type */ 643 #define ICE_LG_ACT_TYPE_S 0 644 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S) 645 646 /* Action type = 0 - Forward to VSI or VSI list */ 647 #define ICE_LG_ACT_VSI_FORWARDING 0 648 #define ICE_LG_ACT_VSI_ID_S 3 649 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S) 650 #define ICE_LG_ACT_VSI_LIST_ID_S 3 651 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S) 652 /* This bit needs to be set if action is forward to VSI list */ 653 #define ICE_LG_ACT_VSI_LIST BIT(13) 654 655 #define ICE_LG_ACT_VALID_BIT BIT(16) 656 657 /* Action type = 1 - Forward to Queue of Queue group */ 658 #define ICE_LG_ACT_TO_Q 0x1 659 #define ICE_LG_ACT_Q_INDEX_S 3 660 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S) 661 #define ICE_LG_ACT_Q_REGION_S 14 662 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S) 663 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17) 664 665 /* Action type = 2 - Prune */ 666 #define ICE_LG_ACT_PRUNE 0x2 667 #define ICE_LG_ACT_EGRESS BIT(14) 668 #define ICE_LG_ACT_INGRESS BIT(15) 669 #define ICE_LG_ACT_PRUNET BIT(16) 670 671 /* Action type = 3 - Mirror VSI */ 672 #define ICE_LG_OTHER_ACT_MIRROR 0x3 673 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3 674 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S) 675 676 /* Action type = 5 - Generic Value */ 677 #define ICE_LG_ACT_GENERIC 0x5 678 #define ICE_LG_ACT_GENERIC_VALUE_S 3 679 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S) 680 #define ICE_LG_ACT_GENERIC_OFFSET_S 19 681 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S) 682 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22 683 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S) 684 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7 685 686 /* Action = 7 - Set Stat count */ 687 #define ICE_LG_ACT_STAT_COUNT 0x7 688 #define ICE_LG_ACT_STAT_COUNT_S 3 689 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S) 690 __le32 act[]; /* array of size for actions */ 691 } __packed __aligned(sizeof(__le16)); 692 693 /* Add/Update/Remove VSI list command/response entry 694 * "index" is returned as part of a response to a successful Add command, and 695 * can be used to identify the VSI list for Update/Get/Remove commands. 696 */ 697 struct ice_sw_rule_vsi_list { 698 struct ice_aqc_sw_rules_elem_hdr hdr; 699 700 __le16 index; /* Index of VSI/Prune list */ 701 __le16 number_vsi; 702 __le16 vsi[]; /* Array of number_vsi VSI numbers */ 703 } __packed __aligned(sizeof(__le16)); 704 705 /* Query PFC Mode (direct 0x0302) 706 * Set PFC Mode (direct 0x0303) 707 */ 708 struct ice_aqc_set_query_pfc_mode { 709 u8 pfc_mode; 710 /* For Query Command response, reserved in all other cases */ 711 #define ICE_AQC_PFC_VLAN_BASED_PFC 1 712 #define ICE_AQC_PFC_DSCP_BASED_PFC 2 713 u8 rsvd[15]; 714 }; 715 /* Get Default Topology (indirect 0x0400) */ 716 struct ice_aqc_get_topo { 717 u8 port_num; 718 u8 num_branches; 719 __le16 reserved1; 720 __le32 reserved2; 721 __le32 addr_high; 722 __le32 addr_low; 723 }; 724 725 /* Get/Set Tx Topology (indirect 0x0418/0x0417) */ 726 struct ice_aqc_get_set_tx_topo { 727 u8 set_flags; 728 #define ICE_AQC_TX_TOPO_FLAGS_CORRER BIT(0) 729 #define ICE_AQC_TX_TOPO_FLAGS_SRC_RAM BIT(1) 730 #define ICE_AQC_TX_TOPO_FLAGS_LOAD_NEW BIT(4) 731 #define ICE_AQC_TX_TOPO_FLAGS_ISSUED BIT(5) 732 733 u8 get_flags; 734 #define ICE_AQC_TX_TOPO_GET_RAM 2 735 736 __le16 reserved1; 737 __le32 reserved2; 738 __le32 addr_high; 739 __le32 addr_low; 740 }; 741 742 /* Update TSE (indirect 0x0403) 743 * Get TSE (indirect 0x0404) 744 * Add TSE (indirect 0x0401) 745 * Delete TSE (indirect 0x040F) 746 * Move TSE (indirect 0x0408) 747 * Suspend Nodes (indirect 0x0409) 748 * Resume Nodes (indirect 0x040A) 749 */ 750 struct ice_aqc_sched_elem_cmd { 751 __le16 num_elem_req; /* Used by commands */ 752 __le16 num_elem_resp; /* Used by responses */ 753 __le32 reserved; 754 __le32 addr_high; 755 __le32 addr_low; 756 }; 757 758 struct ice_aqc_txsched_move_grp_info_hdr { 759 __le32 src_parent_teid; 760 __le32 dest_parent_teid; 761 __le16 num_elems; 762 u8 mode; 763 #define ICE_AQC_MOVE_ELEM_MODE_SAME_PF 0x0 764 #define ICE_AQC_MOVE_ELEM_MODE_GIVE_OWN 0x1 765 #define ICE_AQC_MOVE_ELEM_MODE_KEEP_OWN 0x2 766 u8 reserved; 767 }; 768 769 struct ice_aqc_move_elem { 770 struct ice_aqc_txsched_move_grp_info_hdr hdr; 771 __le32 teid[]; 772 }; 773 774 struct ice_aqc_elem_info_bw { 775 __le16 bw_profile_idx; 776 __le16 bw_alloc; 777 }; 778 779 struct ice_aqc_txsched_elem { 780 u8 elem_type; /* Special field, reserved for some aq calls */ 781 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0 782 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1 783 #define ICE_AQC_ELEM_TYPE_TC 0x2 784 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3 785 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4 786 #define ICE_AQC_ELEM_TYPE_LEAF 0x5 787 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6 788 u8 valid_sections; 789 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0) 790 #define ICE_AQC_ELEM_VALID_CIR BIT(1) 791 #define ICE_AQC_ELEM_VALID_EIR BIT(2) 792 #define ICE_AQC_ELEM_VALID_SHARED BIT(3) 793 u8 generic; 794 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1 795 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1 796 #define ICE_AQC_ELEM_GENERIC_PRIO_M GENMASK(3, 1) 797 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4 798 #define ICE_AQC_ELEM_GENERIC_SP_M GENMASK(4, 4) 799 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5 800 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \ 801 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S) 802 u8 flags; /* Special field, reserved for some aq calls */ 803 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1 804 struct ice_aqc_elem_info_bw cir_bw; 805 struct ice_aqc_elem_info_bw eir_bw; 806 __le16 srl_id; 807 __le16 reserved2; 808 }; 809 810 struct ice_aqc_txsched_elem_data { 811 __le32 parent_teid; 812 __le32 node_teid; 813 struct ice_aqc_txsched_elem data; 814 }; 815 816 struct ice_aqc_txsched_topo_grp_info_hdr { 817 __le32 parent_teid; 818 __le16 num_elems; 819 __le16 reserved2; 820 }; 821 822 struct ice_aqc_add_elem { 823 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 824 struct ice_aqc_txsched_elem_data generic[]; 825 }; 826 827 struct ice_aqc_get_topo_elem { 828 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 829 struct ice_aqc_txsched_elem_data 830 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 831 }; 832 833 struct ice_aqc_delete_elem { 834 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 835 __le32 teid[]; 836 }; 837 838 /* Query Port ETS (indirect 0x040E) 839 * 840 * This indirect command is used to query port TC node configuration. 841 */ 842 struct ice_aqc_query_port_ets { 843 __le32 port_teid; 844 __le32 reserved; 845 __le32 addr_high; 846 __le32 addr_low; 847 }; 848 849 struct ice_aqc_port_ets_elem { 850 u8 tc_valid_bits; 851 u8 reserved[3]; 852 /* 3 bits for UP per TC 0-7, 4th byte reserved */ 853 __le32 up2tc; 854 u8 tc_bw_share[8]; 855 __le32 port_eir_prof_id; 856 __le32 port_cir_prof_id; 857 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */ 858 __le32 tc_node_prio; 859 #define ICE_TC_NODE_PRIO_S 0x4 860 u8 reserved1[4]; 861 __le32 tc_node_teid[8]; /* Used for response, reserved in command */ 862 }; 863 864 /* Rate limiting profile for 865 * Add RL profile (indirect 0x0410) 866 * Query RL profile (indirect 0x0411) 867 * Remove RL profile (indirect 0x0415) 868 * These indirect commands acts on single or multiple 869 * RL profiles with specified data. 870 */ 871 struct ice_aqc_rl_profile { 872 __le16 num_profiles; 873 __le16 num_processed; /* Only for response. Reserved in Command. */ 874 u8 reserved[4]; 875 __le32 addr_high; 876 __le32 addr_low; 877 }; 878 879 struct ice_aqc_rl_profile_elem { 880 u8 level; 881 u8 flags; 882 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0 883 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S) 884 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0 885 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1 886 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2 887 /* The following flag is used for Query RL Profile Data */ 888 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7 889 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S) 890 891 __le16 profile_id; 892 __le16 max_burst_size; 893 __le16 rl_multiply; 894 __le16 wake_up_calc; 895 __le16 rl_encode; 896 }; 897 898 /* Query Scheduler Resource Allocation (indirect 0x0412) 899 * This indirect command retrieves the scheduler resources allocated by 900 * EMP Firmware to the given PF. 901 */ 902 struct ice_aqc_query_txsched_res { 903 u8 reserved[8]; 904 __le32 addr_high; 905 __le32 addr_low; 906 }; 907 908 struct ice_aqc_generic_sched_props { 909 __le16 phys_levels; 910 __le16 logical_levels; 911 u8 flattening_bitmap; 912 u8 max_device_cgds; 913 u8 max_pf_cgds; 914 u8 rsvd0; 915 __le16 rdma_qsets; 916 u8 rsvd1[22]; 917 }; 918 919 struct ice_aqc_layer_props { 920 u8 logical_layer; 921 u8 chunk_size; 922 __le16 max_device_nodes; 923 __le16 max_pf_nodes; 924 u8 rsvd0[4]; 925 __le16 max_sibl_grp_sz; 926 __le16 max_cir_rl_profiles; 927 __le16 max_eir_rl_profiles; 928 __le16 max_srl_profiles; 929 u8 rsvd1[14]; 930 }; 931 932 struct ice_aqc_query_txsched_res_resp { 933 struct ice_aqc_generic_sched_props sched_props; 934 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 935 }; 936 937 /* Get PHY capabilities (indirect 0x0600) */ 938 struct ice_aqc_get_phy_caps { 939 u8 lport_num; 940 u8 reserved; 941 __le16 param0; 942 /* 18.0 - Report qualified modules */ 943 #define ICE_AQC_GET_PHY_RQM BIT(0) 944 /* 18.1 - 18.3 : Report mode 945 * 000b - Report NVM capabilities 946 * 001b - Report topology capabilities 947 * 010b - Report SW configured 948 * 100b - Report default capabilities 949 */ 950 #define ICE_AQC_REPORT_MODE_S 1 951 #define ICE_AQC_REPORT_MODE_M (7 << ICE_AQC_REPORT_MODE_S) 952 #define ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA 0 953 #define ICE_AQC_REPORT_TOPO_CAP_MEDIA BIT(1) 954 #define ICE_AQC_REPORT_ACTIVE_CFG BIT(2) 955 #define ICE_AQC_REPORT_DFLT_CFG BIT(3) 956 __le32 reserved1; 957 __le32 addr_high; 958 __le32 addr_low; 959 }; 960 961 /* This is #define of PHY type (Extended): 962 * The first set of defines is for phy_type_low. 963 */ 964 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0) 965 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1) 966 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2) 967 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3) 968 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4) 969 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5) 970 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6) 971 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7) 972 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8) 973 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9) 974 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10) 975 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11) 976 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12) 977 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13) 978 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14) 979 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15) 980 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16) 981 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17) 982 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18) 983 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19) 984 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20) 985 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21) 986 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22) 987 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23) 988 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24) 989 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25) 990 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26) 991 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27) 992 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28) 993 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29) 994 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30) 995 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31) 996 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32) 997 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33) 998 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34) 999 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35) 1000 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36) 1001 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37) 1002 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38) 1003 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39) 1004 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40) 1005 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41) 1006 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42) 1007 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43) 1008 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44) 1009 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45) 1010 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46) 1011 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47) 1012 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48) 1013 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49) 1014 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50) 1015 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51) 1016 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52) 1017 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53) 1018 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54) 1019 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55) 1020 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56) 1021 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57) 1022 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58) 1023 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59) 1024 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60) 1025 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61) 1026 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62) 1027 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63) 1028 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63 1029 /* The second set of defines is for phy_type_high. */ 1030 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0) 1031 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1) 1032 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2) 1033 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3) 1034 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4) 1035 #define ICE_PHY_TYPE_HIGH_200G_CR4_PAM4 BIT_ULL(5) 1036 #define ICE_PHY_TYPE_HIGH_200G_SR4 BIT_ULL(6) 1037 #define ICE_PHY_TYPE_HIGH_200G_FR4 BIT_ULL(7) 1038 #define ICE_PHY_TYPE_HIGH_200G_LR4 BIT_ULL(8) 1039 #define ICE_PHY_TYPE_HIGH_200G_DR4 BIT_ULL(9) 1040 #define ICE_PHY_TYPE_HIGH_200G_KR4_PAM4 BIT_ULL(10) 1041 #define ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC BIT_ULL(11) 1042 #define ICE_PHY_TYPE_HIGH_200G_AUI4 BIT_ULL(12) 1043 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 12 1044 1045 struct ice_aqc_get_phy_caps_data { 1046 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1047 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1048 u8 caps; 1049 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0) 1050 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1) 1051 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2) 1052 #define ICE_AQC_PHY_EN_LINK BIT(3) 1053 #define ICE_AQC_PHY_AN_MODE BIT(4) 1054 #define ICE_AQC_GET_PHY_EN_MOD_QUAL BIT(5) 1055 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7) 1056 #define ICE_AQC_PHY_CAPS_MASK ICE_M(0xff, 0) 1057 u8 low_power_ctrl_an; 1058 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) 1059 #define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1) 1060 #define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2) 1061 #define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3) 1062 __le16 eee_cap; 1063 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0) 1064 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1) 1065 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2) 1066 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3) 1067 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4) 1068 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5) 1069 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6) 1070 __le16 eeer_value; 1071 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ 1072 u8 phy_fw_ver[8]; 1073 u8 link_fec_options; 1074 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) 1075 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) 1076 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2) 1077 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3) 1078 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4) 1079 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) 1080 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) 1081 #define ICE_AQC_PHY_FEC_MASK ICE_M(0xdf, 0) 1082 u8 module_compliance_enforcement; 1083 #define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0) 1084 u8 extended_compliance_code; 1085 #define ICE_MODULE_TYPE_TOTAL_BYTE 3 1086 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 1087 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0 1088 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80 1089 #define ICE_AQC_MOD_TYPE_IDENT 1 1090 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) 1091 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) 1092 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) 1093 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) 1094 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) 1095 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) 1096 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 1097 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 1098 u8 qualified_module_count; 1099 u8 rsvd2[7]; /* Bytes 47:41 reserved */ 1100 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16 1101 struct { 1102 u8 v_oui[3]; 1103 u8 rsvd3; 1104 u8 v_part[16]; 1105 __le32 v_rev; 1106 __le64 rsvd4; 1107 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX]; 1108 }; 1109 1110 /* Set PHY capabilities (direct 0x0601) 1111 * NOTE: This command must be followed by setup link and restart auto-neg 1112 */ 1113 struct ice_aqc_set_phy_cfg { 1114 u8 lport_num; 1115 u8 reserved[7]; 1116 __le32 addr_high; 1117 __le32 addr_low; 1118 }; 1119 1120 /* Set PHY config command data structure */ 1121 struct ice_aqc_set_phy_cfg_data { 1122 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1123 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1124 u8 caps; 1125 #define ICE_AQ_PHY_ENA_VALID_MASK ICE_M(0xef, 0) 1126 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0) 1127 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1) 1128 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2) 1129 #define ICE_AQ_PHY_ENA_LINK BIT(3) 1130 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5) 1131 #define ICE_AQ_PHY_ENA_LESM BIT(6) 1132 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7) 1133 u8 low_power_ctrl_an; 1134 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */ 1135 __le16 eeer_value; 1136 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */ 1137 u8 module_compliance_enforcement; 1138 }; 1139 1140 /* Set MAC Config command data structure (direct 0x0603) */ 1141 struct ice_aqc_set_mac_cfg { 1142 __le16 max_frame_size; 1143 u8 params; 1144 #define ICE_AQ_SET_MAC_PACE_S 3 1145 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S) 1146 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7) 1147 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0 1148 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M 1149 u8 tx_tmr_priority; 1150 __le16 tx_tmr_value; 1151 __le16 fc_refresh_threshold; 1152 u8 drop_opts; 1153 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0) 1154 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0 1155 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0) 1156 u8 reserved[7]; 1157 }; 1158 1159 /* Restart AN command data structure (direct 0x0605) 1160 * Also used for response, with only the lport_num field present. 1161 */ 1162 struct ice_aqc_restart_an { 1163 u8 lport_num; 1164 u8 reserved; 1165 u8 cmd_flags; 1166 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1) 1167 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2) 1168 u8 reserved2[13]; 1169 }; 1170 1171 /* Get link status (indirect 0x0607), also used for Link Status Event */ 1172 struct ice_aqc_get_link_status { 1173 u8 lport_num; 1174 u8 reserved; 1175 __le16 cmd_flags; 1176 #define ICE_AQ_LSE_M 0x3 1177 #define ICE_AQ_LSE_NOP 0x0 1178 #define ICE_AQ_LSE_DIS 0x2 1179 #define ICE_AQ_LSE_ENA 0x3 1180 /* only response uses this flag */ 1181 #define ICE_AQ_LSE_IS_ENABLED 0x1 1182 __le32 reserved2; 1183 __le32 addr_high; 1184 __le32 addr_low; 1185 }; 1186 1187 /* Get link status response data structure, also used for Link Status Event */ 1188 struct ice_aqc_get_link_status_data { 1189 u8 topo_media_conflict; 1190 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) 1191 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1) 1192 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2) 1193 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4) 1194 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5) 1195 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6) 1196 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7) 1197 u8 link_cfg_err; 1198 #define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED BIT(5) 1199 #define ICE_AQ_LINK_EXTERNAL_PHY_LOAD_FAILURE BIT(6) 1200 #define ICE_AQ_LINK_INVAL_MAX_POWER_LIMIT BIT(7) 1201 u8 link_info; 1202 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */ 1203 #define ICE_AQ_LINK_FAULT BIT(1) 1204 #define ICE_AQ_LINK_FAULT_TX BIT(2) 1205 #define ICE_AQ_LINK_FAULT_RX BIT(3) 1206 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4) 1207 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */ 1208 #define ICE_AQ_MEDIA_AVAILABLE BIT(6) 1209 #define ICE_AQ_SIGNAL_DETECT BIT(7) 1210 u8 an_info; 1211 #define ICE_AQ_AN_COMPLETED BIT(0) 1212 #define ICE_AQ_LP_AN_ABILITY BIT(1) 1213 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */ 1214 #define ICE_AQ_FEC_EN BIT(3) 1215 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */ 1216 #define ICE_AQ_LINK_PAUSE_TX BIT(5) 1217 #define ICE_AQ_LINK_PAUSE_RX BIT(6) 1218 #define ICE_AQ_QUALIFIED_MODULE BIT(7) 1219 u8 ext_info; 1220 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0) 1221 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ 1222 /* Port Tx Suspended */ 1223 #define ICE_AQ_LINK_TX_S 2 1224 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S) 1225 #define ICE_AQ_LINK_TX_ACTIVE 0 1226 #define ICE_AQ_LINK_TX_DRAINED 1 1227 #define ICE_AQ_LINK_TX_FLUSHED 3 1228 u8 reserved2; 1229 __le16 max_frame_size; 1230 u8 cfg; 1231 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0) 1232 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1) 1233 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2) 1234 #define ICE_AQ_FEC_MASK ICE_M(0x7, 0) 1235 /* Pacing Config */ 1236 #define ICE_AQ_CFG_PACING_S 3 1237 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S) 1238 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7) 1239 #define ICE_AQ_CFG_PACING_TYPE_AVG 0 1240 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M 1241 /* External Device Power Ability */ 1242 u8 power_desc; 1243 #define ICE_AQ_PWR_CLASS_M 0x3F 1244 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0 1245 #define ICE_AQ_LINK_PWR_BASET_HIGH 1 1246 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0 1247 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1 1248 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2 1249 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3 1250 __le16 link_speed; 1251 #define ICE_AQ_LINK_SPEED_M 0x7FF 1252 #define ICE_AQ_LINK_SPEED_10MB BIT(0) 1253 #define ICE_AQ_LINK_SPEED_100MB BIT(1) 1254 #define ICE_AQ_LINK_SPEED_1000MB BIT(2) 1255 #define ICE_AQ_LINK_SPEED_2500MB BIT(3) 1256 #define ICE_AQ_LINK_SPEED_5GB BIT(4) 1257 #define ICE_AQ_LINK_SPEED_10GB BIT(5) 1258 #define ICE_AQ_LINK_SPEED_20GB BIT(6) 1259 #define ICE_AQ_LINK_SPEED_25GB BIT(7) 1260 #define ICE_AQ_LINK_SPEED_40GB BIT(8) 1261 #define ICE_AQ_LINK_SPEED_50GB BIT(9) 1262 #define ICE_AQ_LINK_SPEED_100GB BIT(10) 1263 #define ICE_AQ_LINK_SPEED_200GB BIT(11) 1264 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15) 1265 /* Aligns next field to 8-byte boundary */ 1266 __le16 reserved3; 1267 u8 ext_fec_status; 1268 /* RS 272 FEC enabled */ 1269 #define ICE_AQ_LINK_RS_272_FEC_EN BIT(0) 1270 u8 reserved4; 1271 /* Use values from ICE_PHY_TYPE_LOW_* */ 1272 __le64 phy_type_low; 1273 /* Use values from ICE_PHY_TYPE_HIGH_* */ 1274 __le64 phy_type_high; 1275 #define ICE_AQC_LS_DATA_SIZE_V1 \ 1276 offsetofend(struct ice_aqc_get_link_status_data, phy_type_high) 1277 /* Get link status v2 link partner data */ 1278 __le64 lp_phy_type_low; 1279 __le64 lp_phy_type_high; 1280 u8 lp_fec_adv; 1281 #define ICE_AQ_LINK_LP_10G_KR_FEC_CAP BIT(0) 1282 #define ICE_AQ_LINK_LP_25G_KR_FEC_CAP BIT(1) 1283 #define ICE_AQ_LINK_LP_RS_528_FEC_CAP BIT(2) 1284 #define ICE_AQ_LINK_LP_50G_KR_272_FEC_CAP BIT(3) 1285 #define ICE_AQ_LINK_LP_100G_KR_272_FEC_CAP BIT(4) 1286 #define ICE_AQ_LINK_LP_200G_KR_272_FEC_CAP BIT(5) 1287 u8 lp_fec_req; 1288 #define ICE_AQ_LINK_LP_10G_KR_FEC_REQ BIT(0) 1289 #define ICE_AQ_LINK_LP_25G_KR_FEC_REQ BIT(1) 1290 #define ICE_AQ_LINK_LP_RS_528_FEC_REQ BIT(2) 1291 #define ICE_AQ_LINK_LP_KR_272_FEC_REQ BIT(3) 1292 u8 lp_flowcontrol; 1293 #define ICE_AQ_LINK_LP_PAUSE_ADV BIT(0) 1294 #define ICE_AQ_LINK_LP_ASM_DIR_ADV BIT(1) 1295 u8 reserved5[5]; 1296 #define ICE_AQC_LS_DATA_SIZE_V2 \ 1297 offsetofend(struct ice_aqc_get_link_status_data, reserved5) 1298 } __packed; 1299 1300 /* Set event mask command (direct 0x0613) */ 1301 struct ice_aqc_set_event_mask { 1302 u8 lport_num; 1303 u8 reserved[7]; 1304 __le16 event_mask; 1305 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1) 1306 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2) 1307 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3) 1308 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4) 1309 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5) 1310 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6) 1311 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7) 1312 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) 1313 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) 1314 #define ICE_AQ_LINK_EVENT_PHY_FW_LOAD_FAIL BIT(12) 1315 u8 reserved1[6]; 1316 }; 1317 1318 /* Set MAC Loopback command (direct 0x0620) */ 1319 struct ice_aqc_set_mac_lb { 1320 u8 lb_mode; 1321 #define ICE_AQ_MAC_LB_EN BIT(0) 1322 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1) 1323 u8 reserved[15]; 1324 }; 1325 1326 /* Set PHY recovered clock output (direct 0x0630) */ 1327 struct ice_aqc_set_phy_rec_clk_out { 1328 u8 phy_output; 1329 u8 port_num; 1330 #define ICE_AQC_SET_PHY_REC_CLK_OUT_CURR_PORT 0xFF 1331 u8 flags; 1332 #define ICE_AQC_SET_PHY_REC_CLK_OUT_OUT_EN BIT(0) 1333 u8 rsvd; 1334 __le32 freq; 1335 u8 rsvd2[6]; 1336 __le16 node_handle; 1337 }; 1338 1339 /* Get PHY recovered clock output (direct 0x0631) */ 1340 struct ice_aqc_get_phy_rec_clk_out { 1341 u8 phy_output; 1342 u8 port_num; 1343 #define ICE_AQC_GET_PHY_REC_CLK_OUT_CURR_PORT 0xFF 1344 u8 flags; 1345 #define ICE_AQC_GET_PHY_REC_CLK_OUT_OUT_EN BIT(0) 1346 u8 rsvd[11]; 1347 __le16 node_handle; 1348 }; 1349 1350 /* Get sensor reading (direct 0x0632) */ 1351 struct ice_aqc_get_sensor_reading { 1352 u8 sensor; 1353 u8 format; 1354 u8 reserved[6]; 1355 __le32 addr_high; 1356 __le32 addr_low; 1357 }; 1358 1359 /* Get sensor reading response (direct 0x0632) */ 1360 struct ice_aqc_get_sensor_reading_resp { 1361 union { 1362 u8 raw[8]; 1363 /* Output data for sensor 0x00, format 0x00 */ 1364 struct _packed { 1365 s8 temp; 1366 u8 temp_warning_threshold; 1367 u8 temp_critical_threshold; 1368 u8 temp_fatal_threshold; 1369 u8 reserved[4]; 1370 } s0f0; 1371 } data; 1372 }; 1373 1374 /* DNL call command (indirect 0x0682) 1375 * Struct is used for both command and response 1376 */ 1377 struct ice_aqc_dnl_call_command { 1378 u8 ctx; /* Used in command, reserved in response */ 1379 u8 reserved; 1380 __le16 activity_id; 1381 #define ICE_AQC_ACT_ID_DNL 0x1129 1382 __le32 reserved1; 1383 __le32 addr_high; 1384 __le32 addr_low; 1385 }; 1386 1387 struct ice_aqc_dnl_equa_param { 1388 __le16 data_in; 1389 #define ICE_AQC_RX_EQU_SHIFT 8 1390 #define ICE_AQC_RX_EQU_PRE2 (0x10 << ICE_AQC_RX_EQU_SHIFT) 1391 #define ICE_AQC_RX_EQU_PRE1 (0x11 << ICE_AQC_RX_EQU_SHIFT) 1392 #define ICE_AQC_RX_EQU_POST1 (0x12 << ICE_AQC_RX_EQU_SHIFT) 1393 #define ICE_AQC_RX_EQU_BFLF (0x13 << ICE_AQC_RX_EQU_SHIFT) 1394 #define ICE_AQC_RX_EQU_BFHF (0x14 << ICE_AQC_RX_EQU_SHIFT) 1395 #define ICE_AQC_RX_EQU_CTLE_GAINHF (0x20 << ICE_AQC_RX_EQU_SHIFT) 1396 #define ICE_AQC_RX_EQU_CTLE_GAINLF (0x21 << ICE_AQC_RX_EQU_SHIFT) 1397 #define ICE_AQC_RX_EQU_CTLE_GAINDC (0x22 << ICE_AQC_RX_EQU_SHIFT) 1398 #define ICE_AQC_RX_EQU_CTLE_BW (0x23 << ICE_AQC_RX_EQU_SHIFT) 1399 #define ICE_AQC_RX_EQU_DFE_GAIN (0x30 << ICE_AQC_RX_EQU_SHIFT) 1400 #define ICE_AQC_RX_EQU_DFE_GAIN2 (0x31 << ICE_AQC_RX_EQU_SHIFT) 1401 #define ICE_AQC_RX_EQU_DFE_2 (0x32 << ICE_AQC_RX_EQU_SHIFT) 1402 #define ICE_AQC_RX_EQU_DFE_3 (0x33 << ICE_AQC_RX_EQU_SHIFT) 1403 #define ICE_AQC_RX_EQU_DFE_4 (0x34 << ICE_AQC_RX_EQU_SHIFT) 1404 #define ICE_AQC_RX_EQU_DFE_5 (0x35 << ICE_AQC_RX_EQU_SHIFT) 1405 #define ICE_AQC_RX_EQU_DFE_6 (0x36 << ICE_AQC_RX_EQU_SHIFT) 1406 #define ICE_AQC_RX_EQU_DFE_7 (0x37 << ICE_AQC_RX_EQU_SHIFT) 1407 #define ICE_AQC_RX_EQU_DFE_8 (0x38 << ICE_AQC_RX_EQU_SHIFT) 1408 #define ICE_AQC_RX_EQU_DFE_9 (0x39 << ICE_AQC_RX_EQU_SHIFT) 1409 #define ICE_AQC_RX_EQU_DFE_10 (0x3A << ICE_AQC_RX_EQU_SHIFT) 1410 #define ICE_AQC_RX_EQU_DFE_11 (0x3B << ICE_AQC_RX_EQU_SHIFT) 1411 #define ICE_AQC_RX_EQU_DFE_12 (0x3C << ICE_AQC_RX_EQU_SHIFT) 1412 #define ICE_AQC_TX_EQU_PRE1 0x0 1413 #define ICE_AQC_TX_EQU_PRE3 0x3 1414 #define ICE_AQC_TX_EQU_ATTEN 0x4 1415 #define ICE_AQC_TX_EQU_POST1 0x8 1416 #define ICE_AQC_TX_EQU_PRE2 0xC 1417 __le16 op_code_serdes_sel; 1418 #define ICE_AQC_OP_CODE_SHIFT 4 1419 #define ICE_AQC_OP_CODE_RX_EQU (0x9 << ICE_AQC_OP_CODE_SHIFT) 1420 #define ICE_AQC_OP_CODE_TX_EQU (0x10 << ICE_AQC_OP_CODE_SHIFT) 1421 __le32 reserved[3]; 1422 }; 1423 1424 struct ice_aqc_dnl_equa_respon { 1425 /* Equalization value can be negative */ 1426 int val; 1427 __le32 reserved[3]; 1428 }; 1429 1430 /* DNL call command/response buffer (indirect 0x0682) */ 1431 struct ice_aqc_dnl_call { 1432 union { 1433 struct ice_aqc_dnl_equa_param txrx_equa_reqs; 1434 __le32 stores[4]; 1435 struct ice_aqc_dnl_equa_respon txrx_equa_resp; 1436 } sto; 1437 }; 1438 1439 struct ice_aqc_link_topo_params { 1440 u8 lport_num; 1441 u8 lport_num_valid; 1442 #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0) 1443 u8 node_type_ctx; 1444 #define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0 1445 #define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S) 1446 #define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0 1447 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1 1448 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2 1449 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3 1450 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4 1451 #define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5 1452 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6 1453 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7 1454 #define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8 1455 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL 9 1456 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX 10 1457 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPS 11 1458 #define ICE_AQC_LINK_TOPO_NODE_CTX_S 4 1459 #define ICE_AQC_LINK_TOPO_NODE_CTX_M \ 1460 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S) 1461 #define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0 1462 #define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1 1463 #define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2 1464 #define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3 1465 #define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4 1466 #define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5 1467 u8 index; 1468 }; 1469 1470 struct ice_aqc_link_topo_addr { 1471 struct ice_aqc_link_topo_params topo_params; 1472 __le16 handle; 1473 #define ICE_AQC_LINK_TOPO_HANDLE_S 0 1474 #define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S) 1475 /* Used to decode the handle field */ 1476 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9) 1477 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9) 1478 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0 1479 #define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0 1480 /* In case of a Mezzanine type */ 1481 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \ 1482 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1483 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6 1484 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S) 1485 /* In case of a LOM type */ 1486 #define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \ 1487 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1488 }; 1489 1490 /* Get Link Topology Handle (direct, 0x06E0) */ 1491 struct ice_aqc_get_link_topo { 1492 struct ice_aqc_link_topo_addr addr; 1493 u8 node_part_num; 1494 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575 0x21 1495 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032 0x24 1496 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384 0x25 1497 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_E822_PHY 0x30 1498 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_C827 0x31 1499 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_CLK_MUX 0x47 1500 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_GPS 0x48 1501 u8 rsvd[9]; 1502 }; 1503 1504 /* Read/Write I2C (direct, 0x06E2/0x06E3) */ 1505 struct ice_aqc_i2c { 1506 struct ice_aqc_link_topo_addr topo_addr; 1507 __le16 i2c_addr; 1508 u8 i2c_params; 1509 #define ICE_AQC_I2C_DATA_SIZE_M GENMASK(3, 0) 1510 #define ICE_AQC_I2C_USE_REPEATED_START BIT(7) 1511 1512 u8 rsvd; 1513 __le16 i2c_bus_addr; 1514 u8 i2c_data[4]; /* Used only by write command, reserved in read. */ 1515 }; 1516 1517 /* Read I2C Response (direct, 0x06E2) */ 1518 struct ice_aqc_read_i2c_resp { 1519 u8 i2c_data[16]; 1520 }; 1521 1522 /* Set Port Identification LED (direct, 0x06E9) */ 1523 struct ice_aqc_set_port_id_led { 1524 u8 lport_num; 1525 u8 lport_num_valid; 1526 u8 ident_mode; 1527 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0) 1528 #define ICE_AQC_PORT_IDENT_LED_ORIG 0 1529 u8 rsvd[13]; 1530 }; 1531 1532 /* Get Port Options (indirect, 0x06EA) */ 1533 struct ice_aqc_get_port_options { 1534 u8 lport_num; 1535 u8 lport_num_valid; 1536 u8 port_options_count; 1537 #define ICE_AQC_PORT_OPT_COUNT_M GENMASK(3, 0) 1538 #define ICE_AQC_PORT_OPT_MAX 16 1539 1540 u8 innermost_phy_index; 1541 u8 port_options; 1542 #define ICE_AQC_PORT_OPT_ACTIVE_M GENMASK(3, 0) 1543 #define ICE_AQC_PORT_OPT_VALID BIT(7) 1544 1545 u8 pending_port_option_status; 1546 #define ICE_AQC_PENDING_PORT_OPT_IDX_M GENMASK(3, 0) 1547 #define ICE_AQC_PENDING_PORT_OPT_VALID BIT(7) 1548 1549 u8 rsvd[2]; 1550 __le32 addr_high; 1551 __le32 addr_low; 1552 }; 1553 1554 struct ice_aqc_get_port_options_elem { 1555 u8 pmd; 1556 #define ICE_AQC_PORT_OPT_PMD_COUNT_M GENMASK(3, 0) 1557 1558 u8 max_lane_speed; 1559 #define ICE_AQC_PORT_OPT_MAX_LANE_M GENMASK(3, 0) 1560 #define ICE_AQC_PORT_OPT_MAX_LANE_100M 0 1561 #define ICE_AQC_PORT_OPT_MAX_LANE_1G 1 1562 #define ICE_AQC_PORT_OPT_MAX_LANE_2500M 2 1563 #define ICE_AQC_PORT_OPT_MAX_LANE_5G 3 1564 #define ICE_AQC_PORT_OPT_MAX_LANE_10G 4 1565 #define ICE_AQC_PORT_OPT_MAX_LANE_25G 5 1566 #define ICE_AQC_PORT_OPT_MAX_LANE_50G 6 1567 #define ICE_AQC_PORT_OPT_MAX_LANE_100G 7 1568 #define ICE_AQC_PORT_OPT_MAX_LANE_200G 8 1569 #define ICE_AQC_PORT_OPT_MAX_LANE_40G 9 1570 1571 u8 global_scid[2]; 1572 u8 phy_scid[2]; 1573 u8 pf2port_cid[2]; 1574 }; 1575 1576 /* Set Port Option (direct, 0x06EB) */ 1577 struct ice_aqc_set_port_option { 1578 u8 lport_num; 1579 u8 lport_num_valid; 1580 u8 selected_port_option; 1581 u8 rsvd[13]; 1582 }; 1583 1584 /* Set/Get GPIO (direct, 0x06EC/0x06ED) */ 1585 struct ice_aqc_gpio { 1586 __le16 gpio_ctrl_handle; 1587 #define ICE_AQC_GPIO_HANDLE_S 0 1588 #define ICE_AQC_GPIO_HANDLE_M (0x3FF << ICE_AQC_GPIO_HANDLE_S) 1589 u8 gpio_num; 1590 u8 gpio_val; 1591 u8 rsvd[12]; 1592 }; 1593 1594 /* Read/Write SFF EEPROM command (indirect 0x06EE) */ 1595 struct ice_aqc_sff_eeprom { 1596 u8 lport_num; 1597 u8 lport_num_valid; 1598 #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0) 1599 __le16 i2c_bus_addr; 1600 #define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F 1601 #define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF 1602 #define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10) 1603 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0 1604 #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M 1605 #define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11 1606 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S) 1607 #define ICE_AQC_SFF_NO_PAGE_CHANGE 0 1608 #define ICE_AQC_SFF_SET_23_ON_MISMATCH 1 1609 #define ICE_AQC_SFF_SET_22_ON_MISMATCH 2 1610 #define ICE_AQC_SFF_IS_WRITE BIT(15) 1611 __le16 i2c_mem_addr; 1612 __le16 eeprom_page; 1613 #define ICE_AQC_SFF_EEPROM_BANK_S 0 1614 #define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S) 1615 #define ICE_AQC_SFF_EEPROM_PAGE_S 8 1616 #define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S) 1617 __le32 addr_high; 1618 __le32 addr_low; 1619 }; 1620 1621 /* NVM Read command (indirect 0x0701) 1622 * NVM Erase commands (direct 0x0702) 1623 * NVM Update commands (indirect 0x0703) 1624 */ 1625 struct ice_aqc_nvm { 1626 #define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF 1627 __le16 offset_low; 1628 u8 offset_high; 1629 u8 cmd_flags; 1630 #define ICE_AQC_NVM_LAST_CMD BIT(0) 1631 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */ 1632 #define ICE_AQC_NVM_PRESERVATION_S 1 1633 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S) 1634 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S) 1635 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1) 1636 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S) 1637 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S) 1638 #define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */ 1639 #define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4) 1640 #define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5) 1641 #define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6) 1642 #define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */ 1643 #define ICE_AQC_NVM_ACTIV_SEL_MASK ICE_M(0x7, 3) 1644 #define ICE_AQC_NVM_FLASH_ONLY BIT(7) 1645 #define ICE_AQC_NVM_RESET_LVL_M ICE_M(0x3, 0) /* Write reply only */ 1646 #define ICE_AQC_NVM_POR_FLAG 0 1647 #define ICE_AQC_NVM_PERST_FLAG 1 1648 #define ICE_AQC_NVM_EMPR_FLAG 2 1649 #define ICE_AQC_NVM_EMPR_ENA BIT(0) /* Write Activate reply only */ 1650 /* For Write Activate, several flags are sent as part of a separate 1651 * flags2 field using a separate byte. For simplicity of the software 1652 * interface, we pass the flags as a 16 bit value so these flags are 1653 * all offset by 8 bits 1654 */ 1655 #define ICE_AQC_NVM_ACTIV_REQ_EMPR BIT(8) /* NVM Write Activate only */ 1656 __le16 module_typeid; 1657 __le16 length; 1658 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF 1659 __le32 addr_high; 1660 __le32 addr_low; 1661 }; 1662 1663 #define ICE_AQC_NVM_START_POINT 0 1664 #define ICE_AQC_NVM_SECTOR_UNIT 4096 1665 #define ICE_AQC_NVM_SDP_AC_PTR_OFFSET 0xD8 1666 #define ICE_AQC_NVM_SDP_AC_PTR_M GENMASK(14, 0) 1667 #define ICE_AQC_NVM_SDP_AC_PTR_INVAL 0x7FFF 1668 #define ICE_AQC_NVM_SDP_AC_PTR_TYPE_M BIT(15) 1669 #define ICE_AQC_NVM_SDP_AC_SDP_NUM_M GENMASK(2, 0) 1670 #define ICE_AQC_NVM_SDP_AC_DIR_M BIT(3) 1671 #define ICE_AQC_NVM_SDP_AC_PIN_M GENMASK(15, 6) 1672 #define ICE_AQC_NVM_SDP_AC_MAX_SIZE 7 1673 1674 #define ICE_AQC_NVM_TX_TOPO_MOD_ID 0x14B 1675 1676 struct ice_aqc_nvm_tx_topo_user_sel { 1677 __le16 length; 1678 u8 data; 1679 #define ICE_AQC_NVM_TX_TOPO_USER_SEL BIT(4) 1680 u8 reserved; 1681 }; 1682 1683 /* NVM Checksum Command (direct, 0x0706) */ 1684 struct ice_aqc_nvm_checksum { 1685 u8 flags; 1686 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0) 1687 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1) 1688 u8 rsvd; 1689 __le16 checksum; /* Used only by response */ 1690 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA 1691 u8 rsvd2[12]; 1692 }; 1693 1694 /* Used for NVM Set Package Data command - 0x070A */ 1695 struct ice_aqc_nvm_pkg_data { 1696 u8 reserved[3]; 1697 u8 cmd_flags; 1698 #define ICE_AQC_NVM_PKG_DELETE BIT(0) /* used for command call */ 1699 #define ICE_AQC_NVM_PKG_SKIPPED BIT(0) /* used for command response */ 1700 1701 u32 reserved1; 1702 __le32 addr_high; 1703 __le32 addr_low; 1704 }; 1705 1706 /* Used for Pass Component Table command - 0x070B */ 1707 struct ice_aqc_nvm_pass_comp_tbl { 1708 u8 component_response; /* Response only */ 1709 #define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED 0x0 1710 #define ICE_AQ_NVM_PASS_COMP_CAN_MAY_BE_UPDATEABLE 0x1 1711 #define ICE_AQ_NVM_PASS_COMP_CAN_NOT_BE_UPDATED 0x2 1712 #define ICE_AQ_NVM_PASS_COMP_PARTIAL_CHECK 0x3 1713 u8 component_response_code; /* Response only */ 1714 #define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED_CODE 0x0 1715 #define ICE_AQ_NVM_PASS_COMP_STAMP_IDENTICAL_CODE 0x1 1716 #define ICE_AQ_NVM_PASS_COMP_STAMP_LOWER 0x2 1717 #define ICE_AQ_NVM_PASS_COMP_INVALID_STAMP_CODE 0x3 1718 #define ICE_AQ_NVM_PASS_COMP_CONFLICT_CODE 0x4 1719 #define ICE_AQ_NVM_PASS_COMP_PRE_REQ_NOT_MET_CODE 0x5 1720 #define ICE_AQ_NVM_PASS_COMP_NOT_SUPPORTED_CODE 0x6 1721 #define ICE_AQ_NVM_PASS_COMP_CANNOT_DOWNGRADE_CODE 0x7 1722 #define ICE_AQ_NVM_PASS_COMP_INCOMPLETE_IMAGE_CODE 0x8 1723 #define ICE_AQ_NVM_PASS_COMP_VER_STR_IDENTICAL_CODE 0xA 1724 #define ICE_AQ_NVM_PASS_COMP_VER_STR_LOWER_CODE 0xB 1725 u8 reserved; 1726 u8 transfer_flag; 1727 #define ICE_AQ_NVM_PASS_COMP_TBL_START 0x1 1728 #define ICE_AQ_NVM_PASS_COMP_TBL_MIDDLE 0x2 1729 #define ICE_AQ_NVM_PASS_COMP_TBL_END 0x4 1730 #define ICE_AQ_NVM_PASS_COMP_TBL_START_AND_END 0x5 1731 __le32 reserved1; 1732 __le32 addr_high; 1733 __le32 addr_low; 1734 }; 1735 1736 struct ice_aqc_nvm_comp_tbl { 1737 __le16 comp_class; 1738 #define NVM_COMP_CLASS_ALL_FW 0x000A 1739 1740 __le16 comp_id; 1741 #define NVM_COMP_ID_OROM 0x5 1742 #define NVM_COMP_ID_NVM 0x6 1743 #define NVM_COMP_ID_NETLIST 0x8 1744 1745 u8 comp_class_idx; 1746 #define FWU_COMP_CLASS_IDX_NOT_USE 0x0 1747 1748 __le32 comp_cmp_stamp; 1749 u8 cvs_type; 1750 #define NVM_CVS_TYPE_ASCII 0x1 1751 1752 u8 cvs_len; 1753 u8 cvs[]; /* Component Version String */ 1754 } __packed; 1755 1756 /* Send to PF command (indirect 0x0801) ID is only used by PF 1757 * 1758 * Send to VF command (indirect 0x0802) ID is only used by PF 1759 * 1760 */ 1761 struct ice_aqc_pf_vf_msg { 1762 __le32 id; 1763 u32 reserved; 1764 __le32 addr_high; 1765 __le32 addr_low; 1766 }; 1767 1768 /* Get LLDP MIB (indirect 0x0A00) 1769 * Note: This is also used by the LLDP MIB Change Event (0x0A01) 1770 * as the format is the same. 1771 */ 1772 struct ice_aqc_lldp_get_mib { 1773 u8 type; 1774 #define ICE_AQ_LLDP_MIB_TYPE_S 0 1775 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S) 1776 #define ICE_AQ_LLDP_MIB_LOCAL 0 1777 #define ICE_AQ_LLDP_MIB_REMOTE 1 1778 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2 1779 #define ICE_AQ_LLDP_BRID_TYPE_S 2 1780 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S) 1781 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0 1782 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1 1783 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */ 1784 #define ICE_AQ_LLDP_TX_S 0x4 1785 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S) 1786 #define ICE_AQ_LLDP_TX_ACTIVE 0 1787 #define ICE_AQ_LLDP_TX_SUSPENDED 1 1788 #define ICE_AQ_LLDP_TX_FLUSHED 3 1789 /* DCBX mode */ 1790 #define ICE_AQ_LLDP_DCBX_M GENMASK(7, 6) 1791 #define ICE_AQ_LLDP_DCBX_NA 0 1792 #define ICE_AQ_LLDP_DCBX_CEE 1 1793 #define ICE_AQ_LLDP_DCBX_IEEE 2 1794 1795 u8 state; 1796 #define ICE_AQ_LLDP_MIB_CHANGE_STATE_M BIT(0) 1797 #define ICE_AQ_LLDP_MIB_CHANGE_EXECUTED 0 1798 #define ICE_AQ_LLDP_MIB_CHANGE_PENDING 1 1799 1800 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00) 1801 * and in the LLDP MIB Change Event (0x0A01). They are valid for the 1802 * Get LLDP MIB (0x0A00) response only. 1803 */ 1804 __le16 local_len; 1805 __le16 remote_len; 1806 u8 reserved[2]; 1807 __le32 addr_high; 1808 __le32 addr_low; 1809 }; 1810 1811 /* Configure LLDP MIB Change Event (direct 0x0A01) */ 1812 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */ 1813 struct ice_aqc_lldp_set_mib_change { 1814 u8 command; 1815 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 1816 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1 1817 #define ICE_AQ_LLDP_MIB_PENDING_M BIT(1) 1818 #define ICE_AQ_LLDP_MIB_PENDING_DISABLE 0 1819 #define ICE_AQ_LLDP_MIB_PENDING_ENABLE 1 1820 u8 reserved[15]; 1821 }; 1822 1823 /* Stop LLDP (direct 0x0A05) */ 1824 struct ice_aqc_lldp_stop { 1825 u8 command; 1826 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0) 1827 #define ICE_AQ_LLDP_AGENT_STOP 0x0 1828 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK 1829 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1) 1830 u8 reserved[15]; 1831 }; 1832 1833 /* Start LLDP (direct 0x0A06) */ 1834 struct ice_aqc_lldp_start { 1835 u8 command; 1836 #define ICE_AQ_LLDP_AGENT_START BIT(0) 1837 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1) 1838 u8 reserved[15]; 1839 }; 1840 1841 /* Get CEE DCBX Oper Config (0x0A07) 1842 * The command uses the generic descriptor struct and 1843 * returns the struct below as an indirect response. 1844 */ 1845 struct ice_aqc_get_cee_dcb_cfg_resp { 1846 u8 oper_num_tc; 1847 u8 oper_prio_tc[4]; 1848 u8 oper_tc_bw[8]; 1849 u8 oper_pfc_en; 1850 __le16 oper_app_prio; 1851 #define ICE_AQC_CEE_APP_FCOE_S 0 1852 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S) 1853 #define ICE_AQC_CEE_APP_ISCSI_S 3 1854 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S) 1855 #define ICE_AQC_CEE_APP_FIP_S 8 1856 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S) 1857 __le32 tlv_status; 1858 #define ICE_AQC_CEE_PG_STATUS_S 0 1859 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S) 1860 #define ICE_AQC_CEE_PFC_STATUS_S 3 1861 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S) 1862 #define ICE_AQC_CEE_FCOE_STATUS_S 8 1863 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S) 1864 #define ICE_AQC_CEE_ISCSI_STATUS_S 11 1865 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S) 1866 #define ICE_AQC_CEE_FIP_STATUS_S 16 1867 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S) 1868 u8 reserved[12]; 1869 }; 1870 1871 /* Set Local LLDP MIB (indirect 0x0A08) 1872 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX 1873 */ 1874 struct ice_aqc_lldp_set_local_mib { 1875 u8 type; 1876 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0) 1877 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0 1878 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1) 1879 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0 1880 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M 1881 u8 reserved0; 1882 __le16 length; 1883 u8 reserved1[4]; 1884 __le32 addr_high; 1885 __le32 addr_low; 1886 }; 1887 1888 /* Stop/Start LLDP Agent (direct 0x0A09) 1889 * Used for stopping/starting specific LLDP agent. e.g. DCBX. 1890 * The same structure is used for the response, with the command field 1891 * being used as the status field. 1892 */ 1893 struct ice_aqc_lldp_stop_start_specific_agent { 1894 u8 command; 1895 #define ICE_AQC_START_STOP_AGENT_M BIT(0) 1896 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0 1897 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M 1898 u8 reserved[15]; 1899 }; 1900 1901 /* LLDP Filter Control (direct 0x0A0A) */ 1902 struct ice_aqc_lldp_filter_ctrl { 1903 u8 cmd_flags; 1904 #define ICE_AQC_LLDP_FILTER_ACTION_ADD 0x0 1905 #define ICE_AQC_LLDP_FILTER_ACTION_DELETE 0x1 1906 u8 reserved1; 1907 __le16 vsi_num; 1908 u8 reserved2[12]; 1909 }; 1910 1911 #define ICE_AQC_RSS_VSI_VALID BIT(15) 1912 1913 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */ 1914 struct ice_aqc_get_set_rss_key { 1915 __le16 vsi_id; 1916 u8 reserved[6]; 1917 __le32 addr_high; 1918 __le32 addr_low; 1919 }; 1920 1921 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28 1922 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC 1923 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \ 1924 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \ 1925 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE) 1926 1927 struct ice_aqc_get_set_rss_keys { 1928 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE]; 1929 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE]; 1930 }; 1931 1932 enum ice_lut_type { 1933 ICE_LUT_VSI = 0, 1934 ICE_LUT_PF = 1, 1935 ICE_LUT_GLOBAL = 2, 1936 }; 1937 1938 enum ice_lut_size { 1939 ICE_LUT_VSI_SIZE = 64, 1940 ICE_LUT_GLOBAL_SIZE = 512, 1941 ICE_LUT_PF_SIZE = 2048, 1942 }; 1943 1944 /* enum ice_aqc_lut_flags combines constants used to fill 1945 * &ice_aqc_get_set_rss_lut ::flags, which is an amalgamation of global LUT ID, 1946 * LUT size and LUT type, last of which does not need neither shift nor mask. 1947 */ 1948 enum ice_aqc_lut_flags { 1949 ICE_AQC_LUT_SIZE_SMALL = 0, /* size = 64 or 128 */ 1950 ICE_AQC_LUT_SIZE_512 = BIT(2), 1951 ICE_AQC_LUT_SIZE_2K = BIT(3), 1952 1953 ICE_AQC_LUT_GLOBAL_IDX = GENMASK(7, 4), 1954 }; 1955 1956 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */ 1957 struct ice_aqc_get_set_rss_lut { 1958 __le16 vsi_id; 1959 __le16 flags; 1960 __le32 reserved; 1961 __le32 addr_high; 1962 __le32 addr_low; 1963 }; 1964 1965 /* Sideband Control Interface Commands */ 1966 /* Neighbor Device Request (indirect 0x0C00); also used for the response. */ 1967 struct ice_aqc_neigh_dev_req { 1968 __le16 sb_data_len; 1969 u8 reserved[6]; 1970 __le32 addr_high; 1971 __le32 addr_low; 1972 }; 1973 1974 /* Add Tx LAN Queues (indirect 0x0C30) */ 1975 struct ice_aqc_add_txqs { 1976 u8 num_qgrps; 1977 u8 reserved[3]; 1978 __le32 reserved1; 1979 __le32 addr_high; 1980 __le32 addr_low; 1981 }; 1982 1983 /* This is the descriptor of each queue entry for the Add Tx LAN Queues 1984 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp. 1985 */ 1986 struct ice_aqc_add_txqs_perq { 1987 __le16 txq_id; 1988 u8 rsvd[2]; 1989 __le32 q_teid; 1990 ice_txq_ctx_buf_t txq_ctx; 1991 u8 rsvd2[2]; 1992 struct ice_aqc_txsched_elem info; 1993 } __packed; 1994 1995 /* The format of the command buffer for Add Tx LAN Queues (0x0C30) 1996 * is an array of the following structs. Please note that the length of 1997 * each struct ice_aqc_add_tx_qgrp is variable due 1998 * to the variable number of queues in each group! 1999 */ 2000 struct ice_aqc_add_tx_qgrp { 2001 __le32 parent_teid; 2002 u8 num_txqs; 2003 u8 rsvd[3]; 2004 struct ice_aqc_add_txqs_perq txqs[]; 2005 }; 2006 2007 /* Disable Tx LAN Queues (indirect 0x0C31) */ 2008 struct ice_aqc_dis_txqs { 2009 u8 cmd_type; 2010 #define ICE_AQC_Q_DIS_CMD_S 0 2011 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S) 2012 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S) 2013 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S) 2014 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S) 2015 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S) 2016 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2) 2017 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3) 2018 u8 num_entries; 2019 __le16 vmvf_and_timeout; 2020 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0 2021 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S) 2022 #define ICE_AQC_Q_DIS_TIMEOUT_S 10 2023 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S) 2024 __le32 blocked_cgds; 2025 __le32 addr_high; 2026 __le32 addr_low; 2027 }; 2028 2029 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31) 2030 * contains the following structures, arrayed one after the 2031 * other. 2032 * Note: Since the q_id is 16 bits wide, if the 2033 * number of queues is even, then 2 bytes of alignment MUST be 2034 * added before the start of the next group, to allow correct 2035 * alignment of the parent_teid field. 2036 */ 2037 struct ice_aqc_dis_txq_item { 2038 __le32 parent_teid; 2039 u8 num_qs; 2040 u8 rsvd; 2041 /* The length of the q_id array varies according to num_qs */ 2042 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15 2043 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \ 2044 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2045 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \ 2046 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2047 __le16 q_id[]; 2048 } __packed; 2049 2050 /* Move/Reconfigure Tx queue (indirect 0x0C32) */ 2051 struct ice_aqc_cfg_txqs { 2052 u8 cmd_type; 2053 #define ICE_AQC_Q_CFG_MOVE_NODE 0x1 2054 #define ICE_AQC_Q_CFG_TC_CHNG 0x2 2055 #define ICE_AQC_Q_CFG_MOVE_TC_CHNG 0x3 2056 #define ICE_AQC_Q_CFG_SUBSEQ_CALL BIT(2) 2057 #define ICE_AQC_Q_CFG_FLUSH BIT(3) 2058 u8 num_qs; 2059 u8 port_num_chng; 2060 #define ICE_AQC_Q_CFG_SRC_PRT_M 0x7 2061 #define ICE_AQC_Q_CFG_DST_PRT_S 3 2062 #define ICE_AQC_Q_CFG_DST_PRT_M (0x7 << ICE_AQC_Q_CFG_DST_PRT_S) 2063 u8 time_out; 2064 #define ICE_AQC_Q_CFG_TIMEOUT_S 2 2065 #define ICE_AQC_Q_CFG_TIMEOUT_M (0x1F << ICE_AQC_Q_CFG_TIMEOUT_S) 2066 __le32 blocked_cgds; 2067 __le32 addr_high; 2068 __le32 addr_low; 2069 }; 2070 2071 /* Per Q struct for Move/Reconfigure Tx LAN Queues (indirect 0x0C32) */ 2072 struct ice_aqc_cfg_txq_perq { 2073 __le16 q_handle; 2074 u8 tc; 2075 u8 rsvd; 2076 __le32 q_teid; 2077 }; 2078 2079 /* The buffer for Move/Reconfigure Tx LAN Queues (indirect 0x0C32) */ 2080 struct ice_aqc_cfg_txqs_buf { 2081 __le32 src_parent_teid; 2082 __le32 dst_parent_teid; 2083 struct ice_aqc_cfg_txq_perq queue_info[]; 2084 }; 2085 2086 /* Add Tx RDMA Queue Set (indirect 0x0C33) */ 2087 struct ice_aqc_add_rdma_qset { 2088 u8 num_qset_grps; 2089 u8 reserved[7]; 2090 __le32 addr_high; 2091 __le32 addr_low; 2092 }; 2093 2094 /* This is the descriptor of each Qset entry for the Add Tx RDMA Queue Set 2095 * command (0x0C33). Only used within struct ice_aqc_add_rdma_qset. 2096 */ 2097 struct ice_aqc_add_tx_rdma_qset_entry { 2098 __le16 tx_qset_id; 2099 u8 rsvd[2]; 2100 __le32 qset_teid; 2101 struct ice_aqc_txsched_elem info; 2102 }; 2103 2104 /* The format of the command buffer for Add Tx RDMA Queue Set(0x0C33) 2105 * is an array of the following structs. Please note that the length of 2106 * each struct ice_aqc_add_rdma_qset is variable due to the variable 2107 * number of queues in each group! 2108 */ 2109 struct ice_aqc_add_rdma_qset_data { 2110 __le32 parent_teid; 2111 __le16 num_qsets; 2112 u8 rsvd[2]; 2113 struct ice_aqc_add_tx_rdma_qset_entry rdma_qsets[]; 2114 }; 2115 2116 /* Download Package (indirect 0x0C40) */ 2117 /* Also used for Update Package (indirect 0x0C41 and 0x0C42) */ 2118 struct ice_aqc_download_pkg { 2119 u8 flags; 2120 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01 2121 u8 reserved[3]; 2122 __le32 reserved1; 2123 __le32 addr_high; 2124 __le32 addr_low; 2125 }; 2126 2127 struct ice_aqc_download_pkg_resp { 2128 __le32 error_offset; 2129 __le32 error_info; 2130 __le32 addr_high; 2131 __le32 addr_low; 2132 }; 2133 2134 /* Get Package Info List (indirect 0x0C43) */ 2135 struct ice_aqc_get_pkg_info_list { 2136 __le32 reserved1; 2137 __le32 reserved2; 2138 __le32 addr_high; 2139 __le32 addr_low; 2140 }; 2141 2142 /* Version format for packages */ 2143 struct ice_pkg_ver { 2144 u8 major; 2145 u8 minor; 2146 u8 update; 2147 u8 draft; 2148 }; 2149 2150 #define ICE_PKG_NAME_SIZE 32 2151 #define ICE_SEG_ID_SIZE 28 2152 #define ICE_SEG_NAME_SIZE 28 2153 2154 struct ice_aqc_get_pkg_info { 2155 struct ice_pkg_ver ver; 2156 char name[ICE_SEG_NAME_SIZE]; 2157 __le32 track_id; 2158 u8 is_in_nvm; 2159 u8 is_active; 2160 u8 is_active_at_boot; 2161 u8 is_modified; 2162 }; 2163 2164 /* Get Package Info List response buffer format (0x0C43) */ 2165 struct ice_aqc_get_pkg_info_resp { 2166 __le32 count; 2167 struct ice_aqc_get_pkg_info pkg_info[]; 2168 }; 2169 2170 #define ICE_CGU_INPUT_PHASE_OFFSET_BYTES 6 2171 2172 struct ice_cgu_input_measure { 2173 u8 phase_offset[ICE_CGU_INPUT_PHASE_OFFSET_BYTES]; 2174 __le32 freq; 2175 } __packed __aligned(sizeof(__le16)); 2176 2177 #define ICE_AQC_GET_CGU_IN_MEAS_DPLL_IDX_M ICE_M(0xf, 0) 2178 2179 /* Get CGU input measure command response data structure (indirect 0x0C59) */ 2180 struct ice_aqc_get_cgu_input_measure { 2181 u8 dpll_idx_opt; 2182 u8 length; 2183 u8 rsvd[6]; 2184 }; 2185 2186 #define ICE_AQC_GET_CGU_MAX_PHASE_ADJ GENMASK(30, 0) 2187 2188 /* Get CGU abilities command response data structure (indirect 0x0C61) */ 2189 struct ice_aqc_get_cgu_abilities { 2190 u8 num_inputs; 2191 u8 num_outputs; 2192 u8 pps_dpll_idx; 2193 u8 eec_dpll_idx; 2194 __le32 max_in_freq; 2195 __le32 max_in_phase_adj; 2196 __le32 max_out_freq; 2197 __le32 max_out_phase_adj; 2198 u8 cgu_part_num; 2199 u8 rsvd[3]; 2200 }; 2201 2202 #define ICE_AQC_CGU_IN_CFG_FLG2_REFSYNC_EN BIT(7) 2203 2204 /* Set CGU input config (direct 0x0C62) */ 2205 struct ice_aqc_set_cgu_input_config { 2206 u8 input_idx; 2207 u8 flags1; 2208 #define ICE_AQC_SET_CGU_IN_CFG_FLG1_UPDATE_FREQ BIT(6) 2209 #define ICE_AQC_SET_CGU_IN_CFG_FLG1_UPDATE_DELAY BIT(7) 2210 u8 flags2; 2211 #define ICE_AQC_SET_CGU_IN_CFG_FLG2_INPUT_EN BIT(5) 2212 #define ICE_AQC_SET_CGU_IN_CFG_FLG2_ESYNC_EN BIT(6) 2213 u8 rsvd; 2214 __le32 freq; 2215 __le32 phase_delay; 2216 u8 rsvd2[2]; 2217 __le16 node_handle; 2218 }; 2219 2220 /* Get CGU input config response descriptor structure (direct 0x0C63) */ 2221 struct ice_aqc_get_cgu_input_config { 2222 u8 input_idx; 2223 u8 status; 2224 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_LOS BIT(0) 2225 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_SCM_FAIL BIT(1) 2226 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_CFM_FAIL BIT(2) 2227 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_GST_FAIL BIT(3) 2228 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_PFM_FAIL BIT(4) 2229 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_ESYNC_FAIL BIT(6) 2230 #define ICE_AQC_GET_CGU_IN_CFG_STATUS_ESYNC_CAP BIT(7) 2231 u8 type; 2232 #define ICE_AQC_GET_CGU_IN_CFG_TYPE_READ_ONLY BIT(0) 2233 #define ICE_AQC_GET_CGU_IN_CFG_TYPE_GPS BIT(4) 2234 #define ICE_AQC_GET_CGU_IN_CFG_TYPE_EXTERNAL BIT(5) 2235 #define ICE_AQC_GET_CGU_IN_CFG_TYPE_PHY BIT(6) 2236 u8 flags1; 2237 #define ICE_AQC_GET_CGU_IN_CFG_FLG1_PHASE_DELAY_SUPP BIT(0) 2238 #define ICE_AQC_GET_CGU_IN_CFG_FLG1_1PPS_SUPP BIT(2) 2239 #define ICE_AQC_GET_CGU_IN_CFG_FLG1_10MHZ_SUPP BIT(3) 2240 #define ICE_AQC_GET_CGU_IN_CFG_FLG1_ANYFREQ BIT(7) 2241 __le32 freq; 2242 __le32 phase_delay; 2243 u8 flags2; 2244 #define ICE_AQC_GET_CGU_IN_CFG_FLG2_INPUT_EN BIT(5) 2245 #define ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN BIT(6) 2246 u8 rsvd[1]; 2247 __le16 node_handle; 2248 }; 2249 2250 /* Set CGU output config (direct 0x0C64) */ 2251 struct ice_aqc_set_cgu_output_config { 2252 u8 output_idx; 2253 u8 flags; 2254 #define ICE_AQC_SET_CGU_OUT_CFG_OUT_EN BIT(0) 2255 #define ICE_AQC_SET_CGU_OUT_CFG_ESYNC_EN BIT(1) 2256 #define ICE_AQC_SET_CGU_OUT_CFG_UPDATE_FREQ BIT(2) 2257 #define ICE_AQC_SET_CGU_OUT_CFG_UPDATE_PHASE BIT(3) 2258 #define ICE_AQC_SET_CGU_OUT_CFG_UPDATE_SRC_SEL BIT(4) 2259 u8 src_sel; 2260 #define ICE_AQC_SET_CGU_OUT_CFG_DPLL_SRC_SEL ICE_M(0x1F, 0) 2261 u8 rsvd; 2262 __le32 freq; 2263 __le32 phase_delay; 2264 u8 rsvd2[2]; 2265 __le16 node_handle; 2266 }; 2267 2268 /* Get CGU output config (direct 0x0C65) */ 2269 struct ice_aqc_get_cgu_output_config { 2270 u8 output_idx; 2271 u8 flags; 2272 #define ICE_AQC_GET_CGU_OUT_CFG_OUT_EN BIT(0) 2273 #define ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN BIT(1) 2274 #define ICE_AQC_GET_CGU_OUT_CFG_ESYNC_ABILITY BIT(2) 2275 u8 src_sel; 2276 #define ICE_AQC_GET_CGU_OUT_CFG_DPLL_SRC_SEL_SHIFT 0 2277 #define ICE_AQC_GET_CGU_OUT_CFG_DPLL_SRC_SEL \ 2278 ICE_M(0x1F, ICE_AQC_GET_CGU_OUT_CFG_DPLL_SRC_SEL_SHIFT) 2279 #define ICE_AQC_GET_CGU_OUT_CFG_DPLL_MODE_SHIFT 5 2280 #define ICE_AQC_GET_CGU_OUT_CFG_DPLL_MODE \ 2281 ICE_M(0x7, ICE_AQC_GET_CGU_OUT_CFG_DPLL_MODE_SHIFT) 2282 u8 rsvd; 2283 __le32 freq; 2284 __le32 src_freq; 2285 u8 rsvd2[2]; 2286 __le16 node_handle; 2287 }; 2288 2289 /* Get CGU DPLL status (direct 0x0C66) */ 2290 struct ice_aqc_get_cgu_dpll_status { 2291 u8 dpll_num; 2292 u8 ref_state; 2293 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_LOS BIT(0) 2294 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_SCM BIT(1) 2295 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_CFM BIT(2) 2296 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_GST BIT(3) 2297 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_PFM BIT(4) 2298 #define ICE_AQC_GET_CGU_DPLL_STATUS_FAST_LOCK_EN BIT(5) 2299 #define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_ESYNC BIT(6) 2300 u8 dpll_state; 2301 #define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_LOCK BIT(0) 2302 #define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_HO BIT(1) 2303 #define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_HO_READY BIT(2) 2304 #define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_FLHIT BIT(5) 2305 #define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_PSLHIT BIT(7) 2306 u8 config; 2307 #define ICE_AQC_GET_CGU_DPLL_CONFIG_CLK_REF_SEL ICE_M(0x1F, 0) 2308 #define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_SHIFT 5 2309 #define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE \ 2310 ICE_M(0x7, ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_SHIFT) 2311 #define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_FREERUN 0 2312 #define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_AUTOMATIC \ 2313 ICE_M(0x3, ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_SHIFT) 2314 __le32 phase_offset_h; 2315 __le32 phase_offset_l; 2316 u8 eec_mode; 2317 #define ICE_AQC_GET_CGU_DPLL_STATUS_EEC_MODE_1 0xA 2318 #define ICE_AQC_GET_CGU_DPLL_STATUS_EEC_MODE_2 0xB 2319 #define ICE_AQC_GET_CGU_DPLL_STATUS_EEC_MODE_UNKNOWN 0xF 2320 u8 rsvd[1]; 2321 __le16 node_handle; 2322 }; 2323 2324 /* Set CGU DPLL config (direct 0x0C67) */ 2325 struct ice_aqc_set_cgu_dpll_config { 2326 u8 dpll_num; 2327 u8 ref_state; 2328 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_LOS BIT(0) 2329 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_SCM BIT(1) 2330 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_CFM BIT(2) 2331 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_GST BIT(3) 2332 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_PFM BIT(4) 2333 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_FLOCK_EN BIT(5) 2334 #define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_ESYNC BIT(6) 2335 u8 rsvd; 2336 u8 config; 2337 #define ICE_AQC_SET_CGU_DPLL_CONFIG_CLK_REF_SEL ICE_M(0x1F, 0) 2338 #define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_SHIFT 5 2339 #define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE \ 2340 ICE_M(0x7, ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_SHIFT) 2341 #define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_FREERUN 0 2342 #define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_AUTOMATIC \ 2343 ICE_M(0x3, ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_SHIFT) 2344 u8 rsvd2[8]; 2345 u8 eec_mode; 2346 u8 rsvd3[1]; 2347 __le16 node_handle; 2348 }; 2349 2350 /* Set CGU reference priority (direct 0x0C68) */ 2351 struct ice_aqc_set_cgu_ref_prio { 2352 u8 dpll_num; 2353 u8 ref_idx; 2354 u8 ref_priority; 2355 u8 rsvd[11]; 2356 __le16 node_handle; 2357 }; 2358 2359 /* Get CGU reference priority (direct 0x0C69) */ 2360 struct ice_aqc_get_cgu_ref_prio { 2361 u8 dpll_num; 2362 u8 ref_idx; 2363 u8 ref_priority; /* Valid only in response */ 2364 u8 rsvd[13]; 2365 }; 2366 2367 /* Get CGU info (direct 0x0C6A) */ 2368 struct ice_aqc_get_cgu_info { 2369 __le32 cgu_id; 2370 __le32 cgu_cfg_ver; 2371 __le32 cgu_fw_ver; 2372 u8 node_part_num; 2373 u8 dev_rev; 2374 __le16 node_handle; 2375 }; 2376 2377 /* Driver Shared Parameters (direct, 0x0C90) */ 2378 struct ice_aqc_driver_shared_params { 2379 u8 set_or_get_op; 2380 #define ICE_AQC_DRIVER_PARAM_OP_MASK BIT(0) 2381 #define ICE_AQC_DRIVER_PARAM_SET 0 2382 #define ICE_AQC_DRIVER_PARAM_GET 1 2383 u8 param_indx; 2384 #define ICE_AQC_DRIVER_PARAM_MAX_IDX 15 2385 u8 rsvd[2]; 2386 __le32 param_val; 2387 __le32 addr_high; 2388 __le32 addr_low; 2389 }; 2390 2391 /* Lan Queue Overflow Event (direct, 0x1001) */ 2392 struct ice_aqc_event_lan_overflow { 2393 __le32 prtdcb_ruptq; 2394 __le32 qtx_ctl; 2395 u8 reserved[8]; 2396 }; 2397 2398 enum ice_aqc_fw_logging_mod { 2399 ICE_AQC_FW_LOG_ID_GENERAL = 0, 2400 ICE_AQC_FW_LOG_ID_CTRL, 2401 ICE_AQC_FW_LOG_ID_LINK, 2402 ICE_AQC_FW_LOG_ID_LINK_TOPO, 2403 ICE_AQC_FW_LOG_ID_DNL, 2404 ICE_AQC_FW_LOG_ID_I2C, 2405 ICE_AQC_FW_LOG_ID_SDP, 2406 ICE_AQC_FW_LOG_ID_MDIO, 2407 ICE_AQC_FW_LOG_ID_ADMINQ, 2408 ICE_AQC_FW_LOG_ID_HDMA, 2409 ICE_AQC_FW_LOG_ID_LLDP, 2410 ICE_AQC_FW_LOG_ID_DCBX, 2411 ICE_AQC_FW_LOG_ID_DCB, 2412 ICE_AQC_FW_LOG_ID_XLR, 2413 ICE_AQC_FW_LOG_ID_NVM, 2414 ICE_AQC_FW_LOG_ID_AUTH, 2415 ICE_AQC_FW_LOG_ID_VPD, 2416 ICE_AQC_FW_LOG_ID_IOSF, 2417 ICE_AQC_FW_LOG_ID_PARSER, 2418 ICE_AQC_FW_LOG_ID_SW, 2419 ICE_AQC_FW_LOG_ID_SCHEDULER, 2420 ICE_AQC_FW_LOG_ID_TXQ, 2421 ICE_AQC_FW_LOG_ID_RSVD, 2422 ICE_AQC_FW_LOG_ID_POST, 2423 ICE_AQC_FW_LOG_ID_WATCHDOG, 2424 ICE_AQC_FW_LOG_ID_TASK_DISPATCH, 2425 ICE_AQC_FW_LOG_ID_MNG, 2426 ICE_AQC_FW_LOG_ID_SYNCE, 2427 ICE_AQC_FW_LOG_ID_HEALTH, 2428 ICE_AQC_FW_LOG_ID_TSDRV, 2429 ICE_AQC_FW_LOG_ID_PFREG, 2430 ICE_AQC_FW_LOG_ID_MDLVER, 2431 ICE_AQC_FW_LOG_ID_MAX, 2432 }; 2433 2434 enum ice_aqc_health_status_mask { 2435 ICE_AQC_HEALTH_STATUS_SET_PF_SPECIFIC_MASK = BIT(0), 2436 ICE_AQC_HEALTH_STATUS_SET_ALL_PF_MASK = BIT(1), 2437 ICE_AQC_HEALTH_STATUS_SET_GLOBAL_MASK = BIT(2), 2438 }; 2439 2440 /* Set Health Status (direct 0xFF20) */ 2441 struct ice_aqc_set_health_status_cfg { 2442 u8 event_source; 2443 u8 reserved[15]; 2444 }; 2445 2446 enum ice_aqc_health_status { 2447 ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_STRICT = 0x101, 2448 ICE_AQC_HEALTH_STATUS_ERR_MOD_TYPE = 0x102, 2449 ICE_AQC_HEALTH_STATUS_ERR_MOD_QUAL = 0x103, 2450 ICE_AQC_HEALTH_STATUS_ERR_MOD_COMM = 0x104, 2451 ICE_AQC_HEALTH_STATUS_ERR_MOD_CONFLICT = 0x105, 2452 ICE_AQC_HEALTH_STATUS_ERR_MOD_NOT_PRESENT = 0x106, 2453 ICE_AQC_HEALTH_STATUS_INFO_MOD_UNDERUTILIZED = 0x107, 2454 ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_LENIENT = 0x108, 2455 ICE_AQC_HEALTH_STATUS_ERR_MOD_DIAGNOSTIC_FEATURE = 0x109, 2456 ICE_AQC_HEALTH_STATUS_ERR_INVALID_LINK_CFG = 0x10B, 2457 ICE_AQC_HEALTH_STATUS_ERR_PORT_ACCESS = 0x10C, 2458 ICE_AQC_HEALTH_STATUS_ERR_PORT_UNREACHABLE = 0x10D, 2459 ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_MOD_LIMITED = 0x10F, 2460 ICE_AQC_HEALTH_STATUS_ERR_PARALLEL_FAULT = 0x110, 2461 ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_PHY_LIMITED = 0x111, 2462 ICE_AQC_HEALTH_STATUS_ERR_NETLIST_TOPO = 0x112, 2463 ICE_AQC_HEALTH_STATUS_ERR_NETLIST = 0x113, 2464 ICE_AQC_HEALTH_STATUS_ERR_TOPO_CONFLICT = 0x114, 2465 ICE_AQC_HEALTH_STATUS_ERR_LINK_HW_ACCESS = 0x115, 2466 ICE_AQC_HEALTH_STATUS_ERR_LINK_RUNTIME = 0x116, 2467 ICE_AQC_HEALTH_STATUS_ERR_DNL_INIT = 0x117, 2468 ICE_AQC_HEALTH_STATUS_ERR_PHY_NVM_PROG = 0x120, 2469 ICE_AQC_HEALTH_STATUS_ERR_PHY_FW_LOAD = 0x121, 2470 ICE_AQC_HEALTH_STATUS_INFO_RECOVERY = 0x500, 2471 ICE_AQC_HEALTH_STATUS_ERR_FLASH_ACCESS = 0x501, 2472 ICE_AQC_HEALTH_STATUS_ERR_NVM_AUTH = 0x502, 2473 ICE_AQC_HEALTH_STATUS_ERR_OROM_AUTH = 0x503, 2474 ICE_AQC_HEALTH_STATUS_ERR_DDP_AUTH = 0x504, 2475 ICE_AQC_HEALTH_STATUS_ERR_NVM_COMPAT = 0x505, 2476 ICE_AQC_HEALTH_STATUS_ERR_OROM_COMPAT = 0x506, 2477 ICE_AQC_HEALTH_STATUS_ERR_NVM_SEC_VIOLATION = 0x507, 2478 ICE_AQC_HEALTH_STATUS_ERR_OROM_SEC_VIOLATION = 0x508, 2479 ICE_AQC_HEALTH_STATUS_ERR_DCB_MIB = 0x509, 2480 ICE_AQC_HEALTH_STATUS_ERR_MNG_TIMEOUT = 0x50A, 2481 ICE_AQC_HEALTH_STATUS_ERR_BMC_RESET = 0x50B, 2482 ICE_AQC_HEALTH_STATUS_ERR_LAST_MNG_FAIL = 0x50C, 2483 ICE_AQC_HEALTH_STATUS_ERR_RESOURCE_ALLOC_FAIL = 0x50D, 2484 ICE_AQC_HEALTH_STATUS_ERR_FW_LOOP = 0x1000, 2485 ICE_AQC_HEALTH_STATUS_ERR_FW_PFR_FAIL = 0x1001, 2486 ICE_AQC_HEALTH_STATUS_ERR_LAST_FAIL_AQ = 0x1002, 2487 }; 2488 2489 /* Get Health Status (indirect 0xFF22) */ 2490 struct ice_aqc_get_health_status { 2491 __le16 health_status_count; 2492 u8 reserved[6]; 2493 __le32 addr_high; 2494 __le32 addr_low; 2495 }; 2496 2497 enum ice_aqc_health_status_scope { 2498 ICE_AQC_HEALTH_STATUS_PF = 0x1, 2499 ICE_AQC_HEALTH_STATUS_PORT = 0x2, 2500 ICE_AQC_HEALTH_STATUS_GLOBAL = 0x3, 2501 }; 2502 2503 #define ICE_AQC_HEALTH_STATUS_UNDEFINED_DATA 0xDEADBEEF 2504 2505 /* Get Health Status event buffer entry (0xFF22), 2506 * repeated per reported health status. 2507 */ 2508 struct ice_aqc_health_status_elem { 2509 __le16 health_status_code; 2510 __le16 event_source; 2511 __le32 internal_data1; 2512 __le32 internal_data2; 2513 }; 2514 2515 /* Set FW Logging configuration (indirect 0xFF30) 2516 * Register for FW Logging (indirect 0xFF31) 2517 * Query FW Logging (indirect 0xFF32) 2518 * FW Log Event (indirect 0xFF33) 2519 */ 2520 struct ice_aqc_fw_log { 2521 u8 cmd_flags; 2522 #define ICE_AQC_FW_LOG_CONF_UART_EN BIT(0) 2523 #define ICE_AQC_FW_LOG_CONF_AQ_EN BIT(1) 2524 #define ICE_AQC_FW_LOG_QUERY_REGISTERED BIT(2) 2525 #define ICE_AQC_FW_LOG_CONF_SET_VALID BIT(3) 2526 #define ICE_AQC_FW_LOG_AQ_REGISTER BIT(0) 2527 #define ICE_AQC_FW_LOG_AQ_QUERY BIT(2) 2528 2529 u8 rsp_flag; 2530 __le16 fw_rt_msb; 2531 union { 2532 struct { 2533 __le32 fw_rt_lsb; 2534 } sync; 2535 struct { 2536 __le16 log_resolution; 2537 #define ICE_AQC_FW_LOG_MIN_RESOLUTION (1) 2538 #define ICE_AQC_FW_LOG_MAX_RESOLUTION (128) 2539 2540 __le16 mdl_cnt; 2541 } cfg; 2542 } ops; 2543 __le32 addr_high; 2544 __le32 addr_low; 2545 }; 2546 2547 /* Response Buffer for: 2548 * Set Firmware Logging Configuration (0xFF30) 2549 * Query FW Logging (0xFF32) 2550 */ 2551 struct ice_aqc_fw_log_cfg_resp { 2552 __le16 module_identifier; 2553 u8 log_level; 2554 u8 rsvd0; 2555 }; 2556 2557 /* Admin Queue command opcodes */ 2558 enum ice_adminq_opc { 2559 /* AQ commands */ 2560 ice_aqc_opc_get_ver = 0x0001, 2561 ice_aqc_opc_driver_ver = 0x0002, 2562 ice_aqc_opc_q_shutdown = 0x0003, 2563 2564 /* resource ownership */ 2565 ice_aqc_opc_req_res = 0x0008, 2566 ice_aqc_opc_release_res = 0x0009, 2567 2568 /* device/function capabilities */ 2569 ice_aqc_opc_list_func_caps = 0x000A, 2570 ice_aqc_opc_list_dev_caps = 0x000B, 2571 2572 /* manage MAC address */ 2573 ice_aqc_opc_manage_mac_read = 0x0107, 2574 ice_aqc_opc_manage_mac_write = 0x0108, 2575 2576 /* PXE */ 2577 ice_aqc_opc_clear_pxe_mode = 0x0110, 2578 2579 /* internal switch commands */ 2580 ice_aqc_opc_get_sw_cfg = 0x0200, 2581 ice_aqc_opc_set_port_params = 0x0203, 2582 2583 /* Alloc/Free/Get Resources */ 2584 ice_aqc_opc_alloc_res = 0x0208, 2585 ice_aqc_opc_free_res = 0x0209, 2586 ice_aqc_opc_share_res = 0x020B, 2587 ice_aqc_opc_set_vlan_mode_parameters = 0x020C, 2588 ice_aqc_opc_get_vlan_mode_parameters = 0x020D, 2589 2590 /* VSI commands */ 2591 ice_aqc_opc_add_vsi = 0x0210, 2592 ice_aqc_opc_update_vsi = 0x0211, 2593 ice_aqc_opc_free_vsi = 0x0213, 2594 2595 /* recipe commands */ 2596 ice_aqc_opc_add_recipe = 0x0290, 2597 ice_aqc_opc_recipe_to_profile = 0x0291, 2598 ice_aqc_opc_get_recipe = 0x0292, 2599 ice_aqc_opc_get_recipe_to_profile = 0x0293, 2600 2601 /* switch rules population commands */ 2602 ice_aqc_opc_add_sw_rules = 0x02A0, 2603 ice_aqc_opc_update_sw_rules = 0x02A1, 2604 ice_aqc_opc_remove_sw_rules = 0x02A2, 2605 2606 ice_aqc_opc_clear_pf_cfg = 0x02A4, 2607 2608 /* DCB commands */ 2609 ice_aqc_opc_query_pfc_mode = 0x0302, 2610 ice_aqc_opc_set_pfc_mode = 0x0303, 2611 2612 /* transmit scheduler commands */ 2613 ice_aqc_opc_get_dflt_topo = 0x0400, 2614 ice_aqc_opc_add_sched_elems = 0x0401, 2615 ice_aqc_opc_cfg_sched_elems = 0x0403, 2616 ice_aqc_opc_get_sched_elems = 0x0404, 2617 ice_aqc_opc_move_sched_elems = 0x0408, 2618 ice_aqc_opc_suspend_sched_elems = 0x0409, 2619 ice_aqc_opc_resume_sched_elems = 0x040A, 2620 ice_aqc_opc_query_port_ets = 0x040E, 2621 ice_aqc_opc_delete_sched_elems = 0x040F, 2622 ice_aqc_opc_add_rl_profiles = 0x0410, 2623 ice_aqc_opc_query_sched_res = 0x0412, 2624 ice_aqc_opc_remove_rl_profiles = 0x0415, 2625 2626 /* tx topology commands */ 2627 ice_aqc_opc_set_tx_topo = 0x0417, 2628 ice_aqc_opc_get_tx_topo = 0x0418, 2629 2630 /* PHY commands */ 2631 ice_aqc_opc_get_phy_caps = 0x0600, 2632 ice_aqc_opc_set_phy_cfg = 0x0601, 2633 ice_aqc_opc_set_mac_cfg = 0x0603, 2634 ice_aqc_opc_restart_an = 0x0605, 2635 ice_aqc_opc_get_link_status = 0x0607, 2636 ice_aqc_opc_set_event_mask = 0x0613, 2637 ice_aqc_opc_set_mac_lb = 0x0620, 2638 ice_aqc_opc_set_phy_rec_clk_out = 0x0630, 2639 ice_aqc_opc_get_phy_rec_clk_out = 0x0631, 2640 ice_aqc_opc_get_sensor_reading = 0x0632, 2641 ice_aqc_opc_dnl_call = 0x0682, 2642 ice_aqc_opc_get_link_topo = 0x06E0, 2643 ice_aqc_opc_read_i2c = 0x06E2, 2644 ice_aqc_opc_write_i2c = 0x06E3, 2645 ice_aqc_opc_set_port_id_led = 0x06E9, 2646 ice_aqc_opc_get_port_options = 0x06EA, 2647 ice_aqc_opc_set_port_option = 0x06EB, 2648 ice_aqc_opc_set_gpio = 0x06EC, 2649 ice_aqc_opc_get_gpio = 0x06ED, 2650 ice_aqc_opc_sff_eeprom = 0x06EE, 2651 2652 /* NVM commands */ 2653 ice_aqc_opc_nvm_read = 0x0701, 2654 ice_aqc_opc_nvm_erase = 0x0702, 2655 ice_aqc_opc_nvm_write = 0x0703, 2656 ice_aqc_opc_nvm_checksum = 0x0706, 2657 ice_aqc_opc_nvm_write_activate = 0x0707, 2658 ice_aqc_opc_nvm_update_empr = 0x0709, 2659 ice_aqc_opc_nvm_pkg_data = 0x070A, 2660 ice_aqc_opc_nvm_pass_component_tbl = 0x070B, 2661 2662 /* PF/VF mailbox commands */ 2663 ice_mbx_opc_send_msg_to_pf = 0x0801, 2664 ice_mbx_opc_send_msg_to_vf = 0x0802, 2665 /* LLDP commands */ 2666 ice_aqc_opc_lldp_get_mib = 0x0A00, 2667 ice_aqc_opc_lldp_set_mib_change = 0x0A01, 2668 ice_aqc_opc_lldp_stop = 0x0A05, 2669 ice_aqc_opc_lldp_start = 0x0A06, 2670 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07, 2671 ice_aqc_opc_lldp_set_local_mib = 0x0A08, 2672 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09, 2673 ice_aqc_opc_lldp_filter_ctrl = 0x0A0A, 2674 ice_aqc_opc_lldp_execute_pending_mib = 0x0A0B, 2675 2676 /* RSS commands */ 2677 ice_aqc_opc_set_rss_key = 0x0B02, 2678 ice_aqc_opc_set_rss_lut = 0x0B03, 2679 ice_aqc_opc_get_rss_key = 0x0B04, 2680 ice_aqc_opc_get_rss_lut = 0x0B05, 2681 2682 /* Sideband Control Interface commands */ 2683 ice_aqc_opc_neighbour_device_request = 0x0C00, 2684 2685 /* Tx queue handling commands/events */ 2686 ice_aqc_opc_add_txqs = 0x0C30, 2687 ice_aqc_opc_dis_txqs = 0x0C31, 2688 ice_aqc_opc_cfg_txqs = 0x0C32, 2689 ice_aqc_opc_add_rdma_qset = 0x0C33, 2690 2691 /* package commands */ 2692 ice_aqc_opc_download_pkg = 0x0C40, 2693 ice_aqc_opc_upload_section = 0x0C41, 2694 ice_aqc_opc_update_pkg = 0x0C42, 2695 ice_aqc_opc_get_pkg_info_list = 0x0C43, 2696 2697 /* 1588/SyncE commands/events */ 2698 ice_aqc_opc_get_cgu_input_measure = 0x0C59, 2699 ice_aqc_opc_get_cgu_abilities = 0x0C61, 2700 ice_aqc_opc_set_cgu_input_config = 0x0C62, 2701 ice_aqc_opc_get_cgu_input_config = 0x0C63, 2702 ice_aqc_opc_set_cgu_output_config = 0x0C64, 2703 ice_aqc_opc_get_cgu_output_config = 0x0C65, 2704 ice_aqc_opc_get_cgu_dpll_status = 0x0C66, 2705 ice_aqc_opc_set_cgu_dpll_config = 0x0C67, 2706 ice_aqc_opc_set_cgu_ref_prio = 0x0C68, 2707 ice_aqc_opc_get_cgu_ref_prio = 0x0C69, 2708 ice_aqc_opc_get_cgu_info = 0x0C6A, 2709 2710 ice_aqc_opc_driver_shared_params = 0x0C90, 2711 2712 /* Standalone Commands/Events */ 2713 ice_aqc_opc_event_lan_overflow = 0x1001, 2714 2715 /* System Diagnostic commands */ 2716 ice_aqc_opc_set_health_status_cfg = 0xFF20, 2717 ice_aqc_opc_get_health_status = 0xFF22, 2718 2719 /* FW Logging Commands */ 2720 ice_aqc_opc_fw_logs_config = 0xFF30, 2721 ice_aqc_opc_fw_logs_register = 0xFF31, 2722 ice_aqc_opc_fw_logs_query = 0xFF32, 2723 ice_aqc_opc_fw_logs_event = 0xFF33, 2724 }; 2725 2726 #endif /* _ICE_ADMINQ_CMD_H_ */ 2727