1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
5 * Copyright (c) 2024 Pierre-Luc Drouin <pldrouin@pldrouin.net>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 /*
30 * Vybrid Family Inter-Integrated Circuit (I2C)
31 * Originally based on Chapter 48, Vybrid Reference Manual, Rev. 5, 07/2013
32 * Currently based on Chapter 21, LX2160A Reference Manual, Rev. 1, 10/2021
33 *
34 * The current implementation is based on the original driver by Ruslan Bukin,
35 * later modified by Dawid Górecki, and split into FDT and ACPI drivers by Val
36 * Packett.
37 */
38
39 #include <sys/types.h>
40 #include <sys/mutex.h>
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/bus.h>
44 #include <sys/kernel.h>
45 #include <sys/module.h>
46 #include <sys/malloc.h>
47 #include <sys/rman.h>
48 #include <sys/timeet.h>
49 #include <sys/timetc.h>
50
51 #include <dev/iicbus/iiconf.h>
52 #include <dev/iicbus/iicbus.h>
53
54 #include "iicbus_if.h"
55
56 #include <machine/bus.h>
57 #include <machine/cpu.h>
58 #include <machine/intr.h>
59
60 #include <dev/iicbus/controller/vybrid/vf_i2c.h>
61
62 #define I2C_IBAD 0x0 /* I2C Bus Address Register */
63 #define I2C_IBFD 0x1 /* I2C Bus Frequency Divider Register */
64 #define I2C_IBCR 0x2 /* I2C Bus Control Register */
65 #define IBCR_MDIS (1 << 7) /* Module disable. */
66 #define IBCR_IBIE (1 << 6) /* I-Bus Interrupt Enable. */
67 #define IBCR_MSSL (1 << 5) /* Master/Slave mode select. */
68 #define IBCR_TXRX (1 << 4) /* Transmit/Receive mode select. */
69 #define IBCR_NOACK (1 << 3) /* Data Acknowledge disable. */
70 #define IBCR_RSTA (1 << 2) /* Repeat Start. */
71 #define IBCR_DMAEN (1 << 1) /* DMA Enable. */
72 #define I2C_IBSR 0x3 /* I2C Bus Status Register */
73 #define IBSR_TCF (1 << 7) /* Transfer complete. */
74 #define IBSR_IAAS (1 << 6) /* Addressed as a slave. */
75 #define IBSR_IBB (1 << 5) /* Bus busy. */
76 #define IBSR_IBAL (1 << 4) /* Arbitration Lost. */
77 #define IBSR_SRW (1 << 2) /* Slave Read/Write. */
78 #define IBSR_IBIF (1 << 1) /* I-Bus Interrupt Flag. */
79 #define IBSR_RXAK (1 << 0) /* Received Acknowledge. */
80 #define I2C_IBDR 0x4 /* I2C Bus Data I/O Register */
81 #define I2C_IBIC 0x5 /* I2C Bus Interrupt Config Register */
82 #define IBIC_BIIE (1 << 7) /* Bus Idle Interrupt Enable bit. */
83 #define I2C_IBDBG 0x6 /* I2C Bus Debug Register */
84
85 #define DIV_REG_UNSET 0xFF
86
87 #define READ1(_sc, _reg) bus_space_read_1(_sc->bst, _sc->bsh, _reg)
88 #define WRITE1(_sc, _reg, _val) bus_space_write_1(_sc->bst,\
89 _sc->bsh, _reg, _val)
90
91 #ifdef DEBUG
92 #define vf_i2c_dbg(_sc, fmt, args...) \
93 device_printf((_sc)->dev, fmt, ##args)
94 #ifdef DEBUG2
95 #undef WRITE1
96 #define WRITE1(_sc, _reg, _val) ({\
97 vf_i2c_dbg(_sc, "WRITE1 REG 0x%02X VAL 0x%02X\n",_reg,_val);\
98 bus_space_write_1(_sc->bst, _sc->bsh, _reg, _val);\
99 })
100 #undef READ1
101 #define READ1(_sc, _reg) ({\
102 uint32_t ret=bus_space_read_1(_sc->bst, _sc->bsh, _reg);\
103 vf_i2c_dbg(_sc, "READ1 REG 0x%02X RETURNS 0x%02X\n",_reg,ret);\
104 ret;\
105 })
106 #endif
107 #else
108 #define vf_i2c_dbg(_sc, fmt, args...)
109 #endif
110
111 static int i2c_repeated_start(device_t, u_char, int);
112 static int i2c_start(device_t, u_char, int);
113 static int i2c_stop(device_t);
114 static int i2c_reset(device_t, u_char, u_char, u_char *);
115 static int i2c_read(device_t, char *, int, int *, int, int);
116 static int i2c_write(device_t, const char *, int, int *, int);
117
118 struct i2c_div_type {
119 uint32_t reg_val;
120 uint32_t div;
121 };
122
123 static struct resource_spec i2c_spec[] = {
124 { SYS_RES_MEMORY, 0, RF_ACTIVE },
125 { SYS_RES_IRQ, 0, RF_ACTIVE },
126 { -1, 0 }
127 };
128
129 static struct i2c_div_type vf610_div_table[] = {
130 { 0x00, 20 }, { 0x01, 22 }, { 0x02, 24 }, { 0x03, 26 },
131 { 0x04, 28 }, { 0x05, 30 }, { 0x09, 32 }, { 0x06, 34 },
132 { 0x0A, 36 }, { 0x0B, 40 }, { 0x0C, 44 }, { 0x0D, 48 },
133 { 0x0E, 56 }, { 0x12, 64 }, { 0x13, 72 }, { 0x14, 80 },
134 { 0x15, 88 }, { 0x19, 96 }, { 0x16, 104 }, { 0x1A, 112 },
135 { 0x17, 128 }, { 0x1D, 160 }, { 0x1E, 192 }, { 0x22, 224 },
136 { 0x1F, 240 }, { 0x23, 256 }, { 0x24, 288 }, { 0x25, 320 },
137 { 0x26, 384 }, { 0x2A, 448 }, { 0x27, 480 }, { 0x2B, 512 },
138 { 0x2C, 576 }, { 0x2D, 640 }, { 0x2E, 768 }, { 0x32, 896 },
139 { 0x2F, 960 }, { 0x33, 1024 }, { 0x34, 1152 }, { 0x35, 1280 },
140 { 0x36, 1536 }, { 0x3A, 1792 }, { 0x37, 1920 }, { 0x3B, 2048 },
141 { 0x3C, 2304 }, { 0x3D, 2560 }, { 0x3E, 3072 }, { 0x3F, 3840 },
142 { 0x3F, 3840 }, { 0x7B, 4096 }, { 0x7D, 5120 }, { 0x7E, 6144 },
143 };
144
145 int
vf_i2c_attach_common(device_t dev)146 vf_i2c_attach_common(device_t dev)
147 {
148 struct vf_i2c_softc *sc;
149 int error;
150
151 sc = device_get_softc(dev);
152
153 vf_i2c_dbg(sc, "i2c attach common\n");
154
155 mtx_init(&sc->mutex, device_get_nameunit(dev), "I2C", MTX_DEF);
156
157 error = bus_alloc_resources(dev, i2c_spec, sc->res);
158 if (error != 0) {
159 mtx_destroy(&sc->mutex);
160 device_printf(dev, "could not allocate resources\n");
161 return (ENXIO);
162 }
163
164 /* Memory interface */
165 sc->bst = rman_get_bustag(sc->res[0]);
166 sc->bsh = rman_get_bushandle(sc->res[0]);
167
168 mtx_lock(&sc->mutex);
169
170 WRITE1(sc, I2C_IBIC, IBIC_BIIE);
171
172 if (sc->freq == 0) {
173 uint8_t div_reg;
174
175 div_reg = READ1(sc, I2C_IBFD);
176
177 if (div_reg != 0x00) {
178 sc->freq = UINT32_MAX;
179 device_printf(dev, "Using existing bus frequency divider register value (0x%02X).\n", div_reg);
180 } else {
181 device_printf(dev, "Bus frequency divider value appears unset, defaulting to low I2C bus speed.\n");
182 }
183 }
184
185 mtx_unlock(&sc->mutex);
186
187 sc->iicbus = device_add_child(dev, "iicbus", DEVICE_UNIT_ANY);
188
189 if (sc->iicbus == NULL) {
190 device_printf(dev, "could not add iicbus child");
191 mtx_destroy(&sc->mutex);
192 bus_release_resources(dev, i2c_spec, sc->res);
193 return (ENXIO);
194 }
195
196 bus_attach_children(dev);
197
198 return (0);
199 }
200
201 static int
i2c_detach(device_t dev)202 i2c_detach(device_t dev)
203 {
204 struct vf_i2c_softc *sc;
205 int error = 0;
206
207 sc = device_get_softc(dev);
208 vf_i2c_dbg(sc, "i2c detach\n");
209
210 error = bus_generic_detach(dev);
211 if (error != 0) {
212 device_printf(dev, "cannot detach child devices.\n");
213 return (error);
214 }
215
216 error = device_delete_child(dev, sc->iicbus);
217 if (error != 0) {
218 device_printf(dev, "could not delete iicbus child.\n");
219 return (error);
220 }
221
222 mtx_lock(&sc->mutex);
223
224 if (sc->freq == 0) {
225 vf_i2c_dbg(sc, "Writing 0x00 to clock divider register\n");
226 WRITE1(sc, I2C_IBFD, 0x00);
227 }
228
229 bus_release_resources(dev, i2c_spec, sc->res);
230
231 mtx_unlock(&sc->mutex);
232
233 mtx_destroy(&sc->mutex);
234
235 return (0);
236 }
237
238 /* Wait for free bus */
239 static int
wait_for_nibb(struct vf_i2c_softc * sc)240 wait_for_nibb(struct vf_i2c_softc *sc)
241 {
242 int retry;
243
244 retry = 1000;
245 while (retry --) {
246 if ((READ1(sc, I2C_IBSR) & IBSR_IBB) == 0)
247 return (IIC_NOERR);
248 DELAY(10);
249 }
250
251 return (IIC_ETIMEOUT);
252 }
253
254 /* Wait for transfer complete+interrupt flag */
255 static int
wait_for_icf(struct vf_i2c_softc * sc)256 wait_for_icf(struct vf_i2c_softc *sc)
257 {
258 int retry;
259 uint8_t ibsr;
260
261 vf_i2c_dbg(sc, "i2c wait for transfer complete + interrupt flag\n");
262
263 retry = 1000;
264 while (retry --) {
265 ibsr = READ1(sc, I2C_IBSR);
266
267 if (ibsr & IBSR_IBIF) {
268 WRITE1(sc, I2C_IBSR, IBSR_IBIF);
269
270 if (ibsr & IBSR_IBAL) {
271 WRITE1(sc, I2C_IBSR, IBSR_IBAL);
272 return (IIC_EBUSBSY);
273 }
274
275 if (ibsr & IBSR_TCF)
276 return (IIC_NOERR);
277 }
278 DELAY(10);
279 }
280
281 return (IIC_ETIMEOUT);
282 }
283 /* Get ACK bit from last write */
284 static bool
tx_acked(struct vf_i2c_softc * sc)285 tx_acked(struct vf_i2c_softc *sc)
286 {
287 vf_i2c_dbg(sc, "i2c get ACK bit from last write\n");
288
289 return (READ1(sc, I2C_IBSR) & IBSR_RXAK) ? false : true;
290
291 }
292
293 static int
i2c_repeated_start(device_t dev,u_char slave,int timeout)294 i2c_repeated_start(device_t dev, u_char slave, int timeout)
295 {
296 struct vf_i2c_softc *sc;
297 int error;
298 int reg;
299
300 sc = device_get_softc(dev);
301
302 vf_i2c_dbg(sc, "i2c repeated start\n");
303
304 mtx_lock(&sc->mutex);
305
306 if ((READ1(sc, I2C_IBSR) & IBSR_IBB) == 0) {
307 vf_i2c_dbg(sc, "cant i2c repeat start: bus is no longer busy\n");
308 mtx_unlock(&sc->mutex);
309 return (IIC_EBUSERR);
310 }
311
312 reg = READ1(sc, I2C_IBCR);
313 reg |= (IBCR_RSTA | IBCR_IBIE);
314 WRITE1(sc, I2C_IBCR, reg);
315
316 /* Write target address - LSB is R/W bit */
317 WRITE1(sc, I2C_IBDR, slave);
318
319 error = wait_for_icf(sc);
320
321 if (!tx_acked(sc)) {
322 mtx_unlock(&sc->mutex);
323 vf_i2c_dbg(sc, "cant i2c repeat start: missing ACK after slave address\n");
324 return (IIC_ENOACK);
325 }
326
327 mtx_unlock(&sc->mutex);
328
329 if (error != 0)
330 return (error);
331
332 return (IIC_NOERR);
333 }
334
335 static int
i2c_start(device_t dev,u_char slave,int timeout)336 i2c_start(device_t dev, u_char slave, int timeout)
337 {
338 struct vf_i2c_softc *sc;
339 int error;
340 int reg;
341
342 sc = device_get_softc(dev);
343
344 vf_i2c_dbg(sc, "i2c start\n");
345
346 mtx_lock(&sc->mutex);
347
348 error = wait_for_nibb(sc);
349
350 /* Reset controller if bus is still busy. */
351 if (error == IIC_ETIMEOUT) {
352 WRITE1(sc, I2C_IBCR, IBCR_MDIS);
353 DELAY(1000);
354 WRITE1(sc, I2C_IBCR, IBCR_NOACK);
355 error = wait_for_nibb(sc);
356 }
357
358 if (error != 0) {
359 mtx_unlock(&sc->mutex);
360 vf_i2c_dbg(sc, "cant i2c start: %i\n", error);
361 return (error);
362 }
363
364 /* Set start condition */
365 reg = (IBCR_MSSL | IBCR_NOACK | IBCR_IBIE | IBCR_TXRX);
366 WRITE1(sc, I2C_IBCR, reg);
367
368 WRITE1(sc, I2C_IBSR, IBSR_IBIF);
369
370 /* Write target address - LSB is R/W bit */
371 WRITE1(sc, I2C_IBDR, slave);
372
373 error = wait_for_icf(sc);
374 if (error != 0) {
375 mtx_unlock(&sc->mutex);
376 vf_i2c_dbg(sc, "cant i2c start: iif error\n");
377 return (error);
378 }
379 mtx_unlock(&sc->mutex);
380
381 if (!tx_acked(sc)) {
382 vf_i2c_dbg(sc, "cant i2c start: missing ACK after slave address\n");
383 return (IIC_ENOACK);
384 }
385
386 return (IIC_NOERR);
387 }
388
389 static int
i2c_stop(device_t dev)390 i2c_stop(device_t dev)
391 {
392 struct vf_i2c_softc *sc;
393
394 sc = device_get_softc(dev);
395
396 vf_i2c_dbg(sc, "i2c stop\n");
397
398 mtx_lock(&sc->mutex);
399
400 if ((READ1(sc, I2C_IBCR) & IBCR_MSSL) != 0)
401 WRITE1(sc, I2C_IBCR, IBCR_NOACK | IBCR_IBIE);
402
403 mtx_unlock(&sc->mutex);
404
405 return (IIC_NOERR);
406 }
407
408 static uint8_t
i2c_get_div_val(device_t dev)409 i2c_get_div_val(device_t dev)
410 {
411 struct vf_i2c_softc *sc;
412 uint8_t div_reg = DIV_REG_UNSET;
413
414 sc = device_get_softc(dev);
415
416 if (sc->freq == UINT32_MAX)
417 return div_reg;
418 #ifndef FDT
419 div_reg = vf610_div_table[nitems(vf610_div_table) - 1].reg_val;
420 #else
421 if (sc->hwtype == HW_MVF600)
422 div_reg = MVF600_DIV_REG;
423 else if (sc->freq == 0)
424 div_reg = vf610_div_table[nitems(vf610_div_table) - 1].reg_val;
425 else {
426 uint64_t clk_freq;
427 int error, i;
428
429 error = clk_get_freq(sc->clock, &clk_freq);
430 if (error != 0) {
431 device_printf(dev, "Could not get parent clock frequency. "
432 "Using default divider.\n");
433 div_reg = vf610_div_table[nitems(vf610_div_table) - 1].reg_val;
434 } else {
435
436 for (i = 0; i < nitems(vf610_div_table) - 1; i++)
437 if ((clk_freq / vf610_div_table[i].div) <= sc->freq)
438 break;
439 div_reg = vf610_div_table[i].reg_val;
440 }
441 }
442 #endif
443 vf_i2c_dbg(sc, "Writing 0x%02X to clock divider register\n", div_reg);
444 return div_reg;
445 }
446
447 static int
i2c_reset(device_t dev,u_char speed,u_char addr,u_char * oldadr)448 i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldadr)
449 {
450 struct vf_i2c_softc *sc;
451 uint8_t div_reg;
452
453 sc = device_get_softc(dev);
454 div_reg = i2c_get_div_val(dev);
455 vf_i2c_dbg(sc, "i2c reset\n");
456
457 mtx_lock(&sc->mutex);
458 WRITE1(sc, I2C_IBCR, IBCR_MDIS);
459
460 if(div_reg != DIV_REG_UNSET)
461 WRITE1(sc, I2C_IBFD, div_reg);
462
463 WRITE1(sc, I2C_IBCR, 0x0); /* Enable i2c */
464
465 mtx_unlock(&sc->mutex);
466
467 return (IIC_NOERR);
468 }
469
470 static int
i2c_read(device_t dev,char * buf,int len,int * read,int last,int delay)471 i2c_read(device_t dev, char *buf, int len, int *read, int last, int delay)
472 {
473 struct vf_i2c_softc *sc;
474 int error;
475
476 sc = device_get_softc(dev);
477
478 vf_i2c_dbg(sc, "i2c read\n");
479
480 *read = 0;
481
482 mtx_lock(&sc->mutex);
483
484 if (len) {
485 if (len == 1)
486 WRITE1(sc, I2C_IBCR, IBCR_IBIE | IBCR_MSSL | IBCR_NOACK);
487 else
488 WRITE1(sc, I2C_IBCR, IBCR_IBIE | IBCR_MSSL);
489
490 /* dummy read */
491 READ1(sc, I2C_IBDR);
492
493 while (*read < len) {
494 error = wait_for_icf(sc);
495 if (error != 0) {
496 mtx_unlock(&sc->mutex);
497 return (error);
498 }
499
500 if (last) {
501 if (*read == len - 2) {
502 /* NO ACK on last byte */
503 WRITE1(sc, I2C_IBCR, IBCR_IBIE | IBCR_MSSL | IBCR_NOACK);
504
505 } else if (*read == len - 1) {
506 /* Transfer done, remove master bit */
507 WRITE1(sc, I2C_IBCR, IBCR_IBIE | IBCR_NOACK);
508 }
509 }
510
511 *buf++ = READ1(sc, I2C_IBDR);
512 (*read)++;
513 }
514 }
515 mtx_unlock(&sc->mutex);
516
517 return (IIC_NOERR);
518 }
519
520 static int
i2c_write(device_t dev,const char * buf,int len,int * sent,int timeout)521 i2c_write(device_t dev, const char *buf, int len, int *sent, int timeout)
522 {
523 struct vf_i2c_softc *sc;
524 int error;
525
526 sc = device_get_softc(dev);
527
528 vf_i2c_dbg(sc, "i2c write\n");
529
530 *sent = 0;
531
532 mtx_lock(&sc->mutex);
533 while (*sent < len) {
534 WRITE1(sc, I2C_IBDR, *buf++);
535
536 error = wait_for_icf(sc);
537 if (error != 0) {
538 mtx_unlock(&sc->mutex);
539 return (error);
540 }
541
542 if (!tx_acked(sc) && (*sent = (len - 2)) ){
543 mtx_unlock(&sc->mutex);
544 vf_i2c_dbg(sc, "no ACK on %d write\n", *sent);
545 return (IIC_ENOACK);
546 }
547
548 (*sent)++;
549 }
550 mtx_unlock(&sc->mutex);
551 return (IIC_NOERR);
552 }
553
554 static device_method_t i2c_methods[] = {
555 /* Device interface */
556 DEVMETHOD(device_detach, i2c_detach),
557
558 /* Device interface */
559 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
560 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
561 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
562 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
563 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
564 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
565 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
566
567 /* iicbus interface */
568 DEVMETHOD(iicbus_callback, iicbus_null_callback),
569 DEVMETHOD(iicbus_repeated_start, i2c_repeated_start),
570 DEVMETHOD(iicbus_start, i2c_start),
571 DEVMETHOD(iicbus_stop, i2c_stop),
572 DEVMETHOD(iicbus_reset, i2c_reset),
573 DEVMETHOD(iicbus_read, i2c_read),
574 DEVMETHOD(iicbus_write, i2c_write),
575 DEVMETHOD(iicbus_transfer, iicbus_transfer_gen),
576 DEVMETHOD_END
577 };
578
579 driver_t vf_i2c_driver = {
580 "i2c",
581 i2c_methods,
582 sizeof(struct vf_i2c_softc),
583 };
584