xref: /illumos-gate/usr/src/uts/common/io/i40e/core/i40e_adminq_cmd.h (revision df36e06d12cbf655ddf22339ef8c39fa2b83ebf8)
1 /******************************************************************************
2 
3   Copyright (c) 2013-2018, Intel Corporation
4   All rights reserved.
5 
6   Redistribution and use in source and binary forms, with or without
7   modification, are permitted provided that the following conditions are met:
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9    1. Redistributions of source code must retain the above copyright notice,
10       this list of conditions and the following disclaimer.
11 
12    2. Redistributions in binary form must reproduce the above copyright
13       notice, this list of conditions and the following disclaimer in the
14       documentation and/or other materials provided with the distribution.
15 
16    3. Neither the name of the Intel Corporation nor the names of its
17       contributors may be used to endorse or promote products derived from
18       this software without specific prior written permission.
19 
20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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32 ******************************************************************************/
33 /*$FreeBSD$*/
34 
35 #ifndef _I40E_ADMINQ_CMD_H_
36 #define _I40E_ADMINQ_CMD_H_
37 
38 /* This header file defines the i40e Admin Queue commands and is shared between
39  * i40e Firmware and Software.
40  *
41  * This file needs to comply with the Linux Kernel coding style.
42  */
43 
44 
45 #define I40E_FW_API_VERSION_MAJOR	0x0001
46 #define I40E_FW_API_VERSION_MINOR_X722	0x000A
47 #define I40E_FW_API_VERSION_MINOR_X710	0x000A
48 
49 #define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \
50 					I40E_FW_API_VERSION_MINOR_X710 : \
51 					I40E_FW_API_VERSION_MINOR_X722)
52 
53 /* API version 1.7 implements additional link and PHY-specific APIs  */
54 #define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007
55 /* API version 1.9 for X722 implements additional link and PHY-specific APIs */
56 #define I40E_MINOR_VER_GET_LINK_INFO_X722 0x0009
57 /* API version 1.6 for X722 devices adds ability to stop FW LLDP agent */
58 #define I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722 0x0006
59 /* API version 1.10 for X722 devices adds ability to request FEC encoding */
60 #define I40E_MINOR_VER_FW_REQUEST_FEC_X722 0x000A
61 
62 struct i40e_aq_desc {
63 	__le16 flags;
64 	__le16 opcode;
65 	__le16 datalen;
66 	__le16 retval;
67 	__le32 cookie_high;
68 	__le32 cookie_low;
69 	union {
70 		struct {
71 			__le32 param0;
72 			__le32 param1;
73 			__le32 param2;
74 			__le32 param3;
75 		} internal;
76 		struct {
77 			__le32 param0;
78 			__le32 param1;
79 			__le32 addr_high;
80 			__le32 addr_low;
81 		} external;
82 		u8 raw[16];
83 	} params;
84 };
85 
86 /* Flags sub-structure
87  * |0  |1  |2  |3  |4  |5  |6  |7  |8  |9  |10 |11 |12 |13 |14 |15 |
88  * |DD |CMP|ERR|VFE| * *  RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
89  */
90 
91 /* command flags and offsets*/
92 #define I40E_AQ_FLAG_DD_SHIFT	0
93 #define I40E_AQ_FLAG_CMP_SHIFT	1
94 #define I40E_AQ_FLAG_ERR_SHIFT	2
95 #define I40E_AQ_FLAG_VFE_SHIFT	3
96 #define I40E_AQ_FLAG_LB_SHIFT	9
97 #define I40E_AQ_FLAG_RD_SHIFT	10
98 #define I40E_AQ_FLAG_VFC_SHIFT	11
99 #define I40E_AQ_FLAG_BUF_SHIFT	12
100 #define I40E_AQ_FLAG_SI_SHIFT	13
101 #define I40E_AQ_FLAG_EI_SHIFT	14
102 #define I40E_AQ_FLAG_FE_SHIFT	15
103 
104 #define I40E_AQ_FLAG_DD		(1 << I40E_AQ_FLAG_DD_SHIFT)  /* 0x1    */
105 #define I40E_AQ_FLAG_CMP	(1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2    */
106 #define I40E_AQ_FLAG_ERR	(1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4    */
107 #define I40E_AQ_FLAG_VFE	(1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8    */
108 #define I40E_AQ_FLAG_LB		(1 << I40E_AQ_FLAG_LB_SHIFT)  /* 0x200  */
109 #define I40E_AQ_FLAG_RD		(1 << I40E_AQ_FLAG_RD_SHIFT)  /* 0x400  */
110 #define I40E_AQ_FLAG_VFC	(1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800  */
111 #define I40E_AQ_FLAG_BUF	(1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
112 #define I40E_AQ_FLAG_SI		(1 << I40E_AQ_FLAG_SI_SHIFT)  /* 0x2000 */
113 #define I40E_AQ_FLAG_EI		(1 << I40E_AQ_FLAG_EI_SHIFT)  /* 0x4000 */
114 #define I40E_AQ_FLAG_FE		(1 << I40E_AQ_FLAG_FE_SHIFT)  /* 0x8000 */
115 
116 /* error codes */
117 enum i40e_admin_queue_err {
118 	I40E_AQ_RC_OK		= 0,  /* success */
119 	I40E_AQ_RC_EPERM	= 1,  /* Operation not permitted */
120 	I40E_AQ_RC_ENOENT	= 2,  /* No such element */
121 	I40E_AQ_RC_ESRCH	= 3,  /* Bad opcode */
122 	I40E_AQ_RC_EINTR	= 4,  /* operation interrupted */
123 	I40E_AQ_RC_EIO		= 5,  /* I/O error */
124 	I40E_AQ_RC_ENXIO	= 6,  /* No such resource */
125 	I40E_AQ_RC_E2BIG	= 7,  /* Arg too long */
126 	I40E_AQ_RC_EAGAIN	= 8,  /* Try again */
127 	I40E_AQ_RC_ENOMEM	= 9,  /* Out of memory */
128 	I40E_AQ_RC_EACCES	= 10, /* Permission denied */
129 	I40E_AQ_RC_EFAULT	= 11, /* Bad address */
130 	I40E_AQ_RC_EBUSY	= 12, /* Device or resource busy */
131 	I40E_AQ_RC_EEXIST	= 13, /* object already exists */
132 	I40E_AQ_RC_EINVAL	= 14, /* Invalid argument */
133 	I40E_AQ_RC_ENOTTY	= 15, /* Not a typewriter */
134 	I40E_AQ_RC_ENOSPC	= 16, /* No space left or alloc failure */
135 	I40E_AQ_RC_ENOSYS	= 17, /* Function not implemented */
136 	I40E_AQ_RC_ERANGE	= 18, /* Parameter out of range */
137 	I40E_AQ_RC_EFLUSHED	= 19, /* Cmd flushed due to prev cmd error */
138 	I40E_AQ_RC_BAD_ADDR	= 20, /* Descriptor contains a bad pointer */
139 	I40E_AQ_RC_EMODE	= 21, /* Op not allowed in current dev mode */
140 	I40E_AQ_RC_EFBIG	= 22, /* File too large */
141 };
142 
143 /* Admin Queue command opcodes */
144 enum i40e_admin_queue_opc {
145 	/* aq commands */
146 	i40e_aqc_opc_get_version	= 0x0001,
147 	i40e_aqc_opc_driver_version	= 0x0002,
148 	i40e_aqc_opc_queue_shutdown	= 0x0003,
149 	i40e_aqc_opc_set_pf_context	= 0x0004,
150 
151 	/* resource ownership */
152 	i40e_aqc_opc_request_resource	= 0x0008,
153 	i40e_aqc_opc_release_resource	= 0x0009,
154 
155 	i40e_aqc_opc_list_func_capabilities	= 0x000A,
156 	i40e_aqc_opc_list_dev_capabilities	= 0x000B,
157 
158 	/* Proxy commands */
159 	i40e_aqc_opc_set_proxy_config		= 0x0104,
160 	i40e_aqc_opc_set_ns_proxy_table_entry	= 0x0105,
161 
162 	/* LAA */
163 	i40e_aqc_opc_mac_address_read	= 0x0107,
164 	i40e_aqc_opc_mac_address_write	= 0x0108,
165 
166 	/* PXE */
167 	i40e_aqc_opc_clear_pxe_mode	= 0x0110,
168 
169 	/* WoL commands */
170 	i40e_aqc_opc_set_wol_filter	= 0x0120,
171 	i40e_aqc_opc_get_wake_reason	= 0x0121,
172 	i40e_aqc_opc_clear_all_wol_filters = 0x025E,
173 
174 	/* internal switch commands */
175 	i40e_aqc_opc_get_switch_config		= 0x0200,
176 	i40e_aqc_opc_add_statistics		= 0x0201,
177 	i40e_aqc_opc_remove_statistics		= 0x0202,
178 	i40e_aqc_opc_set_port_parameters	= 0x0203,
179 	i40e_aqc_opc_get_switch_resource_alloc	= 0x0204,
180 	i40e_aqc_opc_set_switch_config		= 0x0205,
181 	i40e_aqc_opc_rx_ctl_reg_read		= 0x0206,
182 	i40e_aqc_opc_rx_ctl_reg_write		= 0x0207,
183 
184 	i40e_aqc_opc_add_vsi			= 0x0210,
185 	i40e_aqc_opc_update_vsi_parameters	= 0x0211,
186 	i40e_aqc_opc_get_vsi_parameters		= 0x0212,
187 
188 	i40e_aqc_opc_add_pv			= 0x0220,
189 	i40e_aqc_opc_update_pv_parameters	= 0x0221,
190 	i40e_aqc_opc_get_pv_parameters		= 0x0222,
191 
192 	i40e_aqc_opc_add_veb			= 0x0230,
193 	i40e_aqc_opc_update_veb_parameters	= 0x0231,
194 	i40e_aqc_opc_get_veb_parameters		= 0x0232,
195 
196 	i40e_aqc_opc_delete_element		= 0x0243,
197 
198 	i40e_aqc_opc_add_macvlan		= 0x0250,
199 	i40e_aqc_opc_remove_macvlan		= 0x0251,
200 	i40e_aqc_opc_add_vlan			= 0x0252,
201 	i40e_aqc_opc_remove_vlan		= 0x0253,
202 	i40e_aqc_opc_set_vsi_promiscuous_modes	= 0x0254,
203 	i40e_aqc_opc_add_tag			= 0x0255,
204 	i40e_aqc_opc_remove_tag			= 0x0256,
205 	i40e_aqc_opc_add_multicast_etag		= 0x0257,
206 	i40e_aqc_opc_remove_multicast_etag	= 0x0258,
207 	i40e_aqc_opc_update_tag			= 0x0259,
208 	i40e_aqc_opc_add_control_packet_filter	= 0x025A,
209 	i40e_aqc_opc_remove_control_packet_filter	= 0x025B,
210 	i40e_aqc_opc_add_cloud_filters		= 0x025C,
211 	i40e_aqc_opc_remove_cloud_filters	= 0x025D,
212 	i40e_aqc_opc_clear_wol_switch_filters	= 0x025E,
213 	i40e_aqc_opc_replace_cloud_filters	= 0x025F,
214 
215 	i40e_aqc_opc_add_mirror_rule	= 0x0260,
216 	i40e_aqc_opc_delete_mirror_rule	= 0x0261,
217 
218 	/* DCB commands */
219 	i40e_aqc_opc_dcb_ignore_pfc	= 0x0301,
220 	i40e_aqc_opc_dcb_updated	= 0x0302,
221 	i40e_aqc_opc_set_dcb_parameters = 0x0303,
222 
223 	/* TX scheduler */
224 	i40e_aqc_opc_configure_vsi_bw_limit		= 0x0400,
225 	i40e_aqc_opc_configure_vsi_ets_sla_bw_limit	= 0x0406,
226 	i40e_aqc_opc_configure_vsi_tc_bw		= 0x0407,
227 	i40e_aqc_opc_query_vsi_bw_config		= 0x0408,
228 	i40e_aqc_opc_query_vsi_ets_sla_config		= 0x040A,
229 	i40e_aqc_opc_configure_switching_comp_bw_limit	= 0x0410,
230 
231 	i40e_aqc_opc_enable_switching_comp_ets			= 0x0413,
232 	i40e_aqc_opc_modify_switching_comp_ets			= 0x0414,
233 	i40e_aqc_opc_disable_switching_comp_ets			= 0x0415,
234 	i40e_aqc_opc_configure_switching_comp_ets_bw_limit	= 0x0416,
235 	i40e_aqc_opc_configure_switching_comp_bw_config		= 0x0417,
236 	i40e_aqc_opc_query_switching_comp_ets_config		= 0x0418,
237 	i40e_aqc_opc_query_port_ets_config			= 0x0419,
238 	i40e_aqc_opc_query_switching_comp_bw_config		= 0x041A,
239 	i40e_aqc_opc_suspend_port_tx				= 0x041B,
240 	i40e_aqc_opc_resume_port_tx				= 0x041C,
241 	i40e_aqc_opc_configure_partition_bw			= 0x041D,
242 	/* hmc */
243 	i40e_aqc_opc_query_hmc_resource_profile	= 0x0500,
244 	i40e_aqc_opc_set_hmc_resource_profile	= 0x0501,
245 
246 	/* phy commands*/
247 	i40e_aqc_opc_get_phy_abilities		= 0x0600,
248 	i40e_aqc_opc_set_phy_config		= 0x0601,
249 	i40e_aqc_opc_set_mac_config		= 0x0603,
250 	i40e_aqc_opc_set_link_restart_an	= 0x0605,
251 	i40e_aqc_opc_get_link_status		= 0x0607,
252 	i40e_aqc_opc_set_phy_int_mask		= 0x0613,
253 	i40e_aqc_opc_get_local_advt_reg		= 0x0614,
254 	i40e_aqc_opc_set_local_advt_reg		= 0x0615,
255 	i40e_aqc_opc_get_partner_advt		= 0x0616,
256 	i40e_aqc_opc_set_lb_modes		= 0x0618,
257 	i40e_aqc_opc_get_phy_wol_caps		= 0x0621,
258 	i40e_aqc_opc_set_phy_debug		= 0x0622,
259 	i40e_aqc_opc_upload_ext_phy_fm		= 0x0625,
260 	i40e_aqc_opc_run_phy_activity		= 0x0626,
261 	i40e_aqc_opc_set_phy_register		= 0x0628,
262 	i40e_aqc_opc_get_phy_register		= 0x0629,
263 
264 	/* NVM commands */
265 	i40e_aqc_opc_nvm_read			= 0x0701,
266 	i40e_aqc_opc_nvm_erase			= 0x0702,
267 	i40e_aqc_opc_nvm_update			= 0x0703,
268 	i40e_aqc_opc_nvm_config_read		= 0x0704,
269 	i40e_aqc_opc_nvm_config_write		= 0x0705,
270 	i40e_aqc_opc_nvm_progress		= 0x0706,
271 	i40e_aqc_opc_oem_post_update		= 0x0720,
272 	i40e_aqc_opc_thermal_sensor		= 0x0721,
273 
274 	/* virtualization commands */
275 	i40e_aqc_opc_send_msg_to_pf		= 0x0801,
276 	i40e_aqc_opc_send_msg_to_vf		= 0x0802,
277 	i40e_aqc_opc_send_msg_to_peer		= 0x0803,
278 
279 	/* alternate structure */
280 	i40e_aqc_opc_alternate_write		= 0x0900,
281 	i40e_aqc_opc_alternate_write_indirect	= 0x0901,
282 	i40e_aqc_opc_alternate_read		= 0x0902,
283 	i40e_aqc_opc_alternate_read_indirect	= 0x0903,
284 	i40e_aqc_opc_alternate_write_done	= 0x0904,
285 	i40e_aqc_opc_alternate_set_mode		= 0x0905,
286 	i40e_aqc_opc_alternate_clear_port	= 0x0906,
287 
288 	/* LLDP commands */
289 	i40e_aqc_opc_lldp_get_mib	= 0x0A00,
290 	i40e_aqc_opc_lldp_update_mib	= 0x0A01,
291 	i40e_aqc_opc_lldp_add_tlv	= 0x0A02,
292 	i40e_aqc_opc_lldp_update_tlv	= 0x0A03,
293 	i40e_aqc_opc_lldp_delete_tlv	= 0x0A04,
294 	i40e_aqc_opc_lldp_stop		= 0x0A05,
295 	i40e_aqc_opc_lldp_start		= 0x0A06,
296 	i40e_aqc_opc_get_cee_dcb_cfg	= 0x0A07,
297 	i40e_aqc_opc_lldp_set_local_mib	= 0x0A08,
298 	i40e_aqc_opc_lldp_stop_start_spec_agent	= 0x0A09,
299 	i40e_aqc_opc_lldp_restore		= 0x0A0A,
300 
301 	/* Tunnel commands */
302 	i40e_aqc_opc_add_udp_tunnel	= 0x0B00,
303 	i40e_aqc_opc_del_udp_tunnel	= 0x0B01,
304 	i40e_aqc_opc_set_rss_key	= 0x0B02,
305 	i40e_aqc_opc_set_rss_lut	= 0x0B03,
306 	i40e_aqc_opc_get_rss_key	= 0x0B04,
307 	i40e_aqc_opc_get_rss_lut	= 0x0B05,
308 
309 	/* Async Events */
310 	i40e_aqc_opc_event_lan_overflow		= 0x1001,
311 
312 	/* OEM commands */
313 	i40e_aqc_opc_oem_parameter_change	= 0xFE00,
314 	i40e_aqc_opc_oem_device_status_change	= 0xFE01,
315 	i40e_aqc_opc_oem_ocsd_initialize	= 0xFE02,
316 	i40e_aqc_opc_oem_ocbb_initialize	= 0xFE03,
317 
318 	/* debug commands */
319 	i40e_aqc_opc_debug_read_reg		= 0xFF03,
320 	i40e_aqc_opc_debug_write_reg		= 0xFF04,
321 	i40e_aqc_opc_debug_modify_reg		= 0xFF07,
322 	i40e_aqc_opc_debug_dump_internals	= 0xFF08,
323 };
324 
325 /* command structures and indirect data structures */
326 
327 /* Structure naming conventions:
328  * - no suffix for direct command descriptor structures
329  * - _data for indirect sent data
330  * - _resp for indirect return data (data which is both will use _data)
331  * - _completion for direct return data
332  * - _element_ for repeated elements (may also be _data or _resp)
333  *
334  * Command structures are expected to overlay the params.raw member of the basic
335  * descriptor, and as such cannot exceed 16 bytes in length.
336  */
337 
338 /* This macro is used to generate a compilation error if a structure
339  * is not exactly the correct length. It gives a divide by zero error if the
340  * structure is not of the correct size, otherwise it creates an enum that is
341  * never used.
342  */
343 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
344 	{ i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
345 
346 /* This macro is used extensively to ensure that command structures are 16
347  * bytes in length as they have to map to the raw array of that size.
348  */
349 #define I40E_CHECK_CMD_LENGTH(X)	I40E_CHECK_STRUCT_LEN(16, X)
350 
351 /* internal (0x00XX) commands */
352 
353 /* Get version (direct 0x0001) */
354 struct i40e_aqc_get_version {
355 	__le32 rom_ver;
356 	__le32 fw_build;
357 	__le16 fw_major;
358 	__le16 fw_minor;
359 	__le16 api_major;
360 	__le16 api_minor;
361 };
362 
363 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
364 
365 /* Send driver version (indirect 0x0002) */
366 struct i40e_aqc_driver_version {
367 	u8	driver_major_ver;
368 	u8	driver_minor_ver;
369 	u8	driver_build_ver;
370 	u8	driver_subbuild_ver;
371 	u8	reserved[4];
372 	__le32	address_high;
373 	__le32	address_low;
374 };
375 
376 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
377 
378 /* Queue Shutdown (direct 0x0003) */
379 struct i40e_aqc_queue_shutdown {
380 	__le32	driver_unloading;
381 #define I40E_AQ_DRIVER_UNLOADING	0x1
382 	u8	reserved[12];
383 };
384 
385 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
386 
387 /* Set PF context (0x0004, direct) */
388 struct i40e_aqc_set_pf_context {
389 	u8	pf_id;
390 	u8	reserved[15];
391 };
392 
393 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
394 
395 /* Request resource ownership (direct 0x0008)
396  * Release resource ownership (direct 0x0009)
397  */
398 #define I40E_AQ_RESOURCE_NVM			1
399 #define I40E_AQ_RESOURCE_SDP			2
400 #define I40E_AQ_RESOURCE_ACCESS_READ		1
401 #define I40E_AQ_RESOURCE_ACCESS_WRITE		2
402 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT	3000
403 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT	180000
404 
405 struct i40e_aqc_request_resource {
406 	__le16	resource_id;
407 	__le16	access_type;
408 	__le32	timeout;
409 	__le32	resource_number;
410 	u8	reserved[4];
411 };
412 
413 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
414 
415 /* Get function capabilities (indirect 0x000A)
416  * Get device capabilities (indirect 0x000B)
417  */
418 struct i40e_aqc_list_capabilites {
419 	u8 command_flags;
420 #define I40E_AQ_LIST_CAP_PF_INDEX_EN	1
421 	u8 pf_index;
422 	u8 reserved[2];
423 	__le32 count;
424 	__le32 addr_high;
425 	__le32 addr_low;
426 };
427 
428 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
429 
430 struct i40e_aqc_list_capabilities_element_resp {
431 	__le16	id;
432 	u8	major_rev;
433 	u8	minor_rev;
434 	__le32	number;
435 	__le32	logical_id;
436 	__le32	phys_id;
437 	u8	reserved[16];
438 };
439 
440 /* list of caps */
441 
442 #define I40E_AQ_CAP_ID_SWITCH_MODE	0x0001
443 #define I40E_AQ_CAP_ID_MNG_MODE		0x0002
444 #define I40E_AQ_CAP_ID_NPAR_ACTIVE	0x0003
445 #define I40E_AQ_CAP_ID_OS2BMC_CAP	0x0004
446 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID	0x0005
447 #define I40E_AQ_CAP_ID_ALTERNATE_RAM	0x0006
448 #define I40E_AQ_CAP_ID_WOL_AND_PROXY	0x0008
449 #define I40E_AQ_CAP_ID_SRIOV		0x0012
450 #define I40E_AQ_CAP_ID_VF		0x0013
451 #define I40E_AQ_CAP_ID_VMDQ		0x0014
452 #define I40E_AQ_CAP_ID_8021QBG		0x0015
453 #define I40E_AQ_CAP_ID_8021QBR		0x0016
454 #define I40E_AQ_CAP_ID_VSI		0x0017
455 #define I40E_AQ_CAP_ID_DCB		0x0018
456 #define I40E_AQ_CAP_ID_FCOE		0x0021
457 #define I40E_AQ_CAP_ID_ISCSI		0x0022
458 #define I40E_AQ_CAP_ID_RSS		0x0040
459 #define I40E_AQ_CAP_ID_RXQ		0x0041
460 #define I40E_AQ_CAP_ID_TXQ		0x0042
461 #define I40E_AQ_CAP_ID_MSIX		0x0043
462 #define I40E_AQ_CAP_ID_VF_MSIX		0x0044
463 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR	0x0045
464 #define I40E_AQ_CAP_ID_1588		0x0046
465 #define I40E_AQ_CAP_ID_IWARP		0x0051
466 #define I40E_AQ_CAP_ID_LED		0x0061
467 #define I40E_AQ_CAP_ID_SDP		0x0062
468 #define I40E_AQ_CAP_ID_MDIO		0x0063
469 #define I40E_AQ_CAP_ID_WSR_PROT		0x0064
470 #define I40E_AQ_CAP_ID_NVM_MGMT		0x0080
471 #define I40E_AQ_CAP_ID_FLEX10		0x00F1
472 #define I40E_AQ_CAP_ID_CEM		0x00F2
473 
474 /* Set CPPM Configuration (direct 0x0103) */
475 struct i40e_aqc_cppm_configuration {
476 	__le16	command_flags;
477 #define I40E_AQ_CPPM_EN_LTRC	0x0800
478 #define I40E_AQ_CPPM_EN_DMCTH	0x1000
479 #define I40E_AQ_CPPM_EN_DMCTLX	0x2000
480 #define I40E_AQ_CPPM_EN_HPTC	0x4000
481 #define I40E_AQ_CPPM_EN_DMARC	0x8000
482 	__le16	ttlx;
483 	__le32	dmacr;
484 	__le16	dmcth;
485 	u8	hptc;
486 	u8	reserved;
487 	__le32	pfltrc;
488 };
489 
490 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
491 
492 /* Set ARP Proxy command / response (indirect 0x0104) */
493 struct i40e_aqc_arp_proxy_data {
494 	__le16	command_flags;
495 #define I40E_AQ_ARP_INIT_IPV4	0x0800
496 #define I40E_AQ_ARP_UNSUP_CTL	0x1000
497 #define I40E_AQ_ARP_ENA		0x2000
498 #define I40E_AQ_ARP_ADD_IPV4	0x4000
499 #define I40E_AQ_ARP_DEL_IPV4	0x8000
500 	__le16	table_id;
501 	__le32	enabled_offloads;
502 #define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE	0x00000020
503 #define I40E_AQ_ARP_OFFLOAD_ENABLE		0x00000800
504 	__le32	ip_addr;
505 	u8	mac_addr[6];
506 	u8	reserved[2];
507 };
508 
509 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
510 
511 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
512 struct i40e_aqc_ns_proxy_data {
513 	__le16	table_idx_mac_addr_0;
514 	__le16	table_idx_mac_addr_1;
515 	__le16	table_idx_ipv6_0;
516 	__le16	table_idx_ipv6_1;
517 	__le16	control;
518 #define I40E_AQ_NS_PROXY_ADD_0		0x0001
519 #define I40E_AQ_NS_PROXY_DEL_0		0x0002
520 #define I40E_AQ_NS_PROXY_ADD_1		0x0004
521 #define I40E_AQ_NS_PROXY_DEL_1		0x0008
522 #define I40E_AQ_NS_PROXY_ADD_IPV6_0	0x0010
523 #define I40E_AQ_NS_PROXY_DEL_IPV6_0	0x0020
524 #define I40E_AQ_NS_PROXY_ADD_IPV6_1	0x0040
525 #define I40E_AQ_NS_PROXY_DEL_IPV6_1	0x0080
526 #define I40E_AQ_NS_PROXY_COMMAND_SEQ	0x0100
527 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL	0x0200
528 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL	0x0400
529 #define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE	0x0800
530 #define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE	0x1000
531 	u8	mac_addr_0[6];
532 	u8	mac_addr_1[6];
533 	u8	local_mac_addr[6];
534 	u8	ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
535 	u8	ipv6_addr_1[16];
536 };
537 
538 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
539 
540 /* Manage LAA Command (0x0106) - obsolete */
541 struct i40e_aqc_mng_laa {
542 	__le16	command_flags;
543 #define I40E_AQ_LAA_FLAG_WR	0x8000
544 	u8	reserved[2];
545 	__le32	sal;
546 	__le16	sah;
547 	u8	reserved2[6];
548 };
549 
550 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
551 
552 /* Manage MAC Address Read Command (indirect 0x0107) */
553 struct i40e_aqc_mac_address_read {
554 	__le16	command_flags;
555 #define I40E_AQC_LAN_ADDR_VALID		0x10
556 #define I40E_AQC_SAN_ADDR_VALID		0x20
557 #define I40E_AQC_PORT_ADDR_VALID	0x40
558 #define I40E_AQC_WOL_ADDR_VALID		0x80
559 #define I40E_AQC_MC_MAG_EN_VALID	0x100
560 #define I40E_AQC_WOL_PRESERVE_STATUS	0x200
561 #define I40E_AQC_ADDR_VALID_MASK	0x3F0
562 	u8	reserved[6];
563 	__le32	addr_high;
564 	__le32	addr_low;
565 };
566 
567 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
568 
569 struct i40e_aqc_mac_address_read_data {
570 	u8 pf_lan_mac[6];
571 	u8 pf_san_mac[6];
572 	u8 port_mac[6];
573 	u8 pf_wol_mac[6];
574 };
575 
576 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
577 
578 /* Manage MAC Address Write Command (0x0108) */
579 struct i40e_aqc_mac_address_write {
580 	__le16	command_flags;
581 #define I40E_AQC_MC_MAG_EN		0x0100
582 #define I40E_AQC_WOL_PRESERVE_ON_PFR	0x0200
583 #define I40E_AQC_WRITE_TYPE_LAA_ONLY	0x0000
584 #define I40E_AQC_WRITE_TYPE_LAA_WOL	0x4000
585 #define I40E_AQC_WRITE_TYPE_PORT	0x8000
586 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG	0xC000
587 #define I40E_AQC_WRITE_TYPE_MASK	0xC000
588 
589 	__le16	mac_sah;
590 	__le32	mac_sal;
591 	u8	reserved[8];
592 };
593 
594 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
595 
596 /* PXE commands (0x011x) */
597 
598 /* Clear PXE Command and response  (direct 0x0110) */
599 struct i40e_aqc_clear_pxe {
600 	u8	rx_cnt;
601 	u8	reserved[15];
602 };
603 
604 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
605 
606 /* Set WoL Filter (0x0120) */
607 
608 struct i40e_aqc_set_wol_filter {
609 	__le16 filter_index;
610 #define I40E_AQC_MAX_NUM_WOL_FILTERS	8
611 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT	15
612 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK	(0x1 << \
613 		I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT)
614 
615 #define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT		0
616 #define I40E_AQC_SET_WOL_FILTER_INDEX_MASK	(0x7 << \
617 		I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT)
618 	__le16 cmd_flags;
619 #define I40E_AQC_SET_WOL_FILTER				0x8000
620 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL		0x4000
621 #define I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR	0x2000
622 #define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR		0
623 #define I40E_AQC_SET_WOL_FILTER_ACTION_SET		1
624 	__le16 valid_flags;
625 #define I40E_AQC_SET_WOL_FILTER_ACTION_VALID		0x8000
626 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID	0x4000
627 	u8 reserved[2];
628 	__le32	address_high;
629 	__le32	address_low;
630 };
631 
632 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter);
633 
634 struct i40e_aqc_set_wol_filter_data {
635 	u8 filter[128];
636 	u8 mask[16];
637 };
638 
639 I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data);
640 
641 /* Get Wake Reason (0x0121) */
642 
643 struct i40e_aqc_get_wake_reason_completion {
644 	u8 reserved_1[2];
645 	__le16 wake_reason;
646 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT	0
647 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \
648 		I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT)
649 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT	8
650 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK	(0xFF << \
651 		I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT)
652 	u8 reserved_2[12];
653 };
654 
655 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion);
656 
657 /* Switch configuration commands (0x02xx) */
658 
659 /* Used by many indirect commands that only pass an seid and a buffer in the
660  * command
661  */
662 struct i40e_aqc_switch_seid {
663 	__le16	seid;
664 	u8	reserved[6];
665 	__le32	addr_high;
666 	__le32	addr_low;
667 };
668 
669 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
670 
671 /* Get Switch Configuration command (indirect 0x0200)
672  * uses i40e_aqc_switch_seid for the descriptor
673  */
674 struct i40e_aqc_get_switch_config_header_resp {
675 	__le16	num_reported;
676 	__le16	num_total;
677 	u8	reserved[12];
678 };
679 
680 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
681 
682 struct i40e_aqc_switch_config_element_resp {
683 	u8	element_type;
684 #define I40E_AQ_SW_ELEM_TYPE_MAC	1
685 #define I40E_AQ_SW_ELEM_TYPE_PF		2
686 #define I40E_AQ_SW_ELEM_TYPE_VF		3
687 #define I40E_AQ_SW_ELEM_TYPE_EMP	4
688 #define I40E_AQ_SW_ELEM_TYPE_BMC	5
689 #define I40E_AQ_SW_ELEM_TYPE_PV		16
690 #define I40E_AQ_SW_ELEM_TYPE_VEB	17
691 #define I40E_AQ_SW_ELEM_TYPE_PA		18
692 #define I40E_AQ_SW_ELEM_TYPE_VSI	19
693 	u8	revision;
694 #define I40E_AQ_SW_ELEM_REV_1		1
695 	__le16	seid;
696 	__le16	uplink_seid;
697 	__le16	downlink_seid;
698 	u8	reserved[3];
699 	u8	connection_type;
700 #define I40E_AQ_CONN_TYPE_REGULAR	0x1
701 #define I40E_AQ_CONN_TYPE_DEFAULT	0x2
702 #define I40E_AQ_CONN_TYPE_CASCADED	0x3
703 	__le16	scheduler_id;
704 	__le16	element_info;
705 };
706 
707 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
708 
709 /* Get Switch Configuration (indirect 0x0200)
710  *    an array of elements are returned in the response buffer
711  *    the first in the array is the header, remainder are elements
712  */
713 struct i40e_aqc_get_switch_config_resp {
714 	struct i40e_aqc_get_switch_config_header_resp	header;
715 	struct i40e_aqc_switch_config_element_resp	element[1];
716 };
717 
718 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
719 
720 /* Add Statistics (direct 0x0201)
721  * Remove Statistics (direct 0x0202)
722  */
723 struct i40e_aqc_add_remove_statistics {
724 	__le16	seid;
725 	__le16	vlan;
726 	__le16	stat_index;
727 	u8	reserved[10];
728 };
729 
730 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
731 
732 /* Set Port Parameters command (direct 0x0203) */
733 struct i40e_aqc_set_port_parameters {
734 	__le16	command_flags;
735 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS	1
736 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS	2 /* must set! */
737 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA	4
738 	__le16	bad_frame_vsi;
739 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT	0x0
740 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK	0x3FF
741 	__le16	default_seid;        /* reserved for command */
742 	u8	reserved[10];
743 };
744 
745 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
746 
747 /* Get Switch Resource Allocation (indirect 0x0204) */
748 struct i40e_aqc_get_switch_resource_alloc {
749 	u8	num_entries;         /* reserved for command */
750 	u8	reserved[7];
751 	__le32	addr_high;
752 	__le32	addr_low;
753 };
754 
755 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
756 
757 /* expect an array of these structs in the response buffer */
758 struct i40e_aqc_switch_resource_alloc_element_resp {
759 	u8	resource_type;
760 #define I40E_AQ_RESOURCE_TYPE_VEB		0x0
761 #define I40E_AQ_RESOURCE_TYPE_VSI		0x1
762 #define I40E_AQ_RESOURCE_TYPE_MACADDR		0x2
763 #define I40E_AQ_RESOURCE_TYPE_STAG		0x3
764 #define I40E_AQ_RESOURCE_TYPE_ETAG		0x4
765 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH	0x5
766 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH	0x6
767 #define I40E_AQ_RESOURCE_TYPE_VLAN		0x7
768 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY	0x8
769 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY	0x9
770 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL	0xA
771 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE	0xB
772 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS	0xC
773 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS	0xD
774 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS	0xF
775 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS	0x10
776 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS	0x11
777 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS		0x12
778 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS	0x13
779 	u8	reserved1;
780 	__le16	guaranteed;
781 	__le16	total;
782 	__le16	used;
783 	__le16	total_unalloced;
784 	u8	reserved2[6];
785 };
786 
787 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
788 
789 /* Set Switch Configuration (direct 0x0205) */
790 struct i40e_aqc_set_switch_config {
791 	__le16	flags;
792 /* flags used for both fields below */
793 #define I40E_AQ_SET_SWITCH_CFG_PROMISC		0x0001
794 #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER	0x0002
795 #define I40E_AQ_SET_SWITCH_CFG_HW_ATR_EVICT	0x0004
796 	__le16	valid_flags;
797 	/* The ethertype in switch_tag is dropped on ingress and used
798 	 * internally by the switch. Set this to zero for the default
799 	 * of 0x88a8 (802.1ad). Should be zero for firmware API
800 	 * versions lower than 1.7.
801 	 */
802 	__le16	switch_tag;
803 	/* The ethertypes in first_tag and second_tag are used to
804 	 * match the outer and inner VLAN tags (respectively) when HW
805 	 * double VLAN tagging is enabled via the set port parameters
806 	 * AQ command. Otherwise these are both ignored. Set them to
807 	 * zero for their defaults of 0x8100 (802.1Q). Should be zero
808 	 * for firmware API versions lower than 1.7.
809 	 */
810 	__le16	first_tag;
811 	__le16	second_tag;
812 	/* Next byte is split into following:
813 	 * Bit 7    : 0 : No action, 1: Switch to mode defined by bits 6:0
814 	 * Bit 6    : 0 : Destination Port, 1: source port
815 	 * Bit 5..4 : L4 type
816 	 * 0: rsvd
817 	 * 1: TCP
818 	 * 2: UDP
819 	 * 3: Both TCP and UDP
820 	 * Bits 3:0 Mode
821 	 * 0: default mode
822 	 * 1: L4 port only mode
823 	 * 2: non-tunneled mode
824 	 * 3: tunneled mode
825 	 */
826 #define I40E_AQ_SET_SWITCH_BIT7_VALID		0x80
827 
828 #define I40E_AQ_SET_SWITCH_L4_SRC_PORT		0x40
829 
830 #define I40E_AQ_SET_SWITCH_L4_TYPE_RSVD		0x00
831 #define I40E_AQ_SET_SWITCH_L4_TYPE_TCP		0x10
832 #define I40E_AQ_SET_SWITCH_L4_TYPE_UDP		0x20
833 #define I40E_AQ_SET_SWITCH_L4_TYPE_BOTH		0x30
834 
835 #define I40E_AQ_SET_SWITCH_MODE_DEFAULT		0x00
836 #define I40E_AQ_SET_SWITCH_MODE_L4_PORT		0x01
837 #define I40E_AQ_SET_SWITCH_MODE_NON_TUNNEL	0x02
838 #define I40E_AQ_SET_SWITCH_MODE_TUNNEL		0x03
839 	u8	mode;
840 	u8	rsvd5[5];
841 };
842 
843 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config);
844 
845 /* Read Receive control registers  (direct 0x0206)
846  * Write Receive control registers (direct 0x0207)
847  *     used for accessing Rx control registers that can be
848  *     slow and need special handling when under high Rx load
849  */
850 struct i40e_aqc_rx_ctl_reg_read_write {
851 	__le32 reserved1;
852 	__le32 address;
853 	__le32 reserved2;
854 	__le32 value;
855 };
856 
857 I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write);
858 
859 /* Add VSI (indirect 0x0210)
860  *    this indirect command uses struct i40e_aqc_vsi_properties_data
861  *    as the indirect buffer (128 bytes)
862  *
863  * Update VSI (indirect 0x211)
864  *     uses the same data structure as Add VSI
865  *
866  * Get VSI (indirect 0x0212)
867  *     uses the same completion and data structure as Add VSI
868  */
869 struct i40e_aqc_add_get_update_vsi {
870 	__le16	uplink_seid;
871 	u8	connection_type;
872 #define I40E_AQ_VSI_CONN_TYPE_NORMAL	0x1
873 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT	0x2
874 #define I40E_AQ_VSI_CONN_TYPE_CASCADED	0x3
875 	u8	reserved1;
876 	u8	vf_id;
877 	u8	reserved2;
878 	__le16	vsi_flags;
879 #define I40E_AQ_VSI_TYPE_SHIFT		0x0
880 #define I40E_AQ_VSI_TYPE_MASK		(0x3 << I40E_AQ_VSI_TYPE_SHIFT)
881 #define I40E_AQ_VSI_TYPE_VF		0x0
882 #define I40E_AQ_VSI_TYPE_VMDQ2		0x1
883 #define I40E_AQ_VSI_TYPE_PF		0x2
884 #define I40E_AQ_VSI_TYPE_EMP_MNG	0x3
885 #define I40E_AQ_VSI_FLAG_CASCADED_PV	0x4
886 	__le32	addr_high;
887 	__le32	addr_low;
888 };
889 
890 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
891 
892 struct i40e_aqc_add_get_update_vsi_completion {
893 	__le16 seid;
894 	__le16 vsi_number;
895 	__le16 vsi_used;
896 	__le16 vsi_free;
897 	__le32 addr_high;
898 	__le32 addr_low;
899 };
900 
901 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
902 
903 struct i40e_aqc_vsi_properties_data {
904 	/* first 96 byte are written by SW */
905 	__le16	valid_sections;
906 #define I40E_AQ_VSI_PROP_SWITCH_VALID		0x0001
907 #define I40E_AQ_VSI_PROP_SECURITY_VALID		0x0002
908 #define I40E_AQ_VSI_PROP_VLAN_VALID		0x0004
909 #define I40E_AQ_VSI_PROP_CAS_PV_VALID		0x0008
910 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID	0x0010
911 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID	0x0020
912 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID	0x0040
913 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID	0x0080
914 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID		0x0100
915 #define I40E_AQ_VSI_PROP_SCHED_VALID		0x0200
916 	/* switch section */
917 	__le16	switch_id; /* 12bit id combined with flags below */
918 #define I40E_AQ_VSI_SW_ID_SHIFT		0x0000
919 #define I40E_AQ_VSI_SW_ID_MASK		(0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
920 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG	0x1000
921 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB	0x2000
922 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB	0x4000
923 	u8	sw_reserved[2];
924 	/* security section */
925 	u8	sec_flags;
926 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD	0x01
927 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK	0x02
928 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK	0x04
929 	u8	sec_reserved;
930 	/* VLAN section */
931 	__le16	pvid; /* VLANS include priority bits */
932 	__le16	fcoe_pvid;
933 	u8	port_vlan_flags;
934 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT	0x00
935 #define I40E_AQ_VSI_PVLAN_MODE_MASK	(0x03 << \
936 					 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
937 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED	0x01
938 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED	0x02
939 #define I40E_AQ_VSI_PVLAN_MODE_ALL	0x03
940 #define I40E_AQ_VSI_PVLAN_INSERT_PVID	0x04
941 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT	0x03
942 #define I40E_AQ_VSI_PVLAN_EMOD_MASK	(0x3 << \
943 					 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
944 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH	0x0
945 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP	0x08
946 #define I40E_AQ_VSI_PVLAN_EMOD_STR	0x10
947 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING	0x18
948 	u8	pvlan_reserved[3];
949 	/* ingress egress up sections */
950 	__le32	ingress_table; /* bitmap, 3 bits per up */
951 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT	0
952 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK	(0x7 << \
953 					 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
954 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT	3
955 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK	(0x7 << \
956 					 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
957 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT	6
958 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK	(0x7 << \
959 					 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
960 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT	9
961 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK	(0x7 << \
962 					 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
963 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT	12
964 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK	(0x7 << \
965 					 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
966 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT	15
967 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK	(0x7 << \
968 					 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
969 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT	18
970 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK	(0x7 << \
971 					 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
972 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT	21
973 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK	(0x7 << \
974 					 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
975 	__le32	egress_table;   /* same defines as for ingress table */
976 	/* cascaded PV section */
977 	__le16	cas_pv_tag;
978 	u8	cas_pv_flags;
979 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT		0x00
980 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK		(0x03 << \
981 						 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
982 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE		0x00
983 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE		0x01
984 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY		0x02
985 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG		0x10
986 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE		0x20
987 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG	0x40
988 	u8	cas_pv_reserved;
989 	/* queue mapping section */
990 	__le16	mapping_flags;
991 #define I40E_AQ_VSI_QUE_MAP_CONTIG	0x0
992 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG	0x1
993 	__le16	queue_mapping[16];
994 #define I40E_AQ_VSI_QUEUE_SHIFT		0x0
995 #define I40E_AQ_VSI_QUEUE_MASK		(0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
996 	__le16	tc_mapping[8];
997 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT	0
998 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK	(0x1FF << \
999 					 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
1000 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT	9
1001 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK	(0x7 << \
1002 					 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
1003 	/* queueing option section */
1004 	u8	queueing_opt_flags;
1005 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA	0x04
1006 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA	0x08
1007 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA	0x10
1008 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA	0x20
1009 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF	0x00
1010 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI	0x40
1011 	u8	queueing_opt_reserved[3];
1012 	/* scheduler section */
1013 	u8	up_enable_bits;
1014 	u8	sched_reserved;
1015 	/* outer up section */
1016 	__le32	outer_up_table; /* same structure and defines as ingress tbl */
1017 	u8	cmd_reserved[8];
1018 	/* last 32 bytes are written by FW */
1019 	__le16	qs_handle[8];
1020 #define I40E_AQ_VSI_QS_HANDLE_INVALID	0xFFFF
1021 	__le16	stat_counter_idx;
1022 	__le16	sched_id;
1023 	u8	resp_reserved[12];
1024 };
1025 
1026 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
1027 
1028 /* Add Port Virtualizer (direct 0x0220)
1029  * also used for update PV (direct 0x0221) but only flags are used
1030  * (IS_CTRL_PORT only works on add PV)
1031  */
1032 struct i40e_aqc_add_update_pv {
1033 	__le16	command_flags;
1034 #define I40E_AQC_PV_FLAG_PV_TYPE		0x1
1035 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN	0x2
1036 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN	0x4
1037 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT		0x8
1038 	__le16	uplink_seid;
1039 	__le16	connected_seid;
1040 	u8	reserved[10];
1041 };
1042 
1043 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
1044 
1045 struct i40e_aqc_add_update_pv_completion {
1046 	/* reserved for update; for add also encodes error if rc == ENOSPC */
1047 	__le16	pv_seid;
1048 #define I40E_AQC_PV_ERR_FLAG_NO_PV	0x1
1049 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED	0x2
1050 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER	0x4
1051 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY	0x8
1052 	u8	reserved[14];
1053 };
1054 
1055 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
1056 
1057 /* Get PV Params (direct 0x0222)
1058  * uses i40e_aqc_switch_seid for the descriptor
1059  */
1060 
1061 struct i40e_aqc_get_pv_params_completion {
1062 	__le16	seid;
1063 	__le16	default_stag;
1064 	__le16	pv_flags; /* same flags as add_pv */
1065 #define I40E_AQC_GET_PV_PV_TYPE			0x1
1066 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG	0x2
1067 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG	0x4
1068 	u8	reserved[8];
1069 	__le16	default_port_seid;
1070 };
1071 
1072 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
1073 
1074 /* Add VEB (direct 0x0230) */
1075 struct i40e_aqc_add_veb {
1076 	__le16	uplink_seid;
1077 	__le16	downlink_seid;
1078 	__le16	veb_flags;
1079 #define I40E_AQC_ADD_VEB_FLOATING		0x1
1080 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT	1
1081 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK		(0x3 << \
1082 					I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
1083 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT	0x2
1084 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA		0x4
1085 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER	0x8     /* deprecated */
1086 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS	0x10
1087 	u8	enable_tcs;
1088 	u8	reserved[9];
1089 };
1090 
1091 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
1092 
1093 struct i40e_aqc_add_veb_completion {
1094 	u8	reserved[6];
1095 	__le16	switch_seid;
1096 	/* also encodes error if rc == ENOSPC; codes are the same as add_pv */
1097 	__le16	veb_seid;
1098 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB		0x1
1099 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED		0x2
1100 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER	0x4
1101 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY		0x8
1102 	__le16	statistic_index;
1103 	__le16	vebs_used;
1104 	__le16	vebs_free;
1105 };
1106 
1107 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
1108 
1109 /* Get VEB Parameters (direct 0x0232)
1110  * uses i40e_aqc_switch_seid for the descriptor
1111  */
1112 struct i40e_aqc_get_veb_parameters_completion {
1113 	__le16	seid;
1114 	__le16	switch_id;
1115 	__le16	veb_flags; /* only the first/last flags from 0x0230 is valid */
1116 	__le16	statistic_index;
1117 	__le16	vebs_used;
1118 	__le16	vebs_free;
1119 	u8	reserved[4];
1120 };
1121 
1122 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
1123 
1124 /* Delete Element (direct 0x0243)
1125  * uses the generic i40e_aqc_switch_seid
1126  */
1127 
1128 /* Add MAC-VLAN (indirect 0x0250) */
1129 
1130 /* used for the command for most vlan commands */
1131 struct i40e_aqc_macvlan {
1132 	__le16	num_addresses;
1133 	__le16	seid[3];
1134 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT	0
1135 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK	(0x3FF << \
1136 					I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1137 #define I40E_AQC_MACVLAN_CMD_SEID_VALID		0x8000
1138 	__le32	addr_high;
1139 	__le32	addr_low;
1140 };
1141 
1142 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
1143 
1144 /* indirect data for command and response */
1145 struct i40e_aqc_add_macvlan_element_data {
1146 	u8	mac_addr[6];
1147 	__le16	vlan_tag;
1148 	__le16	flags;
1149 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH	0x0001
1150 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH		0x0002
1151 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN	0x0004
1152 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE		0x0008
1153 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC	0x0010
1154 	__le16	queue_number;
1155 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT	0
1156 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK		(0x7FF << \
1157 					I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1158 	/* response section */
1159 	u8	match_method;
1160 #define I40E_AQC_MM_PERFECT_MATCH	0x01
1161 #define I40E_AQC_MM_HASH_MATCH		0x02
1162 #define I40E_AQC_MM_ERR_NO_RES		0xFF
1163 	u8	reserved1[3];
1164 };
1165 
1166 struct i40e_aqc_add_remove_macvlan_completion {
1167 	__le16 perfect_mac_used;
1168 	__le16 perfect_mac_free;
1169 	__le16 unicast_hash_free;
1170 	__le16 multicast_hash_free;
1171 	__le32 addr_high;
1172 	__le32 addr_low;
1173 };
1174 
1175 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
1176 
1177 /* Remove MAC-VLAN (indirect 0x0251)
1178  * uses i40e_aqc_macvlan for the descriptor
1179  * data points to an array of num_addresses of elements
1180  */
1181 
1182 struct i40e_aqc_remove_macvlan_element_data {
1183 	u8	mac_addr[6];
1184 	__le16	vlan_tag;
1185 	u8	flags;
1186 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH	0x01
1187 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH		0x02
1188 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN	0x08
1189 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS		0x10
1190 	u8	reserved[3];
1191 	/* reply section */
1192 	u8	error_code;
1193 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS		0x0
1194 #define I40E_AQC_REMOVE_MACVLAN_FAIL		0xFF
1195 	u8	reply_reserved[3];
1196 };
1197 
1198 /* Add VLAN (indirect 0x0252)
1199  * Remove VLAN (indirect 0x0253)
1200  * use the generic i40e_aqc_macvlan for the command
1201  */
1202 struct i40e_aqc_add_remove_vlan_element_data {
1203 	__le16	vlan_tag;
1204 	u8	vlan_flags;
1205 /* flags for add VLAN */
1206 #define I40E_AQC_ADD_VLAN_LOCAL			0x1
1207 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT		1
1208 #define I40E_AQC_ADD_PVLAN_TYPE_MASK	(0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1209 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR		0x0
1210 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY		0x2
1211 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY	0x4
1212 #define I40E_AQC_VLAN_PTYPE_SHIFT		3
1213 #define I40E_AQC_VLAN_PTYPE_MASK	(0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1214 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI		0x0
1215 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI		0x8
1216 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI	0x10
1217 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI	0x18
1218 /* flags for remove VLAN */
1219 #define I40E_AQC_REMOVE_VLAN_ALL	0x1
1220 	u8	reserved;
1221 	u8	result;
1222 /* flags for add VLAN */
1223 #define I40E_AQC_ADD_VLAN_SUCCESS	0x0
1224 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST	0xFE
1225 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE	0xFF
1226 /* flags for remove VLAN */
1227 #define I40E_AQC_REMOVE_VLAN_SUCCESS	0x0
1228 #define I40E_AQC_REMOVE_VLAN_FAIL	0xFF
1229 	u8	reserved1[3];
1230 };
1231 
1232 struct i40e_aqc_add_remove_vlan_completion {
1233 	u8	reserved[4];
1234 	__le16	vlans_used;
1235 	__le16	vlans_free;
1236 	__le32	addr_high;
1237 	__le32	addr_low;
1238 };
1239 
1240 /* Set VSI Promiscuous Modes (direct 0x0254) */
1241 struct i40e_aqc_set_vsi_promiscuous_modes {
1242 	__le16	promiscuous_flags;
1243 	__le16	valid_flags;
1244 /* flags used for both fields above */
1245 #define I40E_AQC_SET_VSI_PROMISC_UNICAST	0x01
1246 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST	0x02
1247 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST	0x04
1248 #define I40E_AQC_SET_VSI_DEFAULT		0x08
1249 #define I40E_AQC_SET_VSI_PROMISC_VLAN		0x10
1250 #define I40E_AQC_SET_VSI_PROMISC_TX		0x8000
1251 	__le16	seid;
1252 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK		0x3FF
1253 	__le16	vlan_tag;
1254 #define I40E_AQC_SET_VSI_VLAN_MASK		0x0FFF
1255 #define I40E_AQC_SET_VSI_VLAN_VALID		0x8000
1256 	u8	reserved[8];
1257 };
1258 
1259 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1260 
1261 /* Add S/E-tag command (direct 0x0255)
1262  * Uses generic i40e_aqc_add_remove_tag_completion for completion
1263  */
1264 struct i40e_aqc_add_tag {
1265 	__le16	flags;
1266 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE		0x0001
1267 	__le16	seid;
1268 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT	0
1269 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK	(0x3FF << \
1270 					I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1271 	__le16	tag;
1272 	__le16	queue_number;
1273 	u8	reserved[8];
1274 };
1275 
1276 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1277 
1278 struct i40e_aqc_add_remove_tag_completion {
1279 	u8	reserved[12];
1280 	__le16	tags_used;
1281 	__le16	tags_free;
1282 };
1283 
1284 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1285 
1286 /* Remove S/E-tag command (direct 0x0256)
1287  * Uses generic i40e_aqc_add_remove_tag_completion for completion
1288  */
1289 struct i40e_aqc_remove_tag {
1290 	__le16	seid;
1291 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT	0
1292 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK	(0x3FF << \
1293 					I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1294 	__le16	tag;
1295 	u8	reserved[12];
1296 };
1297 
1298 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1299 
1300 /* Add multicast E-Tag (direct 0x0257)
1301  * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1302  * and no external data
1303  */
1304 struct i40e_aqc_add_remove_mcast_etag {
1305 	__le16	pv_seid;
1306 	__le16	etag;
1307 	u8	num_unicast_etags;
1308 	u8	reserved[3];
1309 	__le32	addr_high;          /* address of array of 2-byte s-tags */
1310 	__le32	addr_low;
1311 };
1312 
1313 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1314 
1315 struct i40e_aqc_add_remove_mcast_etag_completion {
1316 	u8	reserved[4];
1317 	__le16	mcast_etags_used;
1318 	__le16	mcast_etags_free;
1319 	__le32	addr_high;
1320 	__le32	addr_low;
1321 
1322 };
1323 
1324 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1325 
1326 /* Update S/E-Tag (direct 0x0259) */
1327 struct i40e_aqc_update_tag {
1328 	__le16	seid;
1329 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT	0
1330 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK	(0x3FF << \
1331 					I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1332 	__le16	old_tag;
1333 	__le16	new_tag;
1334 	u8	reserved[10];
1335 };
1336 
1337 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1338 
1339 struct i40e_aqc_update_tag_completion {
1340 	u8	reserved[12];
1341 	__le16	tags_used;
1342 	__le16	tags_free;
1343 };
1344 
1345 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1346 
1347 /* Add Control Packet filter (direct 0x025A)
1348  * Remove Control Packet filter (direct 0x025B)
1349  * uses the i40e_aqc_add_oveb_cloud,
1350  * and the generic direct completion structure
1351  */
1352 struct i40e_aqc_add_remove_control_packet_filter {
1353 	u8	mac[6];
1354 	__le16	etype;
1355 	__le16	flags;
1356 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC	0x0001
1357 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP		0x0002
1358 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE	0x0004
1359 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX		0x0008
1360 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX		0x0000
1361 	__le16	seid;
1362 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT	0
1363 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK	(0x3FF << \
1364 				I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1365 	__le16	queue;
1366 	u8	reserved[2];
1367 };
1368 
1369 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1370 
1371 struct i40e_aqc_add_remove_control_packet_filter_completion {
1372 	__le16	mac_etype_used;
1373 	__le16	etype_used;
1374 	__le16	mac_etype_free;
1375 	__le16	etype_free;
1376 	u8	reserved[8];
1377 };
1378 
1379 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1380 
1381 /* Add Cloud filters (indirect 0x025C)
1382  * Remove Cloud filters (indirect 0x025D)
1383  * uses the i40e_aqc_add_remove_cloud_filters,
1384  * and the generic indirect completion structure
1385  */
1386 struct i40e_aqc_add_remove_cloud_filters {
1387 	u8	num_filters;
1388 	u8	reserved;
1389 	__le16	seid;
1390 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT	0
1391 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK	(0x3FF << \
1392 					I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1393 	u8	big_buffer_flag;
1394 #define I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER	1
1395 #define I40E_AQC_ADD_CLOUD_CMD_BB		1
1396 	u8	reserved2[3];
1397 	__le32	addr_high;
1398 	__le32	addr_low;
1399 };
1400 
1401 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1402 
1403 struct i40e_aqc_cloud_filters_element_data {
1404 	u8	outer_mac[6];
1405 	u8	inner_mac[6];
1406 	__le16	inner_vlan;
1407 	union {
1408 		struct {
1409 			u8 reserved[12];
1410 			u8 data[4];
1411 		} v4;
1412 		struct {
1413 			u8 data[16];
1414 		} v6;
1415 		struct {
1416 			__le16 data[8];
1417 		} raw_v6;
1418 	} ipaddr;
1419 	__le16	flags;
1420 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT			0
1421 #define I40E_AQC_ADD_CLOUD_FILTER_MASK	(0x3F << \
1422 					I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1423 /* 0x0000 reserved */
1424 /* 0x0001 reserved */
1425 /* 0x0002 reserved */
1426 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN		0x0003
1427 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID	0x0004
1428 /* 0x0005 reserved */
1429 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID		0x0006
1430 /* 0x0007 reserved */
1431 /* 0x0008 reserved */
1432 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC			0x0009
1433 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC			0x000A
1434 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC	0x000B
1435 #define I40E_AQC_ADD_CLOUD_FILTER_IIP			0x000C
1436 /* 0x000D reserved */
1437 /* 0x000E reserved */
1438 /* 0x000F reserved */
1439 /* 0x0010 to 0x0017 is for custom filters */
1440 #define I40E_AQC_ADD_CLOUD_FILTER_IP_PORT		0x0010 /* Dest IP + L4 Port */
1441 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT		0x0011 /* Dest MAC + L4 Port */
1442 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT		0x0012 /* Dest MAC + VLAN + L4 Port */
1443 
1444 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE		0x0080
1445 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT			6
1446 #define I40E_AQC_ADD_CLOUD_VNK_MASK			0x00C0
1447 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4			0
1448 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6			0x0100
1449 
1450 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT		9
1451 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK		0x1E00
1452 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN		0
1453 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC		1
1454 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE		2
1455 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP			3
1456 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED		4
1457 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE		5
1458 
1459 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC	0x2000
1460 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC	0x4000
1461 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP	0x8000
1462 
1463 	__le32	tenant_id;
1464 	u8	reserved[4];
1465 	__le16	queue_number;
1466 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT		0
1467 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK		(0x7FF << \
1468 						 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1469 	u8	reserved2[14];
1470 	/* response section */
1471 	u8	allocation_result;
1472 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS	0x0
1473 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL		0xFF
1474 	u8	response_reserved[7];
1475 };
1476 
1477 /* i40e_aqc_add_rm_cloud_filt_elem_ext is used when
1478  * I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER flag is set.
1479  */
1480 struct i40e_aqc_add_rm_cloud_filt_elem_ext {
1481 	struct i40e_aqc_cloud_filters_element_data element;
1482 	u16     general_fields[32];
1483 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0	0
1484 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1	1
1485 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2	2
1486 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0	3
1487 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1	4
1488 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2	5
1489 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0	6
1490 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1	7
1491 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2	8
1492 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0	9
1493 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1	10
1494 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2	11
1495 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0	12
1496 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1	13
1497 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2	14
1498 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0	15
1499 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1	16
1500 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2	17
1501 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3	18
1502 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4	19
1503 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5	20
1504 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6	21
1505 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7	22
1506 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0	23
1507 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1	24
1508 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2	25
1509 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3	26
1510 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4	27
1511 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5	28
1512 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6	29
1513 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7	30
1514 };
1515 
1516 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_cloud_filters_element_data);
1517 
1518 /* i40e_aqc_cloud_filters_element_bb is used when
1519  * I40E_AQC_CLOUD_CMD_BB flag is set.
1520  */
1521 struct i40e_aqc_cloud_filters_element_bb {
1522 	struct i40e_aqc_cloud_filters_element_data element;
1523 	u16     general_fields[32];
1524 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0	0
1525 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1	1
1526 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2	2
1527 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0	3
1528 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1	4
1529 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2	5
1530 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0	6
1531 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1	7
1532 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2	8
1533 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0	9
1534 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1	10
1535 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2	11
1536 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0	12
1537 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1	13
1538 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2	14
1539 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0	15
1540 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1	16
1541 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2	17
1542 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3	18
1543 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4	19
1544 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5	20
1545 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6	21
1546 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7	22
1547 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0	23
1548 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1	24
1549 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2	25
1550 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3	26
1551 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4	27
1552 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5	28
1553 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6	29
1554 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7	30
1555 };
1556 
1557 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_cloud_filters_element_bb);
1558 
1559 struct i40e_aqc_remove_cloud_filters_completion {
1560 	__le16 perfect_ovlan_used;
1561 	__le16 perfect_ovlan_free;
1562 	__le16 vlan_used;
1563 	__le16 vlan_free;
1564 	__le32 addr_high;
1565 	__le32 addr_low;
1566 };
1567 
1568 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1569 
1570 /* Replace filter Command 0x025F
1571  * uses the i40e_aqc_replace_cloud_filters,
1572  * and the generic indirect completion structure
1573  */
1574 struct i40e_filter_data {
1575 	u8 filter_type;
1576 	u8 input[3];
1577 };
1578 
1579 I40E_CHECK_STRUCT_LEN(4, i40e_filter_data);
1580 
1581 struct i40e_aqc_replace_cloud_filters_cmd {
1582 	u8	valid_flags;
1583 #define I40E_AQC_REPLACE_L1_FILTER		0x0
1584 #define I40E_AQC_REPLACE_CLOUD_FILTER		0x1
1585 #define I40E_AQC_GET_CLOUD_FILTERS		0x2
1586 #define I40E_AQC_MIRROR_CLOUD_FILTER		0x4
1587 #define I40E_AQC_HIGH_PRIORITY_CLOUD_FILTER	0x8
1588 	u8	old_filter_type;
1589 	u8	new_filter_type;
1590 	u8	tr_bit;
1591 	u8	tr_bit2;
1592 	u8	reserved[3];
1593 	__le32 addr_high;
1594 	__le32 addr_low;
1595 };
1596 
1597 I40E_CHECK_CMD_LENGTH(i40e_aqc_replace_cloud_filters_cmd);
1598 
1599 struct i40e_aqc_replace_cloud_filters_cmd_buf {
1600 	u8	data[32];
1601 /* Filter type INPUT codes*/
1602 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_ENTRIES_MAX	3
1603 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED	(1 << 7UL)
1604 
1605 /* Field Vector offsets */
1606 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_MAC_DA		0
1607 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_ETH		6
1608 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG		7
1609 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN		8
1610 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_OVLAN		9
1611 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN		10
1612 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY		11
1613 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC		12
1614 /* big FLU */
1615 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IP_DA		14
1616 /* big FLU */
1617 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_OIP_DA		15
1618 
1619 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN		37
1620 	struct i40e_filter_data	filters[8];
1621 };
1622 
1623 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_replace_cloud_filters_cmd_buf);
1624 
1625 /* Add Mirror Rule (indirect or direct 0x0260)
1626  * Delete Mirror Rule (indirect or direct 0x0261)
1627  * note: some rule types (4,5) do not use an external buffer.
1628  *       take care to set the flags correctly.
1629  */
1630 struct i40e_aqc_add_delete_mirror_rule {
1631 	__le16 seid;
1632 	__le16 rule_type;
1633 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT		0
1634 #define I40E_AQC_MIRROR_RULE_TYPE_MASK		(0x7 << \
1635 						I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1636 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS	1
1637 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS	2
1638 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN		3
1639 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS	4
1640 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS	5
1641 	__le16 num_entries;
1642 	__le16 destination;  /* VSI for add, rule id for delete */
1643 	__le32 addr_high;    /* address of array of 2-byte VSI or VLAN ids */
1644 	__le32 addr_low;
1645 };
1646 
1647 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1648 
1649 struct i40e_aqc_add_delete_mirror_rule_completion {
1650 	u8	reserved[2];
1651 	__le16	rule_id;  /* only used on add */
1652 	__le16	mirror_rules_used;
1653 	__le16	mirror_rules_free;
1654 	__le32	addr_high;
1655 	__le32	addr_low;
1656 };
1657 
1658 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1659 
1660 /* DCB 0x03xx*/
1661 
1662 /* PFC Ignore (direct 0x0301)
1663  *    the command and response use the same descriptor structure
1664  */
1665 struct i40e_aqc_pfc_ignore {
1666 	u8	tc_bitmap;
1667 	u8	command_flags; /* unused on response */
1668 #define I40E_AQC_PFC_IGNORE_SET		0x80
1669 #define I40E_AQC_PFC_IGNORE_CLEAR	0x0
1670 	u8	reserved[14];
1671 };
1672 
1673 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1674 
1675 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1676  * with no parameters
1677  */
1678 
1679 /* TX scheduler 0x04xx */
1680 
1681 /* Almost all the indirect commands use
1682  * this generic struct to pass the SEID in param0
1683  */
1684 struct i40e_aqc_tx_sched_ind {
1685 	__le16	vsi_seid;
1686 	u8	reserved[6];
1687 	__le32	addr_high;
1688 	__le32	addr_low;
1689 };
1690 
1691 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1692 
1693 /* Several commands respond with a set of queue set handles */
1694 struct i40e_aqc_qs_handles_resp {
1695 	__le16 qs_handles[8];
1696 };
1697 
1698 /* Configure VSI BW limits (direct 0x0400) */
1699 struct i40e_aqc_configure_vsi_bw_limit {
1700 	__le16	vsi_seid;
1701 	u8	reserved[2];
1702 	__le16	credit;
1703 	u8	reserved1[2];
1704 	u8	max_credit; /* 0-3, limit = 2^max */
1705 	u8	reserved2[7];
1706 };
1707 
1708 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1709 
1710 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1711  *    responds with i40e_aqc_qs_handles_resp
1712  */
1713 struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1714 	u8	tc_valid_bits;
1715 	u8	reserved[15];
1716 	__le16	tc_bw_credits[8]; /* FW writesback QS handles here */
1717 
1718 	/* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1719 	__le16	tc_bw_max[2];
1720 	u8	reserved1[28];
1721 };
1722 
1723 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1724 
1725 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1726  *    responds with i40e_aqc_qs_handles_resp
1727  */
1728 struct i40e_aqc_configure_vsi_tc_bw_data {
1729 	u8	tc_valid_bits;
1730 	u8	reserved[3];
1731 	u8	tc_bw_credits[8];
1732 	u8	reserved1[4];
1733 	__le16	qs_handles[8];
1734 };
1735 
1736 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1737 
1738 /* Query vsi bw configuration (indirect 0x0408) */
1739 struct i40e_aqc_query_vsi_bw_config_resp {
1740 	u8	tc_valid_bits;
1741 	u8	tc_suspended_bits;
1742 	u8	reserved[14];
1743 	__le16	qs_handles[8];
1744 	u8	reserved1[4];
1745 	__le16	port_bw_limit;
1746 	u8	reserved2[2];
1747 	u8	max_bw; /* 0-3, limit = 2^max */
1748 	u8	reserved3[23];
1749 };
1750 
1751 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1752 
1753 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1754 struct i40e_aqc_query_vsi_ets_sla_config_resp {
1755 	u8	tc_valid_bits;
1756 	u8	reserved[3];
1757 	u8	share_credits[8];
1758 	__le16	credits[8];
1759 
1760 	/* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1761 	__le16	tc_bw_max[2];
1762 };
1763 
1764 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1765 
1766 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1767 struct i40e_aqc_configure_switching_comp_bw_limit {
1768 	__le16	seid;
1769 	u8	reserved[2];
1770 	__le16	credit;
1771 	u8	reserved1[2];
1772 	u8	max_bw; /* 0-3, limit = 2^max */
1773 	u8	reserved2[7];
1774 };
1775 
1776 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1777 
1778 /* Enable  Physical Port ETS (indirect 0x0413)
1779  * Modify  Physical Port ETS (indirect 0x0414)
1780  * Disable Physical Port ETS (indirect 0x0415)
1781  */
1782 struct i40e_aqc_configure_switching_comp_ets_data {
1783 	u8	reserved[4];
1784 	u8	tc_valid_bits;
1785 	u8	seepage;
1786 #define I40E_AQ_ETS_SEEPAGE_EN_MASK	0x1
1787 	u8	tc_strict_priority_flags;
1788 	u8	reserved1[17];
1789 	u8	tc_bw_share_credits[8];
1790 	u8	reserved2[96];
1791 };
1792 
1793 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1794 
1795 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1796 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1797 	u8	tc_valid_bits;
1798 	u8	reserved[15];
1799 	__le16	tc_bw_credit[8];
1800 
1801 	/* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1802 	__le16	tc_bw_max[2];
1803 	u8	reserved1[28];
1804 };
1805 
1806 I40E_CHECK_STRUCT_LEN(0x40,
1807 		      i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1808 
1809 /* Configure Switching Component Bandwidth Allocation per Tc
1810  * (indirect 0x0417)
1811  */
1812 struct i40e_aqc_configure_switching_comp_bw_config_data {
1813 	u8	tc_valid_bits;
1814 	u8	reserved[2];
1815 	u8	absolute_credits; /* bool */
1816 	u8	tc_bw_share_credits[8];
1817 	u8	reserved1[20];
1818 };
1819 
1820 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1821 
1822 /* Query Switching Component Configuration (indirect 0x0418) */
1823 struct i40e_aqc_query_switching_comp_ets_config_resp {
1824 	u8	tc_valid_bits;
1825 	u8	reserved[35];
1826 	__le16	port_bw_limit;
1827 	u8	reserved1[2];
1828 	u8	tc_bw_max; /* 0-3, limit = 2^max */
1829 	u8	reserved2[23];
1830 };
1831 
1832 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1833 
1834 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1835 struct i40e_aqc_query_port_ets_config_resp {
1836 	u8	reserved[4];
1837 	u8	tc_valid_bits;
1838 	u8	reserved1;
1839 	u8	tc_strict_priority_bits;
1840 	u8	reserved2;
1841 	u8	tc_bw_share_credits[8];
1842 	__le16	tc_bw_limits[8];
1843 
1844 	/* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1845 	__le16	tc_bw_max[2];
1846 	u8	reserved3[32];
1847 };
1848 
1849 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1850 
1851 /* Query Switching Component Bandwidth Allocation per Traffic Type
1852  * (indirect 0x041A)
1853  */
1854 struct i40e_aqc_query_switching_comp_bw_config_resp {
1855 	u8	tc_valid_bits;
1856 	u8	reserved[2];
1857 	u8	absolute_credits_enable; /* bool */
1858 	u8	tc_bw_share_credits[8];
1859 	__le16	tc_bw_limits[8];
1860 
1861 	/* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1862 	__le16	tc_bw_max[2];
1863 };
1864 
1865 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1866 
1867 /* Suspend/resume port TX traffic
1868  * (direct 0x041B and 0x041C) uses the generic SEID struct
1869  */
1870 
1871 /* Configure partition BW
1872  * (indirect 0x041D)
1873  */
1874 struct i40e_aqc_configure_partition_bw_data {
1875 	__le16	pf_valid_bits;
1876 	u8	min_bw[16];      /* guaranteed bandwidth */
1877 	u8	max_bw[16];      /* bandwidth limit */
1878 };
1879 
1880 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1881 
1882 /* Get and set the active HMC resource profile and status.
1883  * (direct 0x0500) and (direct 0x0501)
1884  */
1885 struct i40e_aq_get_set_hmc_resource_profile {
1886 	u8	pm_profile;
1887 	u8	pe_vf_enabled;
1888 	u8	reserved[14];
1889 };
1890 
1891 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1892 
1893 enum i40e_aq_hmc_profile {
1894 	/* I40E_HMC_PROFILE_NO_CHANGE	= 0, reserved */
1895 	I40E_HMC_PROFILE_DEFAULT	= 1,
1896 	I40E_HMC_PROFILE_FAVOR_VF	= 2,
1897 	I40E_HMC_PROFILE_EQUAL		= 3,
1898 };
1899 
1900 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1901 
1902 /* set in param0 for get phy abilities to report qualified modules */
1903 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES	0x0001
1904 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES	0x0002
1905 
1906 enum i40e_aq_phy_type {
1907 	I40E_PHY_TYPE_SGMII			= 0x0,
1908 	I40E_PHY_TYPE_1000BASE_KX		= 0x1,
1909 	I40E_PHY_TYPE_10GBASE_KX4		= 0x2,
1910 	I40E_PHY_TYPE_10GBASE_KR		= 0x3,
1911 	I40E_PHY_TYPE_40GBASE_KR4		= 0x4,
1912 	I40E_PHY_TYPE_XAUI			= 0x5,
1913 	I40E_PHY_TYPE_XFI			= 0x6,
1914 	I40E_PHY_TYPE_SFI			= 0x7,
1915 	I40E_PHY_TYPE_XLAUI			= 0x8,
1916 	I40E_PHY_TYPE_XLPPI			= 0x9,
1917 	I40E_PHY_TYPE_40GBASE_CR4_CU		= 0xA,
1918 	I40E_PHY_TYPE_10GBASE_CR1_CU		= 0xB,
1919 	I40E_PHY_TYPE_10GBASE_AOC		= 0xC,
1920 	I40E_PHY_TYPE_40GBASE_AOC		= 0xD,
1921 	I40E_PHY_TYPE_UNRECOGNIZED		= 0xE,
1922 	I40E_PHY_TYPE_UNSUPPORTED		= 0xF,
1923 	I40E_PHY_TYPE_100BASE_TX		= 0x11,
1924 	I40E_PHY_TYPE_1000BASE_T		= 0x12,
1925 	I40E_PHY_TYPE_10GBASE_T			= 0x13,
1926 	I40E_PHY_TYPE_10GBASE_SR		= 0x14,
1927 	I40E_PHY_TYPE_10GBASE_LR		= 0x15,
1928 	I40E_PHY_TYPE_10GBASE_SFPP_CU		= 0x16,
1929 	I40E_PHY_TYPE_10GBASE_CR1		= 0x17,
1930 	I40E_PHY_TYPE_40GBASE_CR4		= 0x18,
1931 	I40E_PHY_TYPE_40GBASE_SR4		= 0x19,
1932 	I40E_PHY_TYPE_40GBASE_LR4		= 0x1A,
1933 	I40E_PHY_TYPE_1000BASE_SX		= 0x1B,
1934 	I40E_PHY_TYPE_1000BASE_LX		= 0x1C,
1935 	I40E_PHY_TYPE_1000BASE_T_OPTICAL	= 0x1D,
1936 	I40E_PHY_TYPE_20GBASE_KR2		= 0x1E,
1937 	I40E_PHY_TYPE_25GBASE_KR		= 0x1F,
1938 	I40E_PHY_TYPE_25GBASE_CR		= 0x20,
1939 	I40E_PHY_TYPE_25GBASE_SR		= 0x21,
1940 	I40E_PHY_TYPE_25GBASE_LR		= 0x22,
1941 	I40E_PHY_TYPE_25GBASE_AOC		= 0x23,
1942 	I40E_PHY_TYPE_25GBASE_ACC		= 0x24,
1943 	I40E_PHY_TYPE_2_5GBASE_T		= 0x30,
1944 	I40E_PHY_TYPE_5GBASE_T			= 0x31,
1945 	I40E_PHY_TYPE_MAX,
1946 	I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP	= 0xFD,
1947 	I40E_PHY_TYPE_EMPTY			= 0xFE,
1948 	I40E_PHY_TYPE_DEFAULT			= 0xFF,
1949 };
1950 
1951 #define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \
1952 				BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) | \
1953 				BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) | \
1954 				BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) | \
1955 				BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) | \
1956 				BIT_ULL(I40E_PHY_TYPE_XAUI) | \
1957 				BIT_ULL(I40E_PHY_TYPE_XFI) | \
1958 				BIT_ULL(I40E_PHY_TYPE_SFI) | \
1959 				BIT_ULL(I40E_PHY_TYPE_XLAUI) | \
1960 				BIT_ULL(I40E_PHY_TYPE_XLPPI) | \
1961 				BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) | \
1962 				BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) | \
1963 				BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) | \
1964 				BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) | \
1965 				BIT_ULL(I40E_PHY_TYPE_UNRECOGNIZED) | \
1966 				BIT_ULL(I40E_PHY_TYPE_UNSUPPORTED) | \
1967 				BIT_ULL(I40E_PHY_TYPE_100BASE_TX) | \
1968 				BIT_ULL(I40E_PHY_TYPE_1000BASE_T) | \
1969 				BIT_ULL(I40E_PHY_TYPE_10GBASE_T) | \
1970 				BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) | \
1971 				BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) | \
1972 				BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) | \
1973 				BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) | \
1974 				BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) | \
1975 				BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) | \
1976 				BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) | \
1977 				BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) | \
1978 				BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) | \
1979 				BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) | \
1980 				BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) | \
1981 				BIT_ULL(I40E_PHY_TYPE_25GBASE_KR) | \
1982 				BIT_ULL(I40E_PHY_TYPE_25GBASE_CR) | \
1983 				BIT_ULL(I40E_PHY_TYPE_25GBASE_SR) | \
1984 				BIT_ULL(I40E_PHY_TYPE_25GBASE_LR) | \
1985 				BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC) | \
1986 				BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC) | \
1987 				BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T) | \
1988 				BIT_ULL(I40E_PHY_TYPE_5GBASE_T))
1989 
1990 #define I40E_LINK_SPEED_2_5GB_SHIFT	0x0
1991 #define I40E_LINK_SPEED_100MB_SHIFT	0x1
1992 #define I40E_LINK_SPEED_1000MB_SHIFT	0x2
1993 #define I40E_LINK_SPEED_10GB_SHIFT	0x3
1994 #define I40E_LINK_SPEED_40GB_SHIFT	0x4
1995 #define I40E_LINK_SPEED_20GB_SHIFT	0x5
1996 #define I40E_LINK_SPEED_25GB_SHIFT	0x6
1997 #define I40E_LINK_SPEED_5GB_SHIFT	0x7
1998 
1999 enum i40e_aq_link_speed {
2000 	I40E_LINK_SPEED_UNKNOWN	= 0,
2001 	I40E_LINK_SPEED_100MB	= (1 << I40E_LINK_SPEED_100MB_SHIFT),
2002 	I40E_LINK_SPEED_1GB	= (1 << I40E_LINK_SPEED_1000MB_SHIFT),
2003 	I40E_LINK_SPEED_2_5GB	= (1 << I40E_LINK_SPEED_2_5GB_SHIFT),
2004 	I40E_LINK_SPEED_5GB	= (1 << I40E_LINK_SPEED_5GB_SHIFT),
2005 	I40E_LINK_SPEED_10GB	= (1 << I40E_LINK_SPEED_10GB_SHIFT),
2006 	I40E_LINK_SPEED_40GB	= (1 << I40E_LINK_SPEED_40GB_SHIFT),
2007 	I40E_LINK_SPEED_20GB	= (1 << I40E_LINK_SPEED_20GB_SHIFT),
2008 	I40E_LINK_SPEED_25GB	= (1 << I40E_LINK_SPEED_25GB_SHIFT),
2009 };
2010 
2011 struct i40e_aqc_module_desc {
2012 	u8 oui[3];
2013 	u8 reserved1;
2014 	u8 part_number[16];
2015 	u8 revision[4];
2016 	u8 reserved2[8];
2017 };
2018 
2019 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
2020 
2021 struct i40e_aq_get_phy_abilities_resp {
2022 	__le32	phy_type;       /* bitmap using the above enum for offsets */
2023 	u8	link_speed;     /* bitmap using the above enum bit patterns */
2024 	u8	abilities;
2025 #define I40E_AQ_PHY_FLAG_PAUSE_TX	0x01
2026 #define I40E_AQ_PHY_FLAG_PAUSE_RX	0x02
2027 #define I40E_AQ_PHY_FLAG_LOW_POWER	0x04
2028 #define I40E_AQ_PHY_LINK_ENABLED	0x08
2029 #define I40E_AQ_PHY_AN_ENABLED		0x10
2030 #define I40E_AQ_PHY_FLAG_MODULE_QUAL	0x20
2031 #define I40E_AQ_PHY_FEC_ABILITY_KR	0x40
2032 #define I40E_AQ_PHY_FEC_ABILITY_RS	0x80
2033 	__le16	eee_capability;
2034 #define I40E_AQ_EEE_AUTO		0x0001
2035 #define I40E_AQ_EEE_100BASE_TX		0x0002
2036 #define I40E_AQ_EEE_1000BASE_T		0x0004
2037 #define I40E_AQ_EEE_10GBASE_T		0x0008
2038 #define I40E_AQ_EEE_1000BASE_KX		0x0010
2039 #define I40E_AQ_EEE_10GBASE_KX4		0x0020
2040 #define I40E_AQ_EEE_10GBASE_KR		0x0040
2041 #define I40E_AQ_EEE_2_5GBASE_T		0x0100
2042 #define I40E_AQ_EEE_5GBASE_T		0x0200
2043 	__le32	eeer_val;
2044 	u8	d3_lpan;
2045 #define I40E_AQ_SET_PHY_D3_LPAN_ENA	0x01
2046 	u8	phy_type_ext;
2047 #define I40E_AQ_PHY_TYPE_EXT_25G_KR	0x01
2048 #define I40E_AQ_PHY_TYPE_EXT_25G_CR	0x02
2049 #define I40E_AQ_PHY_TYPE_EXT_25G_SR	0x04
2050 #define I40E_AQ_PHY_TYPE_EXT_25G_LR	0x08
2051 #define I40E_AQ_PHY_TYPE_EXT_25G_AOC	0x10
2052 #define I40E_AQ_PHY_TYPE_EXT_25G_ACC	0x20
2053 #define I40E_AQ_PHY_TYPE_EXT_2_5GBASE_T	0x40
2054 #define I40E_AQ_PHY_TYPE_EXT_5GBASE_T	0x80
2055 	u8	fec_cfg_curr_mod_ext_info;
2056 #define I40E_AQ_ENABLE_FEC_KR		0x01
2057 #define I40E_AQ_ENABLE_FEC_RS		0x02
2058 #define I40E_AQ_REQUEST_FEC_KR		0x04
2059 #define I40E_AQ_REQUEST_FEC_RS		0x08
2060 #define I40E_AQ_ENABLE_FEC_AUTO		0x10
2061 #define I40E_AQ_FEC
2062 #define I40E_AQ_MODULE_TYPE_EXT_MASK	0xE0
2063 #define I40E_AQ_MODULE_TYPE_EXT_SHIFT	5
2064 
2065 	u8	ext_comp_code;
2066 	u8	phy_id[4];
2067 	u8	module_type[3];
2068 	u8	qualified_module_count;
2069 #define I40E_AQ_PHY_MAX_QMS		16
2070 	struct i40e_aqc_module_desc	qualified_module[I40E_AQ_PHY_MAX_QMS];
2071 };
2072 
2073 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
2074 
2075 /* Set PHY Config (direct 0x0601) */
2076 struct i40e_aq_set_phy_config { /* same bits as above in all */
2077 	__le32	phy_type;
2078 	u8	link_speed;
2079 	u8	abilities;
2080 /* bits 0-2 use the values from get_phy_abilities_resp */
2081 #define I40E_AQ_PHY_ENABLE_LINK		0x08
2082 #define I40E_AQ_PHY_ENABLE_AN		0x10
2083 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK	0x20
2084 	__le16	eee_capability;
2085 	__le32	eeer;
2086 	u8	low_power_ctrl;
2087 	u8	phy_type_ext;
2088 	u8	fec_config;
2089 #define I40E_AQ_SET_FEC_ABILITY_KR	BIT(0)
2090 #define I40E_AQ_SET_FEC_ABILITY_RS	BIT(1)
2091 #define I40E_AQ_SET_FEC_REQUEST_KR	BIT(2)
2092 #define I40E_AQ_SET_FEC_REQUEST_RS	BIT(3)
2093 #define I40E_AQ_SET_FEC_AUTO		BIT(4)
2094 #define I40E_AQ_PHY_FEC_CONFIG_SHIFT	0x0
2095 #define I40E_AQ_PHY_FEC_CONFIG_MASK	(0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT)
2096 	u8	reserved;
2097 };
2098 
2099 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
2100 
2101 /* Set MAC Config command data structure (direct 0x0603) */
2102 struct i40e_aq_set_mac_config {
2103 	__le16	max_frame_size;
2104 	u8	params;
2105 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN			0x04
2106 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK		0x78
2107 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT		3
2108 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE		0x0
2109 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX		0xF
2110 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX		0x9
2111 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX		0x8
2112 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX		0x7
2113 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX		0x6
2114 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX		0x5
2115 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX		0x4
2116 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX		0x3
2117 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX		0x2
2118 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX		0x1
2119 #define I40E_AQ_SET_MAC_CONFIG_DROP_BLOCKING_PACKET_EN	0x80
2120 	u8	tx_timer_priority; /* bitmap */
2121 	__le16	tx_timer_value;
2122 	__le16	fc_refresh_threshold;
2123 	u8	reserved[8];
2124 };
2125 
2126 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
2127 
2128 /* Restart Auto-Negotiation (direct 0x605) */
2129 struct i40e_aqc_set_link_restart_an {
2130 	u8	command;
2131 #define I40E_AQ_PHY_RESTART_AN	0x02
2132 #define I40E_AQ_PHY_LINK_ENABLE	0x04
2133 	u8	reserved[15];
2134 };
2135 
2136 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
2137 
2138 /* Get Link Status cmd & response data structure (direct 0x0607) */
2139 struct i40e_aqc_get_link_status {
2140 	__le16	command_flags; /* only field set on command */
2141 #define I40E_AQ_LSE_MASK		0x3
2142 #define I40E_AQ_LSE_NOP			0x0
2143 #define I40E_AQ_LSE_DISABLE		0x2
2144 #define I40E_AQ_LSE_ENABLE		0x3
2145 /* only response uses this flag */
2146 #define I40E_AQ_LSE_IS_ENABLED		0x1
2147 	u8	phy_type;    /* i40e_aq_phy_type   */
2148 	u8	link_speed;  /* i40e_aq_link_speed */
2149 	u8	link_info;
2150 #define I40E_AQ_LINK_UP			0x01    /* obsolete */
2151 #define I40E_AQ_LINK_UP_FUNCTION	0x01
2152 #define I40E_AQ_LINK_FAULT		0x02
2153 #define I40E_AQ_LINK_FAULT_TX		0x04
2154 #define I40E_AQ_LINK_FAULT_RX		0x08
2155 #define I40E_AQ_LINK_FAULT_REMOTE	0x10
2156 #define I40E_AQ_LINK_UP_PORT		0x20
2157 #define I40E_AQ_MEDIA_AVAILABLE		0x40
2158 #define I40E_AQ_SIGNAL_DETECT		0x80
2159 	u8	an_info;
2160 #define I40E_AQ_AN_COMPLETED		0x01
2161 #define I40E_AQ_LP_AN_ABILITY		0x02
2162 #define I40E_AQ_PD_FAULT		0x04
2163 #define I40E_AQ_FEC_EN			0x08
2164 #define I40E_AQ_PHY_LOW_POWER		0x10
2165 #define I40E_AQ_LINK_PAUSE_TX		0x20
2166 #define I40E_AQ_LINK_PAUSE_RX		0x40
2167 #define I40E_AQ_QUALIFIED_MODULE	0x80
2168 	u8	ext_info;
2169 #define I40E_AQ_LINK_PHY_TEMP_ALARM	0x01
2170 #define I40E_AQ_LINK_XCESSIVE_ERRORS	0x02
2171 #define I40E_AQ_LINK_TX_SHIFT		0x02
2172 #define I40E_AQ_LINK_TX_MASK		(0x03 << I40E_AQ_LINK_TX_SHIFT)
2173 #define I40E_AQ_LINK_TX_ACTIVE		0x00
2174 #define I40E_AQ_LINK_TX_DRAINED		0x01
2175 #define I40E_AQ_LINK_TX_FLUSHED		0x03
2176 #define I40E_AQ_LINK_FORCED_40G		0x10
2177 /* 25G Error Codes */
2178 #define I40E_AQ_25G_NO_ERR		0X00
2179 #define I40E_AQ_25G_NOT_PRESENT		0X01
2180 #define I40E_AQ_25G_NVM_CRC_ERR		0X02
2181 #define I40E_AQ_25G_SBUS_UCODE_ERR	0X03
2182 #define I40E_AQ_25G_SERDES_UCODE_ERR	0X04
2183 #define I40E_AQ_25G_NIMB_UCODE_ERR	0X05
2184 	u8	loopback; /* use defines from i40e_aqc_set_lb_mode */
2185 /* Since firmware API 1.7 loopback field keeps power class info as well */
2186 #define I40E_AQ_LOOPBACK_MASK		0x07
2187 #define I40E_AQ_PWR_CLASS_SHIFT_LB	6
2188 #define I40E_AQ_PWR_CLASS_MASK_LB	(0x03 << I40E_AQ_PWR_CLASS_SHIFT_LB)
2189 	__le16	max_frame_size;
2190 	u8	config;
2191 #define I40E_AQ_CONFIG_FEC_KR_ENA	0x01
2192 #define I40E_AQ_CONFIG_FEC_RS_ENA	0x02
2193 #define I40E_AQ_CONFIG_CRC_ENA		0x04
2194 #define I40E_AQ_CONFIG_PACING_MASK	0x78
2195 	union {
2196 		struct {
2197 			u8	power_desc;
2198 #define I40E_AQ_LINK_POWER_CLASS_1	0x00
2199 #define I40E_AQ_LINK_POWER_CLASS_2	0x01
2200 #define I40E_AQ_LINK_POWER_CLASS_3	0x02
2201 #define I40E_AQ_LINK_POWER_CLASS_4	0x03
2202 #define I40E_AQ_PWR_CLASS_MASK		0x03
2203 			u8	reserved[4];
2204 		};
2205 		struct {
2206 			u8	link_type[4];
2207 			u8	link_type_ext;
2208 		};
2209 	};
2210 };
2211 
2212 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
2213 
2214 /* Set event mask command (direct 0x613) */
2215 struct i40e_aqc_set_phy_int_mask {
2216 	u8	reserved[8];
2217 	__le16	event_mask;
2218 #define I40E_AQ_EVENT_LINK_UPDOWN	0x0002
2219 #define I40E_AQ_EVENT_MEDIA_NA		0x0004
2220 #define I40E_AQ_EVENT_LINK_FAULT	0x0008
2221 #define I40E_AQ_EVENT_PHY_TEMP_ALARM	0x0010
2222 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS	0x0020
2223 #define I40E_AQ_EVENT_SIGNAL_DETECT	0x0040
2224 #define I40E_AQ_EVENT_AN_COMPLETED	0x0080
2225 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL	0x0100
2226 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED	0x0200
2227 	u8	reserved1[6];
2228 };
2229 
2230 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
2231 
2232 /* Get Local AN advt register (direct 0x0614)
2233  * Set Local AN advt register (direct 0x0615)
2234  * Get Link Partner AN advt register (direct 0x0616)
2235  */
2236 struct i40e_aqc_an_advt_reg {
2237 	__le32	local_an_reg0;
2238 	__le16	local_an_reg1;
2239 	u8	reserved[10];
2240 };
2241 
2242 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
2243 
2244 /* Set Loopback mode (0x0618) */
2245 struct i40e_aqc_set_lb_mode {
2246 	u8	lb_level;
2247 #define I40E_AQ_LB_NONE	0
2248 #define I40E_AQ_LB_MAC	1
2249 #define I40E_AQ_LB_SERDES	2
2250 #define I40E_AQ_LB_PHY_INT	3
2251 #define I40E_AQ_LB_PHY_EXT	4
2252 #define I40E_AQ_LB_BASE_T_PCS	5
2253 #define I40E_AQ_LB_BASE_T_EXT	6
2254 #define I40E_AQ_LB_PHY_LOCAL	0x01
2255 #define I40E_AQ_LB_PHY_REMOTE	0x02
2256 #define I40E_AQ_LB_MAC_LOCAL	0x04
2257 	u8	lb_type;
2258 #define I40E_AQ_LB_LOCAL	0
2259 #define I40E_AQ_LB_FAR	0x01
2260 	u8	speed;
2261 #define I40E_AQ_LB_SPEED_NONE	0
2262 #define I40E_AQ_LB_SPEED_1G	1
2263 #define I40E_AQ_LB_SPEED_10G	2
2264 #define I40E_AQ_LB_SPEED_40G	3
2265 #define I40E_AQ_LB_SPEED_20G	4
2266 	u8	force_speed;
2267 	u8	reserved[12];
2268 };
2269 
2270 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
2271 
2272 /* Set PHY Debug command (0x0622) */
2273 struct i40e_aqc_set_phy_debug {
2274 	u8	command_flags;
2275 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL	0x02
2276 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT	2
2277 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK	(0x03 << \
2278 					I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
2279 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE	0x00
2280 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD	0x01
2281 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT	0x02
2282 /* Disable link manageability on a single port */
2283 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW	0x10
2284 /* Disable link manageability on all ports needs both bits 4 and 5 */
2285 #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW	0x20
2286 	u8	reserved[15];
2287 };
2288 
2289 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
2290 
2291 enum i40e_aq_phy_reg_type {
2292 	I40E_AQC_PHY_REG_INTERNAL	= 0x1,
2293 	I40E_AQC_PHY_REG_EXERNAL_BASET	= 0x2,
2294 	I40E_AQC_PHY_REG_EXERNAL_MODULE	= 0x3
2295 };
2296 
2297 #pragma pack(1)
2298 /* Run PHY Activity (0x0626) */
2299 struct i40e_aqc_run_phy_activity {
2300 	u8	cmd_flags;
2301 	__le16	activity_id;
2302 #define I40E_AQ_RUN_PHY_ACT_ID_USR_DFND			0x10
2303 	u8	reserved;
2304 	union {
2305 		struct {
2306 			__le32  dnl_opcode;
2307 #define I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_STAT_DUR	0x801a
2308 #define I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_STAT	0x801b
2309 #define I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_DUR	0x1801b
2310 			__le32  data;
2311 			u8	reserved2[4];
2312 		} cmd;
2313 		struct {
2314 			__le32	cmd_status;
2315 #define I40E_AQ_RUN_PHY_ACT_CMD_STAT_SUCC		0x4
2316 #define I40E_AQ_RUN_PHY_ACT_CMD_STAT_MASK		0xFFFF
2317 			__le32	data0;
2318 			__le32	data1;
2319 		} resp;
2320 	} params;
2321 };
2322 #pragma pack()
2323 
2324 /*
2325  * Unfortunately, for some reason smatch cannot parse the following correctly
2326  * and emits divide by zero expressions when it shouldn't. Until this is fixed,
2327  * for the time being comment out the check.
2328  */
2329 #ifndef __sun__
2330 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity);
2331 #endif
2332 
2333 /* Set PHY Register command (0x0628) */
2334 /* Get PHY Register command (0x0629) */
2335 struct i40e_aqc_phy_register_access {
2336 	u8	phy_interface;
2337 #define I40E_AQ_PHY_REG_ACCESS_INTERNAL	0
2338 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL	1
2339 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE	2
2340 	u8	dev_addres;
2341 	u8	cmd_flags;
2342 #define I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE	0x01
2343 #define I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER	0x02
2344 #define I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT	2
2345 #define I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK	(0x3 << \
2346 		I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT)
2347 	u8	reserved1;
2348 	__le32	reg_address;
2349 	__le32	reg_value;
2350 	u8	reserved2[4];
2351 };
2352 
2353 I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access);
2354 
2355 /* NVM Read command (indirect 0x0701)
2356  * NVM Erase commands (direct 0x0702)
2357  * NVM Update commands (indirect 0x0703)
2358  */
2359 struct i40e_aqc_nvm_update {
2360 	u8	command_flags;
2361 #define I40E_AQ_NVM_LAST_CMD			0x01
2362 #define I40E_AQ_NVM_REARRANGE_TO_FLAT		0x20
2363 #define I40E_AQ_NVM_REARRANGE_TO_STRUCT		0x40
2364 #define I40E_AQ_NVM_FLASH_ONLY			0x80
2365 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT	1
2366 #define I40E_AQ_NVM_PRESERVATION_FLAGS_MASK	0x03
2367 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED	0x03
2368 #define I40E_AQ_NVM_PRESERVATION_FLAGS_ALL	0x01
2369 	u8	module_pointer;
2370 	__le16	length;
2371 	__le32	offset;
2372 	__le32	addr_high;
2373 	__le32	addr_low;
2374 };
2375 
2376 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
2377 
2378 /* NVM Config Read (indirect 0x0704) */
2379 struct i40e_aqc_nvm_config_read {
2380 	__le16	cmd_flags;
2381 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK	1
2382 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE		0
2383 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES		1
2384 	__le16	element_count;
2385 	__le16	element_id;	/* Feature/field ID */
2386 	__le16	element_id_msw;	/* MSWord of field ID */
2387 	__le32	address_high;
2388 	__le32	address_low;
2389 };
2390 
2391 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
2392 
2393 /* NVM Config Write (indirect 0x0705) */
2394 struct i40e_aqc_nvm_config_write {
2395 	__le16	cmd_flags;
2396 	__le16	element_count;
2397 	u8	reserved[4];
2398 	__le32	address_high;
2399 	__le32	address_low;
2400 };
2401 
2402 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
2403 
2404 /* Used for 0x0704 as well as for 0x0705 commands */
2405 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT		1
2406 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
2407 				(1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
2408 #define I40E_AQ_ANVM_FEATURE		0
2409 #define I40E_AQ_ANVM_IMMEDIATE_FIELD	(1 << FEATURE_OR_IMMEDIATE_SHIFT)
2410 struct i40e_aqc_nvm_config_data_feature {
2411 	__le16 feature_id;
2412 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY		0x01
2413 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP		0x08
2414 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR		0x10
2415 	__le16 feature_options;
2416 	__le16 feature_selection;
2417 };
2418 
2419 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
2420 
2421 struct i40e_aqc_nvm_config_data_immediate_field {
2422 	__le32 field_id;
2423 	__le32 field_value;
2424 	__le16 field_options;
2425 	__le16 reserved;
2426 };
2427 
2428 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
2429 
2430 /* OEM Post Update (indirect 0x0720)
2431  * no command data struct used
2432  */
2433 struct i40e_aqc_nvm_oem_post_update {
2434 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA	0x01
2435 	u8 sel_data;
2436 	u8 reserved[7];
2437 };
2438 
2439 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
2440 
2441 struct i40e_aqc_nvm_oem_post_update_buffer {
2442 	u8 str_len;
2443 	u8 dev_addr;
2444 	__le16 eeprom_addr;
2445 	u8 data[36];
2446 };
2447 
2448 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
2449 
2450 /* Thermal Sensor (indirect 0x0721)
2451  *     read or set thermal sensor configs and values
2452  *     takes a sensor and command specific data buffer, not detailed here
2453  */
2454 struct i40e_aqc_thermal_sensor {
2455 	u8 sensor_action;
2456 #define I40E_AQ_THERMAL_SENSOR_READ_CONFIG	0
2457 #define I40E_AQ_THERMAL_SENSOR_SET_CONFIG	1
2458 #define I40E_AQ_THERMAL_SENSOR_READ_TEMP	2
2459 	u8 reserved[7];
2460 	__le32	addr_high;
2461 	__le32	addr_low;
2462 };
2463 
2464 I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor);
2465 
2466 /* Send to PF command (indirect 0x0801) id is only used by PF
2467  * Send to VF command (indirect 0x0802) id is only used by PF
2468  * Send to Peer PF command (indirect 0x0803)
2469  */
2470 struct i40e_aqc_pf_vf_message {
2471 	__le32	id;
2472 	u8	reserved[4];
2473 	__le32	addr_high;
2474 	__le32	addr_low;
2475 };
2476 
2477 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
2478 
2479 /* Alternate structure */
2480 
2481 /* Direct write (direct 0x0900)
2482  * Direct read (direct 0x0902)
2483  */
2484 struct i40e_aqc_alternate_write {
2485 	__le32 address0;
2486 	__le32 data0;
2487 	__le32 address1;
2488 	__le32 data1;
2489 };
2490 
2491 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
2492 
2493 /* Indirect write (indirect 0x0901)
2494  * Indirect read (indirect 0x0903)
2495  */
2496 
2497 struct i40e_aqc_alternate_ind_write {
2498 	__le32 address;
2499 	__le32 length;
2500 	__le32 addr_high;
2501 	__le32 addr_low;
2502 };
2503 
2504 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
2505 
2506 /* Done alternate write (direct 0x0904)
2507  * uses i40e_aq_desc
2508  */
2509 struct i40e_aqc_alternate_write_done {
2510 	__le16	cmd_flags;
2511 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK	1
2512 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY	0
2513 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI	1
2514 #define I40E_AQ_ALTERNATE_RESET_NEEDED		2
2515 	u8	reserved[14];
2516 };
2517 
2518 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
2519 
2520 /* Set OEM mode (direct 0x0905) */
2521 struct i40e_aqc_alternate_set_mode {
2522 	__le32	mode;
2523 #define I40E_AQ_ALTERNATE_MODE_NONE	0
2524 #define I40E_AQ_ALTERNATE_MODE_OEM	1
2525 	u8	reserved[12];
2526 };
2527 
2528 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
2529 
2530 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
2531 
2532 /* async events 0x10xx */
2533 
2534 /* Lan Queue Overflow Event (direct, 0x1001) */
2535 struct i40e_aqc_lan_overflow {
2536 	__le32	prtdcb_rupto;
2537 	__le32	otx_ctl;
2538 	u8	reserved[8];
2539 };
2540 
2541 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
2542 
2543 /* Get LLDP MIB (indirect 0x0A00) */
2544 struct i40e_aqc_lldp_get_mib {
2545 	u8	type;
2546 	u8	reserved1;
2547 #define I40E_AQ_LLDP_MIB_TYPE_MASK		0x3
2548 #define I40E_AQ_LLDP_MIB_LOCAL			0x0
2549 #define I40E_AQ_LLDP_MIB_REMOTE			0x1
2550 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE	0x2
2551 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK		0xC
2552 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT		0x2
2553 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE	0x0
2554 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR	0x1
2555 #define I40E_AQ_LLDP_TX_SHIFT			0x4
2556 #define I40E_AQ_LLDP_TX_MASK			(0x03 << I40E_AQ_LLDP_TX_SHIFT)
2557 /* TX pause flags use I40E_AQ_LINK_TX_* above */
2558 	__le16	local_len;
2559 	__le16	remote_len;
2560 	u8	reserved2[2];
2561 	__le32	addr_high;
2562 	__le32	addr_low;
2563 };
2564 
2565 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
2566 
2567 /* Configure LLDP MIB Change Event (direct 0x0A01)
2568  * also used for the event (with type in the command field)
2569  */
2570 struct i40e_aqc_lldp_update_mib {
2571 	u8	command;
2572 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE	0x0
2573 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE	0x1
2574 	u8	reserved[7];
2575 	__le32	addr_high;
2576 	__le32	addr_low;
2577 };
2578 
2579 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
2580 
2581 /* Add LLDP TLV (indirect 0x0A02)
2582  * Delete LLDP TLV (indirect 0x0A04)
2583  */
2584 struct i40e_aqc_lldp_add_tlv {
2585 	u8	type; /* only nearest bridge and non-TPMR from 0x0A00 */
2586 	u8	reserved1[1];
2587 	__le16	len;
2588 	u8	reserved2[4];
2589 	__le32	addr_high;
2590 	__le32	addr_low;
2591 };
2592 
2593 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2594 
2595 /* Update LLDP TLV (indirect 0x0A03) */
2596 struct i40e_aqc_lldp_update_tlv {
2597 	u8	type; /* only nearest bridge and non-TPMR from 0x0A00 */
2598 	u8	reserved;
2599 	__le16	old_len;
2600 	__le16	new_offset;
2601 	__le16	new_len;
2602 	__le32	addr_high;
2603 	__le32	addr_low;
2604 };
2605 
2606 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2607 
2608 /* Stop LLDP (direct 0x0A05) */
2609 struct i40e_aqc_lldp_stop {
2610 	u8	command;
2611 #define I40E_AQ_LLDP_AGENT_STOP			0x0
2612 #define I40E_AQ_LLDP_AGENT_SHUTDOWN		0x1
2613 #define I40E_AQ_LLDP_AGENT_STOP_PERSIST		0x2
2614 	u8	reserved[15];
2615 };
2616 
2617 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2618 
2619 /* Start LLDP (direct 0x0A06) */
2620 struct i40e_aqc_lldp_start {
2621 	u8	command;
2622 #define I40E_AQ_LLDP_AGENT_START		0x1
2623 #define I40E_AQ_LLDP_AGENT_START_PERSIST	0x2
2624 	u8	reserved[15];
2625 };
2626 
2627 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2628 
2629 /* Set DCB (direct 0x0303) */
2630 struct i40e_aqc_set_dcb_parameters {
2631 	u8 command;
2632 #define I40E_AQ_DCB_SET_AGENT	0x1
2633 #define I40E_DCB_VALID		0x1
2634 	u8 valid_flags;
2635 	u8 reserved[14];
2636 };
2637 
2638 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_dcb_parameters);
2639 
2640 /* Get CEE DCBX Oper Config (0x0A07)
2641  * uses the generic descriptor struct
2642  * returns below as indirect response
2643  */
2644 
2645 #define I40E_AQC_CEE_APP_FCOE_SHIFT	0x0
2646 #define I40E_AQC_CEE_APP_FCOE_MASK	(0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2647 #define I40E_AQC_CEE_APP_ISCSI_SHIFT	0x3
2648 #define I40E_AQC_CEE_APP_ISCSI_MASK	(0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2649 #define I40E_AQC_CEE_APP_FIP_SHIFT	0x8
2650 #define I40E_AQC_CEE_APP_FIP_MASK	(0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2651 
2652 #define I40E_AQC_CEE_PG_STATUS_SHIFT	0x0
2653 #define I40E_AQC_CEE_PG_STATUS_MASK	(0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2654 #define I40E_AQC_CEE_PFC_STATUS_SHIFT	0x3
2655 #define I40E_AQC_CEE_PFC_STATUS_MASK	(0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2656 #define I40E_AQC_CEE_APP_STATUS_SHIFT	0x8
2657 #define I40E_AQC_CEE_APP_STATUS_MASK	(0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2658 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT	0x8
2659 #define I40E_AQC_CEE_FCOE_STATUS_MASK	(0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT)
2660 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT	0xB
2661 #define I40E_AQC_CEE_ISCSI_STATUS_MASK	(0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT)
2662 #define I40E_AQC_CEE_FIP_STATUS_SHIFT	0x10
2663 #define I40E_AQC_CEE_FIP_STATUS_MASK	(0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT)
2664 
2665 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
2666  * word boundary layout issues, which the Linux compilers silently deal
2667  * with by adding padding, making the actual struct larger than designed.
2668  * However, the FW compiler for the NIC is less lenient and complains
2669  * about the struct.  Hence, the struct defined here has an extra byte in
2670  * fields reserved3 and reserved4 to directly acknowledge that padding,
2671  * and the new length is used in the length check macro.
2672  */
2673 struct i40e_aqc_get_cee_dcb_cfg_v1_resp {
2674 	u8	reserved1;
2675 	u8	oper_num_tc;
2676 	u8	oper_prio_tc[4];
2677 	u8	reserved2;
2678 	u8	oper_tc_bw[8];
2679 	u8	oper_pfc_en;
2680 	u8	reserved3[2];
2681 	__le16	oper_app_prio;
2682 	u8	reserved4[2];
2683 	__le16	tlv_status;
2684 };
2685 
2686 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp);
2687 
2688 struct i40e_aqc_get_cee_dcb_cfg_resp {
2689 	u8	oper_num_tc;
2690 	u8	oper_prio_tc[4];
2691 	u8	oper_tc_bw[8];
2692 	u8	oper_pfc_en;
2693 	__le16	oper_app_prio;
2694 	__le32	tlv_status;
2695 	u8	reserved[12];
2696 };
2697 
2698 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);
2699 
2700 /*	Set Local LLDP MIB (indirect 0x0A08)
2701  *	Used to replace the local MIB of a given LLDP agent. e.g. DCBx
2702  */
2703 struct i40e_aqc_lldp_set_local_mib {
2704 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT	0
2705 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK	(1 << \
2706 					SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
2707 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB	0x0
2708 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT	(1)
2709 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK	(1 << \
2710 				SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
2711 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS		0x1
2712 	u8	type;
2713 	u8	reserved0;
2714 	__le16	length;
2715 	u8	reserved1[4];
2716 	__le32	address_high;
2717 	__le32	address_low;
2718 };
2719 
2720 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib);
2721 
2722 struct i40e_aqc_lldp_set_local_mib_resp {
2723 #define SET_LOCAL_MIB_RESP_EVENT_TRIGGERED_MASK      0x01
2724 	u8  status;
2725 	u8  reserved[15];
2726 };
2727 
2728 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_lldp_set_local_mib_resp);
2729 
2730 /*	Stop/Start LLDP Agent (direct 0x0A09)
2731  *	Used for stopping/starting specific LLDP agent. e.g. DCBx
2732  */
2733 struct i40e_aqc_lldp_stop_start_specific_agent {
2734 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT	0
2735 #define I40E_AQC_START_SPECIFIC_AGENT_MASK \
2736 				(1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT)
2737 	u8	command;
2738 	u8	reserved[15];
2739 };
2740 
2741 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent);
2742 
2743 /* Restore LLDP Agent factory settings (direct 0x0A0A) */
2744 struct i40e_aqc_lldp_restore {
2745 	u8	command;
2746 #define I40E_AQ_LLDP_AGENT_RESTORE_NOT		0x0
2747 #define I40E_AQ_LLDP_AGENT_RESTORE		0x1
2748 	u8	reserved[15];
2749 };
2750 
2751 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_restore);
2752 
2753 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2754 struct i40e_aqc_add_udp_tunnel {
2755 	__le16	udp_port;
2756 	u8	reserved0[3];
2757 	u8	protocol_type;
2758 #define I40E_AQC_TUNNEL_TYPE_VXLAN	0x00
2759 #define I40E_AQC_TUNNEL_TYPE_NGE	0x01
2760 #define I40E_AQC_TUNNEL_TYPE_TEREDO	0x10
2761 #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE	0x11
2762 	u8	reserved1[10];
2763 };
2764 
2765 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2766 
2767 struct i40e_aqc_add_udp_tunnel_completion {
2768 	__le16	udp_port;
2769 	u8	filter_entry_index;
2770 	u8	multiple_pfs;
2771 #define I40E_AQC_SINGLE_PF		0x0
2772 #define I40E_AQC_MULTIPLE_PFS		0x1
2773 	u8	total_filters;
2774 	u8	reserved[11];
2775 };
2776 
2777 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2778 
2779 /* remove UDP Tunnel command (0x0B01) */
2780 struct i40e_aqc_remove_udp_tunnel {
2781 	u8	reserved[2];
2782 	u8	index; /* 0 to 15 */
2783 	u8	reserved2[13];
2784 };
2785 
2786 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2787 
2788 struct i40e_aqc_del_udp_tunnel_completion {
2789 	__le16	udp_port;
2790 	u8	index; /* 0 to 15 */
2791 	u8	multiple_pfs;
2792 	u8	total_filters_used;
2793 	u8	reserved1[11];
2794 };
2795 
2796 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2797 
2798 struct i40e_aqc_get_set_rss_key {
2799 #define I40E_AQC_SET_RSS_KEY_VSI_VALID		(0x1 << 15)
2800 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT	0
2801 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK	(0x3FF << \
2802 					I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2803 	__le16	vsi_id;
2804 	u8	reserved[6];
2805 	__le32	addr_high;
2806 	__le32	addr_low;
2807 };
2808 
2809 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
2810 
2811 struct i40e_aqc_get_set_rss_key_data {
2812 	u8 standard_rss_key[0x28];
2813 	u8 extended_hash_key[0xc];
2814 };
2815 
2816 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2817 
2818 struct  i40e_aqc_get_set_rss_lut {
2819 #define I40E_AQC_SET_RSS_LUT_VSI_VALID		(0x1 << 15)
2820 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT	0
2821 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK	(0x3FF << \
2822 					I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2823 	__le16	vsi_id;
2824 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT	0
2825 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK	(0x1 << \
2826 					I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2827 
2828 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI	0
2829 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF	1
2830 	__le16	flags;
2831 	u8	reserved[4];
2832 	__le32	addr_high;
2833 	__le32	addr_low;
2834 };
2835 
2836 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
2837 
2838 /* tunnel key structure 0x0B10 */
2839 
2840 struct i40e_aqc_tunnel_key_structure {
2841 	u8	key1_off;
2842 	u8	key2_off;
2843 	u8	key1_len;  /* 0 to 15 */
2844 	u8	key2_len;  /* 0 to 15 */
2845 	u8	flags;
2846 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE	0x01
2847 /* response flags */
2848 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS	0x01
2849 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED	0x02
2850 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN	0x03
2851 	u8	network_key_index;
2852 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN		0x0
2853 #define I40E_AQC_NETWORK_KEY_INDEX_NGE			0x1
2854 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP	0x2
2855 #define I40E_AQC_NETWORK_KEY_INDEX_GRE			0x3
2856 	u8	reserved[10];
2857 };
2858 
2859 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2860 
2861 /* OEM mode commands (direct 0xFE0x) */
2862 struct i40e_aqc_oem_param_change {
2863 	__le32	param_type;
2864 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL	0
2865 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL	1
2866 #define I40E_AQ_OEM_PARAM_MAC		2
2867 	__le32	param_value1;
2868 	__le16	param_value2;
2869 	u8	reserved[6];
2870 };
2871 
2872 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2873 
2874 struct i40e_aqc_oem_state_change {
2875 	__le32	state;
2876 #define I40E_AQ_OEM_STATE_LINK_DOWN	0x0
2877 #define I40E_AQ_OEM_STATE_LINK_UP	0x1
2878 	u8	reserved[12];
2879 };
2880 
2881 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2882 
2883 /* Initialize OCSD (0xFE02, direct) */
2884 struct i40e_aqc_opc_oem_ocsd_initialize {
2885 	u8 type_status;
2886 	u8 reserved1[3];
2887 	__le32 ocsd_memory_block_addr_high;
2888 	__le32 ocsd_memory_block_addr_low;
2889 	__le32 requested_update_interval;
2890 };
2891 
2892 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2893 
2894 /* Initialize OCBB  (0xFE03, direct) */
2895 struct i40e_aqc_opc_oem_ocbb_initialize {
2896 	u8 type_status;
2897 	u8 reserved1[3];
2898 	__le32 ocbb_memory_block_addr_high;
2899 	__le32 ocbb_memory_block_addr_low;
2900 	u8 reserved2[4];
2901 };
2902 
2903 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2904 
2905 /* debug commands */
2906 
2907 /* get device id (0xFF00) uses the generic structure */
2908 
2909 /* set test more (0xFF01, internal) */
2910 
2911 struct i40e_acq_set_test_mode {
2912 	u8	mode;
2913 #define I40E_AQ_TEST_PARTIAL	0
2914 #define I40E_AQ_TEST_FULL	1
2915 #define I40E_AQ_TEST_NVM	2
2916 	u8	reserved[3];
2917 	u8	command;
2918 #define I40E_AQ_TEST_OPEN	0
2919 #define I40E_AQ_TEST_CLOSE	1
2920 #define I40E_AQ_TEST_INC	2
2921 	u8	reserved2[3];
2922 	__le32	address_high;
2923 	__le32	address_low;
2924 };
2925 
2926 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2927 
2928 /* Debug Read Register command (0xFF03)
2929  * Debug Write Register command (0xFF04)
2930  */
2931 struct i40e_aqc_debug_reg_read_write {
2932 	__le32 reserved;
2933 	__le32 address;
2934 	__le32 value_high;
2935 	__le32 value_low;
2936 };
2937 
2938 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2939 
2940 /* Scatter/gather Reg Read  (indirect 0xFF05)
2941  * Scatter/gather Reg Write (indirect 0xFF06)
2942  */
2943 
2944 /* i40e_aq_desc is used for the command */
2945 struct i40e_aqc_debug_reg_sg_element_data {
2946 	__le32 address;
2947 	__le32 value;
2948 };
2949 
2950 /* Debug Modify register (direct 0xFF07) */
2951 struct i40e_aqc_debug_modify_reg {
2952 	__le32 address;
2953 	__le32 value;
2954 	__le32 clear_mask;
2955 	__le32 set_mask;
2956 };
2957 
2958 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2959 
2960 /* dump internal data (0xFF08, indirect) */
2961 
2962 #define I40E_AQ_CLUSTER_ID_AUX		0
2963 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU	1
2964 #define I40E_AQ_CLUSTER_ID_TXSCHED	2
2965 #define I40E_AQ_CLUSTER_ID_HMC		3
2966 #define I40E_AQ_CLUSTER_ID_MAC0		4
2967 #define I40E_AQ_CLUSTER_ID_MAC1		5
2968 #define I40E_AQ_CLUSTER_ID_MAC2		6
2969 #define I40E_AQ_CLUSTER_ID_MAC3		7
2970 #define I40E_AQ_CLUSTER_ID_DCB		8
2971 #define I40E_AQ_CLUSTER_ID_EMP_MEM	9
2972 #define I40E_AQ_CLUSTER_ID_PKT_BUF	10
2973 #define I40E_AQ_CLUSTER_ID_ALTRAM	11
2974 
2975 struct i40e_aqc_debug_dump_internals {
2976 	u8	cluster_id;
2977 	u8	table_id;
2978 	__le16	data_size;
2979 	__le32	idx;
2980 	__le32	address_high;
2981 	__le32	address_low;
2982 };
2983 
2984 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2985 
2986 struct i40e_aqc_debug_modify_internals {
2987 	u8	cluster_id;
2988 	u8	cluster_specific_params[7];
2989 	__le32	address_high;
2990 	__le32	address_low;
2991 };
2992 
2993 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2994 
2995 #endif /* _I40E_ADMINQ_CMD_H_ */
2996