| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCopyToCombine.cpp | 799 Register HiReg = HiOperand.getReg(); in emitCombineRI() local
850 Register HiReg = HiOperand.getReg(); in emitCombineRR() local
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| H A D | HexagonFrameLowering.cpp | 1118 Register HiReg = HRI.getSubReg(Reg, Hexagon::isub_hi); in insertCFIInstructionsAt() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcAsmPrinter.cpp | 443 Register HiReg, LoReg; in PrintAsmOperand() local
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| H A D | SparcISelLowering.cpp | 1315 Register HiReg = VA.getLocReg(); in LowerCall_64() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVCallingConv.cpp | 501 MCRegister HiReg = State.AllocateReg(ArgGPRs); in CC_RISCV() local
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| H A D | RISCVISelLowering.cpp | 21296 Register HiReg = MI.getOperand(1).getReg(); in emitReadCounterWidePseudo() local
21335 Register HiReg = MI.getOperand(1).getReg(); in emitSplitF64Pseudo() local
21372 Register HiReg = MI.getOperand(2).getReg(); in emitBuildPairF64Pseudo() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.cpp | 798 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
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| H A D | MipsSEFrameLowering.cpp | 307 Register HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
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| H A D | MipsISelLowering.cpp | 3131 MCRegister HiReg = State.AllocateReg(IntRegs); in CC_MipsO32() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 1643 Register HiReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectBallot() local
2477 Register HiReg = MRI->createVirtualRegister(DstRC); in selectG_TRUNC() local
2669 Register HiReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_SZA_EXT() local
2834 Register HiReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_FNEG() local
2872 Register HiReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_FABS() local
3153 Register HiReg = MRI->createVirtualRegister(&RegRC); in selectG_PTRMASK() local
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| H A D | SILoadStoreOptimizer.cpp | 189 Register HiReg; member
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 2103 for (unsigned LoReg = ARM::R7, HiReg = ARM::R11; LoReg >= ARM::R4; in CMSEPushCalleeSaves() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 6232 Register HiReg = MI.getOperand(1).getReg(); in emitSplitPairF64Pseudo() local
6255 Register HiReg = MI.getOperand(2).getReg(); in emitBuildPairF64Pseudo() local
6776 MCRegister HiReg = State.AllocateReg(ArgGPRs); in CC_LoongArch() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 5779 unsigned LoReg, HiReg; in Select() local
5922 unsigned LoReg, HiReg, ClrReg; in Select() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 7495 MCRegister Reg, MCRegister HiReg, in checkLowRegisterList()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 13872 Register HiReg = MI.getOperand(1).getReg(); in EmitInstrWithCustomInserter() local
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