1 /* reset_reg_1 */ 2 #define MISC_REGISTERS_RESET_REG_1_SET 0x584 // MISC_REGISTERS_RESET_REG_1+4 3 #define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588 // MISC_REGISTERS_RESET_REG_1+8 4 #define MISC_REGISTERS_RESET_REG_1_RST_BRB1 (0x1<<0) 5 #define MISC_REGISTERS_RESET_REG_1_RST_PRS (0x1<<1) 6 #define MISC_REGISTERS_RESET_REG_1_RST_SRC (0x1<<2) 7 #define MISC_REGISTERS_RESET_REG_1_RST_TSDM (0x1<<3) 8 #define MISC_REGISTERS_RESET_REG_1_RST_TSEM (0x1<<4) 9 #define MISC_REGISTERS_RESET_REG_1_RST_TCM (0x1<<5) 10 #define MISC_REGISTERS_RESET_REG_1_RST_RBCR (0x1<<6) 11 #define MISC_REGISTERS_RESET_REG_1_RST_NIG (0x1<<7) 12 #define MISC_REGISTERS_RESET_REG_1_RST_USDM (0x1<<8) 13 #define MISC_REGISTERS_RESET_REG_1_RST_UCM (0x1<<9) 14 #define MISC_REGISTERS_RESET_REG_1_RST_USEM (0x1<<10) 15 #define MISC_REGISTERS_RESET_REG_1_RST_UPB (0x1<<11) 16 #define MISC_REGISTERS_RESET_REG_1_RST_CCM (0x1<<12) 17 #define MISC_REGISTERS_RESET_REG_1_RST_CSEM (0x1<<13) 18 #define MISC_REGISTERS_RESET_REG_1_RST_CSDM (0x1<<14) 19 #define MISC_REGISTERS_RESET_REG_1_RST_RBCU (0x1<<15) 20 #define MISC_REGISTERS_RESET_REG_1_RST_PBF (0x1<<16) 21 #define MISC_REGISTERS_RESET_REG_1_RST_QM (0x1<<17) 22 #define MISC_REGISTERS_RESET_REG_1_RST_TM (0x1<<18) 23 #define MISC_REGISTERS_RESET_REG_1_RST_DORQ (0x1<<19) 24 #define MISC_REGISTERS_RESET_REG_1_RST_XCM (0x1<<20) 25 #define MISC_REGISTERS_RESET_REG_1_RST_XSDM (0x1<<21) 26 #define MISC_REGISTERS_RESET_REG_1_RST_XSEM (0x1<<22) 27 #define MISC_REGISTERS_RESET_REG_1_RST_RBCT (0x1<<23) 28 #define MISC_REGISTERS_RESET_REG_1_RST_CDU (0x1<<24) 29 #define MISC_REGISTERS_RESET_REG_1_RST_CFC (0x1<<25) 30 #define MISC_REGISTERS_RESET_REG_1_RST_PXP (0x1<<26) 31 #define MISC_REGISTERS_RESET_REG_1_RST_PXPV (0x1<<27) 32 #define MISC_REGISTERS_RESET_REG_1_RST_RBCP (0x1<<28) 33 #define MISC_REGISTERS_RESET_REG_1_RST_HC (0x1<<29) 34 #define MISC_REGISTERS_RESET_REG_1_RST_DMAE (0x1<<30) 35 #define MISC_REGISTERS_RESET_REG_1_RST_SEMI_RTC (0x1<<31) 36 /* reset_reg_2 */ 37 #define MISC_REGISTERS_RESET_REG_2_SET 0x594 // MISC_REGISTERS_RESET_REG_2+4 38 #define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598 // MISC_REGISTERS_RESET_REG_2+8 39 #define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0) 40 #define MISC_REGISTERS_RESET_REG_2_RST_BMAC1 (0x1<<1) 41 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC0 (0x1<<2) 42 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC1 (0x1<<3) 43 #define MISC_REGISTERS_RESET_REG_2_RST_GRC (0x1<<4) //Global register 44 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1<<5) //Global register 45 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B (0x1<<6) //Global register 46 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU (0x1<<7) //Global register 47 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE (0x1<<8) //Global register 48 #define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1<<9) 49 #define MISC_REGISTERS_RESET_REG_2_RST_DBG (0x1<<10) 50 #define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE (0x1<<11) //Global register 51 #define MISC_REGISTERS_RESET_REG_2_RST_DBUE (0x1<<12) //Global register 52 #define MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO (0x1<<13) //Global register 53 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1<<14) 54 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE (0x1<<15) 55 #define MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR (0x1<<16) 56 #define MISC_REGISTERS_RESET_REG_2_RST_ATC (0x1<<17) 57 #define MISC_REGISTERS_RESET_REG_2_CNIG (0x1<<18) 58 #define MISC_REGISTERS_RESET_REG_2_PGLC (0x1<<19) //Global register 59 #define MISC_REGISTERS_RESET_REG_2_UMAC0 (0x1<<20) 60 #define MISC_REGISTERS_RESET_REG_2_UMAC1 (0x1<<21) 61 #define MISC_REGISTERS_RESET_REG_2_XMAC (0x1<<22) 62 #define MISC_REGISTERS_RESET_REG_2_XMAC_SOFT (0x1<<23) 63 #define MISC_REGISTERS_RESET_REG_2_MSTAT0 (0x1<<24) 64 #define MISC_REGISTERS_RESET_REG_2_MSTAT1 (0x1<<25) 65 66 /* reset_reg_3 */ 67 #define MISC_REGISTERS_RESET_REG_3_SET 0x5a4 // MISC_REGISTERS_RESET_REG_3+4 68 #define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8 // MISC_REGISTERS_RESET_REG_3+8 69 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0) //(NIG - Reset Controls to SERDES0) 70 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1) //(NIG - Reset Controls to SERDES0) 71 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2) //(NIG - Reset Controls to SERDES0) 72 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3) //(NIG - Reset Controls to SERDES0) 73 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4) //(NIG - Reset Controls to XGXS 0) 74 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5) //(NIG - Reset Controls to XGXS 0) 75 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6) //(NIG - Reset Controls to XGXS 0) 76 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7) //(NIG - Reset Controls to XGXS 0) 77 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8) //(NIG - Reset Controls to XGXS 0) 78 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES1_RSTB_HW (0x1<<16) //(NIG - Reset Controls to SERDES1) 79 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES1_IDDQ (0x1<<17) //(NIG - Reset Controls to SERDES1) 80 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES1_PWRDWN (0x1<<18) //(NIG - Reset Controls to SERDES1) 81 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES1_PWRDWN_SD (0x1<<19) //(NIG - Reset Controls to SERDES1) 82 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS1_RSTB_HW (0x1<<20) //(NIG - Reset Controls to XGXS 1) 83 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS1_IDDQ (0x1<<21) //(NIG - Reset Controls to XGXS 1) 84 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS1_PWRDWN (0x1<<22) //(NIG - Reset Controls to XGXS 1) 85 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS1_PWRDWN_SD (0x1<<23) //(NIG - Reset Controls to XGXS 1) 86 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS1_TXD_FIFO_RSTB (0x1<<24) //(NIG - Reset Controls to XGXS 1) 87 /*reset_config*/ 88 #define MISC_REGISTERS_RESET_CONFIG_VREGPNP_BG_2A_EN (0x1<<0) 89 #define MISC_REGISTERS_RESET_CONFIG_VREGPNP_BG_8A_VMAIN_EN (0x1<<1) 90 #define MISC_REGISTERS_RESET_CONFIG_VREGPNP_BG_8A_VAUX_EN (0x1<<2) 91 #define MISC_REGISTERS_RESET_CONFIG_RST_PXP_AUTO_MODE (0x1<<3) 92 #define MISC_REGISTERS_RESET_CONFIG_RST_PGL_AUTO_MODE (0x1<<4) 93 #define MISC_REGISTERS_RESET_CONFIG_RST_RBCP_AUTO_MODE (0x1<<5) 94 #define MISC_REGISTERS_RESET_CONFIG_RST_GRC (0x1<<6) 95 #define MISC_REGISTERS_RESET_CONFIG_RST_MCP_N_RESET_REG_HARD_CORE_AUTO_MODE (0x1<<7) 96 #define MISC_REGISTERS_RESET_CONFIG_RST_MCP_N_HARD_CORE_RST_B_AUTO_MODE (0x1<<8) 97 #define MISC_REGISTERS_RESET_CONFIG_RST_MCP_N_RESET_CMN_CPU_AUTO_MODE (0x1<<9) 98 #define MISC_REGISTERS_RESET_CONFIG_RST_MCP_N_RESET_CMN_CORE_AUTO_MODE (0x1<<10) 99 #define MISC_REGISTERS_RESET_CONFIG_IDDQ_MCP (0x1<<11) 100 #define MISC_REGISTERS_RESET_CONFIG_RST_RBCN_AUTO_MODE (0x1<<12) 101 #define MISC_REGISTERS_RESET_CONFIG_RST_DBG_AUTO_MODE (0x1<<13) 102 #define MISC_REGISTERS_RESET_CONFIG_RST_MISC_CORE_AUTO_MODE (0x1<<14) 103 #define MISC_REGISTERS_RESET_CONFIG_RST_DBUE_AUTO_MODE (0x1<<15) 104 #define MISC_REGISTERS_RESET_CONFIG_GRC_RESET_ASSERT_ON_CORE_RST (0x1<<16) 105 #define MISC_REGISTERS_RESET_CONFIG_RST_MCP_N_RESET_CMN_CPU_ASSERT_ON_CORE_RST (0x1<<17) 106 #define MISC_REGISTERS_RESET_CONFIG_RST_MCP_N_RESET_CMN_CORE_ASSERT_ON_CORE_RST (0x1<<18) 107 #define MISC_REGISTERS_RESET_CONFIG_RST_RBCN_ASSERT_ON_CORE_RST (0x1<<19) 108 #define MISC_REGISTERS_RESET_CONFIG_RST_DBG_ASSERT_ON_CORE_RST (0x1<<20) 109 #define MISC_REGISTERS_RESET_CONFIG_RST_MISC_CORE_ASSERT_ON_CORE_RST (0x1<<21) 110 #define MISC_REGISTERS_RESET_CONFIG_RST_DBUE_ASSERT_ON_CORE_RST (0x1<<22) 111 #define MISC_REGISTERS_RESET_CONFIG_WRAPPERS_IDDQ_AND_RST_SIGNALS _ASSERT_ON_CORE_RST (0x1<<23) 112 113 /* voltage_register */ 114 #define MISC_REGISTERS_VOLTAGE_REG_MDIO_VOLTAGE_SEL_MASK (1L<<0) 115 #define MISC_REGISTERS_VOLTAGE_REG_MDIO_VOLTAGE_SEL_1_2V (0L<<0) 116 #define MISC_REGISTERS_VOLTAGE_REG_MDIO_VOLTAGE_SEL_2_5V (1L<<0) 117 118 // Definitions for GPIO 119 #define MISC_REGISTERS_GPIO_PORT_SHIFT 4 120 #define MISC_REGISTERS_GPIO_0 0 121 #define MISC_REGISTERS_GPIO_1 1 122 #define MISC_REGISTERS_GPIO_2 2 123 #define MISC_REGISTERS_GPIO_3 3 124 125 #define MISC_REGISTERS_GPIO_OUTPUT_LOW 0 126 #define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1 127 #define MISC_REGISTERS_GPIO_INPUT_HI_Z 2 128 129 #define MISC_REGISTERS_GPIO_VALUE (0xffL<<0) 130 #define MISC_REGISTERS_GPIO_VALUE_POS 0 131 #define MISC_REGISTERS_GPIO_SET (0xffL<<8) 132 #define MISC_REGISTERS_GPIO_SET_POS 8 133 #define MISC_REGISTERS_GPIO_CLR (0xffL<<16) 134 #define MISC_REGISTERS_GPIO_CLR_POS 16 135 #define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24) 136 #define MISC_REGISTERS_GPIO_FLOAT_POS 24 137 138 // Port 1 float pins are in bits 31-28 139 #define GRC_MISC_REGISTERS_GPIO_PORT1_FLOAT3 0x80000000 140 #define GRC_MISC_REGISTERS_GPIO_PORT1_FLOAT2 0x40000000 141 #define GRC_MISC_REGISTERS_GPIO_PORT1_FLOAT1 0x20000000 142 #define GRC_MISC_REGISTERS_GPIO_PORT1_FLOAT0 0x10000000 143 // Port 0 float pins are in bits 27-24 144 #define GRC_MISC_REGISTERS_GPIO_PORT0_FLOAT3 0x08000000 145 #define GRC_MISC_REGISTERS_GPIO_PORT0_FLOAT2 0x04000000 146 #define GRC_MISC_REGISTERS_GPIO_PORT0_FLOAT1 0x02000000 147 #define GRC_MISC_REGISTERS_GPIO_PORT0_FLOAT0 0x01000000 148 149 #define MISC_REGISTERS_GPIO_OUTPUT 1 150 #define MISC_REGISTERS_GPIO_INTPUT 0 151 #define MISC_REGISTERS_GPIO_HIGH 1 152 #define MISC_REGISTERS_GPIO_LOW 0 153 // Port 1 output enable pins are in bits 31-28 154 #define GRC_MISC_REGISTERS_GPIO_PORT1_OE3 0x80000000 155 #define GRC_MISC_REGISTERS_GPIO_PORT1_OE2 0x40000000 156 #define GRC_MISC_REGISTERS_GPIO_PORT1_OE1 0x20000000 157 #define GRC_MISC_REGISTERS_GPIO_PORT1_OE0 0x10000000 158 // Port 0 output enable pins are in bits 27-24 159 #define GRC_MISC_REGISTERS_GPIO_PORT0_OE3 0x08000000 160 #define GRC_MISC_REGISTERS_GPIO_PORT0_OE2 0x04000000 161 #define GRC_MISC_REGISTERS_GPIO_PORT0_OE1 0x02000000 162 #define GRC_MISC_REGISTERS_GPIO_PORT0_OE0 0x01000000 163 // Port 1 CLR pins are in bits 23-20 164 #define GRC_MISC_REGISTERS_GPIO_PORT1_CLR3 0x00800000 165 #define GRC_MISC_REGISTERS_GPIO_PORT1_CLR2 0x00400000 166 #define GRC_MISC_REGISTERS_GPIO_PORT1_CLR1 0x00200000 167 #define GRC_MISC_REGISTERS_GPIO_PORT1_CLR0 0x00100000 168 // Port 0 CLR pins are in bits 19-16 169 #define GRC_MISC_REGISTERS_GPIO_PORT0_CLR3 0x00080000 170 #define GRC_MISC_REGISTERS_GPIO_PORT0_CLR2 0x00040000 171 #define GRC_MISC_REGISTERS_GPIO_PORT0_CLR1 0x00020000 172 #define GRC_MISC_REGISTERS_GPIO_PORT0_CLR0 0x00010000 173 // Port 1 SET pins are in bits 15-12 174 #define GRC_MISC_REGISTERS_GPIO_PORT1_SET3 0x00008000 175 #define GRC_MISC_REGISTERS_GPIO_PORT1_SET2 0x00004000 176 #define GRC_MISC_REGISTERS_GPIO_PORT1_SET1 0x00002000 177 #define GRC_MISC_REGISTERS_GPIO_PORT1_SET0 0x00001000 178 // Port 0 SET pins are in bits 11-8 179 #define GRC_MISC_REGISTERS_GPIO_PORT0_SET3 0x00000800 180 #define GRC_MISC_REGISTERS_GPIO_PORT0_SET2 0x00000400 181 #define GRC_MISC_REGISTERS_GPIO_PORT0_SET1 0x00000200 182 #define GRC_MISC_REGISTERS_GPIO_PORT0_SET0 0x00000100 183 // Port 1 pin values are in bits 7-4 184 #define GRC_MISC_REGISTERS_GPIO_PORT1_VAL3 0x00000080 185 #define GRC_MISC_REGISTERS_GPIO_PORT1_VAL2 0x00000040 186 #define GRC_MISC_REGISTERS_GPIO_PORT1_VAL1 0x00000020 187 #define GRC_MISC_REGISTERS_GPIO_PORT1_VAL0 0x00000010 188 // Port 0 pin values are in bits 3-0 189 #define GRC_MISC_REGISTERS_GPIO_PORT0_VAL3 0x00000008 190 #define GRC_MISC_REGISTERS_GPIO_PORT0_VAL2 0x00000004 191 #define GRC_MISC_REGISTERS_GPIO_PORT0_VAL1 0x00000002 192 #define GRC_MISC_REGISTERS_GPIO_PORT0_VAL0 0x00000001 193 194 // Definitions for SPIO 195 #define MISC_SPIO_OUTPUT_LOW 0 196 #define MISC_SPIO_OUTPUT_HIGH 1 197 #define MISC_SPIO_INPUT_HI_Z 2 198 199 #define MISC_SPIO_VALUE (0xffL<<0) 200 #define MISC_SPIO_VALUE_POS 0 201 #define MISC_SPIO_SET (0xffL<<8) 202 #define MISC_SPIO_SET_POS 8 203 #define MISC_SPIO_CLR (0xffL<<16) 204 #define MISC_SPIO_CLR_POS 16 205 #define MISC_SPIO_FLOAT (0xffL<<24) 206 #define MISC_SPIO_FLOAT_POS 24 207 208 #define MISC_SPIO_INT_INT_STATE_POS 0 209 #define MISC_SPIO_INT_OLD_VALUE_POS 8 210 #define MISC_SPIO_INT_OLD_SET_POS 16 211 #define MISC_SPIO_INT_OLD_CLR_POS 24 212 213 // SPIO pin assignment 214 #define MISC_SPIO_EN_VAUX_L 0x01 // SPIO 0 215 #define MISC_SPIO_DIS_VAUX_L 0x02 // SPIO 1 216 #define MISC_SPIO_SEL_VAUX_L 0x04 // SPIO 2 Control to power switching logic 217 #define MISC_SPIO_PORT_SWAP 0x08 // SPIO 3 218 #define MISC_SPIO_SPIO4 0x10 // SPIO 4 (MFW_SELECT) 219 #define MISC_SPIO_SPIO5 0x20 // SPIO 5 ==> Output (SMALERT) 220 #define MISC_SPIO_UMP_ADDR0 0x40 // SPIO 6 <== Input Bit 0 of UMP device ID select 221 #define MISC_SPIO_UMP_ADDR1 0x80 // SPIO 7 <== Input Bit 1 of UMP device ID select 222 223 // Gpio int 224 #define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR 0 225 #define MISC_REGISTERS_GPIO_INT_OUTPUT_SET 1 226 227 #define MISC_REGISTERS_GPIO_INT_INT_STATUS_MASK (0xffL<<0) 228 #define MISC_REGISTERS_GPIO_INT_INT_STATUS_POS 0 229 #define MISC_REGISTERS_GPIO_INT_OLD_VAL_MASK (0xffL<<8) 230 #define MISC_REGISTERS_GPIO_INT_OLD_VAL_POS 8 231 #define MISC_REGISTERS_GPIO_INT_SET_MASK (0xffL<<16) 232 #define MISC_REGISTERS_GPIO_INT_SET_POS 16 233 #define MISC_REGISTERS_GPIO_INT_CLR_MASK (0xffL<<24) 234 #define MISC_REGISTERS_GPIO_INT_CLR_POS 24 235 236 // [31-28] OLD_CLR port1, [27-24] OLD_CLR port0: Writing a '1' to 237 // these bits clears the corresponding bit in the OLD_VALUE 238 // register. This will acknowledge an interrupt on the falling edge of 239 // corresponding GPIO input (reset value 0). 240 // [31-28] OLD_CLR port1 241 #define GRC_MISC_REGISTERS_GPIO_INT_PORT1_CLR3 0x80000000 242 #define GRC_MISC_REGISTERS_GPIO_INT_PORT1_CLR2 0x40000000 243 #define GRC_MISC_REGISTERS_GPIO_INT_PORT1_CLR1 0x20000000 244 #define GRC_MISC_REGISTERS_GPIO_INT_PORT1_CLR0 0x10000000 245 // [27-24] OLD_CLR port0 246 #define GRC_MISC_REGISTERS_GPIO_INT_PORT0_CLR3 0x08000000 247 #define GRC_MISC_REGISTERS_GPIO_INT_PORT0_CLR2 0x04000000 248 #define GRC_MISC_REGISTERS_GPIO_INT_PORT0_CLR1 0x02000000 249 #define GRC_MISC_REGISTERS_GPIO_INT_PORT0_CLR0 0x01000000 250 251 //[23-20] OLD_SET port1, [19-16] OLD_SET port0: Writing a '1' to 252 //these bit sets the corresponding bit in the OLD_VALUE register. 253 //This will acknowledge an interrupt on the rising edge of 254 //corresponding GPIO input (reset value 0). 255 // [23-20] OLD_SET port1 256 #define GRC_MISC_REGISTERS_GPIO_INT_PORT1_SET3 0x00800000 257 #define GRC_MISC_REGISTERS_GPIO_INT_PORT1_SET2 0x00400000 258 #define GRC_MISC_REGISTERS_GPIO_INT_PORT1_SET1 0x00200000 259 #define GRC_MISC_REGISTERS_GPIO_INT_PORT1_SET0 0x00100000 260 // [19-16] OLD_SET port0 261 #define GRC_MISC_REGISTERS_GPIO_INT_PORT0_SET3 0x00080000 262 #define GRC_MISC_REGISTERS_GPIO_INT_PORT0_SET2 0x00040000 263 #define GRC_MISC_REGISTERS_GPIO_INT_PORT0_SET1 0x00020000 264 #define GRC_MISC_REGISTERS_GPIO_INT_PORT0_SET0 0x00010000 265 266 //[15-12] OLD_VALUE port1, [11-8] OLD_VALUE port0 (RO field): 267 //These bits indicate the old value of the GPIO input value. When the 268 //INT_STATE bit is set; this bit indicates the OLD value of the pin 269 //such that if INT_STATE is set and this bit is '0'; then the interrupt is 270 //due to a low to high edge. If INT_STATE is set and this bit is '1'; 271 //then the interrupt is due to a high to low edge (reset value 0xX). 272 273 // [15-12] OLD_VALUE port1 274 #define GRC_MISC_REGISTERS_GPIO_INT_PORT1_OLD_VAL3 0x00008000 275 #define GRC_MISC_REGISTERS_GPIO_INT_PORT1_OLD_VAL2 0x00004000 276 #define GRC_MISC_REGISTERS_GPIO_INT_PORT1_OLD_VAL1 0x00002000 277 #define GRC_MISC_REGISTERS_GPIO_INT_PORT1_OLD_VAL0 0x00001000 278 // [11-8] OLD_VALUE port0 279 #define GRC_MISC_REGISTERS_GPIO_INT_PORT0_OLD_VAL3 0x00000800 280 #define GRC_MISC_REGISTERS_GPIO_INT_PORT0_OLD_VAL2 0x00000400 281 #define GRC_MISC_REGISTERS_GPIO_INT_PORT0_OLD_VAL1 0x00000200 282 #define GRC_MISC_REGISTERS_GPIO_INT_PORT0_OLD_VAL0 0x00000100 283 284 //[7-4] INT_STATE port1, [3-0] INT_STATE port0 (RO field): These 285 //bits indicate the current GPIO interrupt state for each GPIO pin. 286 //This bit is cleared when the appropriate OLD_SET or OLD_CLR 287 //command bit is written. This bit is set when the GPIO input does 288 //not match the current value in OLD_VALUE (reset value 0xX). 289 // [7-4] INT_STATE port1 290 #define GRC_MISC_REGISTERS_GPIO_INT_PORT1_INT_STATE3 0x00000080 291 #define GRC_MISC_REGISTERS_GPIO_INT_PORT1_INT_STATE2 0x00000040 292 #define GRC_MISC_REGISTERS_GPIO_INT_PORT1_INT_STATE1 0x00000020 293 #define GRC_MISC_REGISTERS_GPIO_INT_PORT1_INT_STATE0 0x00000010 294 // [3-0] INT_STATE port0 295 #define GRC_MISC_REGISTERS_GPIO_INT_PORT0_INT_STATE3 0x00000008 296 #define GRC_MISC_REGISTERS_GPIO_INT_PORT0_INT_STATE2 0x00000004 297 #define GRC_MISC_REGISTERS_GPIO_INT_PORT0_INT_STATE1 0x00000002 298 #define GRC_MISC_REGISTERS_GPIO_INT_PORT0_INT_STATE0 0x00000001 299 300 // EPIO 301 // E3 Pins Type SFP+ I/F Pins Notes 302 // P0_SIG_DET I P0_RX_LOS Port 0 receiver loss detection 303 // EPIO_16 I P0_MOD_ABS Port 0 module absent 304 // EPIO_17 I P0_TX_FAULT Port 0 transmission fault 305 // EPIO_18 O P0_TX_DIS Port 0 transmitter laser disable 306 // P1_SIG_DET I P1_RX_LOS Port 1 receiver loss detection 307 // EPIO_19 I P1_MOD_ABS Port 1 module absent 308 // EPIO_20 I P1_TX_FAULT Port 1 transmission fault 309 // EPIO_21 O P1_TX_DIS Port 1 transmitter laser disable 310 // P2_SIG_DET I P2_RX_LOS Port 2 receiver loss detection 311 // EPIO_22 I P2_MOD_ABS Port 2 module absent 312 // EPIO_23 I P2_TX_FAULT Port 2 transmission fault 313 // EPIO_24 O P2_TX_DIS Port 2 transmitter laser disable 314 // P3_SIG_DET I P3_RX_LOS Port 3 receiver loss detection 315 // EPIO_25 I P3_MOD_ABS Port 3 module absent 316 // EPIO_26 I P3_TX_FAULT Port 3 transmission fault 317 // EPIO_27 O P3_TX_DIS Port 3 transmitter laser disable 318 // EPIO_28 O BSC_SEL_0 BSC port select 0 319 // EPIO_29 O BSC_SEL_1 BSC port select 1 320 // BSC_SCL I/O BSC_SCL BSC clock 321 // BSC_SDA I/O BSC_SDA BSC data 322 323 ///////////////////////// 324 // HW Lock Definitions // 325 ///////////////////////// 326 327 // Masters 328 #define HW_LOCK_MASTER_FUNC_0 0 329 #define HW_LOCK_MASTER_FUNC_1 1 330 #define HW_LOCK_MASTER_FUNC_2 2 331 #define HW_LOCK_MASTER_FUNC_3 3 332 #define HW_LOCK_MASTER_FUNC_4 4 333 #define HW_LOCK_MASTER_FUNC_5 5 334 #define HW_LOCK_MASTER_FUNC_6 6 335 #define HW_LOCK_MASTER_FUNC_7 7 336 #define HW_LOCK_MASTER_RESERVED_8 8 337 #define HW_LOCK_MASTER_RESERVED_9 9 338 #define HW_LOCK_MASTER_RESERVED_10 10 339 #define HW_LOCK_MASTER_RESERVED_11 11 340 #define HW_LOCK_MASTER_RESERVED_12 12 341 #define HW_LOCK_MASTER_HOST_SCRIPTS 13 342 #define HW_LOCK_MASTER_MCP_RESET 14 343 #define HW_LOCK_MASTER_MCP 15 344 345 // Resources 346 #define HW_LOCK_RESOURCE_MDIO 0 347 #define HW_LOCK_RESOURCE_GPIO 1 348 #define HW_LOCK_RESOURCE_SPIO 2 349 #define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3 350 #define HW_LOCK_RESOURCE_PORT1_ATT_MASK 4 351 #define HW_LOCK_RESOURCE_RESET 5 352 #define HW_LOCK_RESOURCE_PORT0_DMAE_COPY_CMD 6 353 #define HW_LOCK_RESOURCE_PORT1_DMAE_COPY_CMD 7 354 #define HW_LOCK_RESOURCE_RECOVERY_LEADER_0 8 355 #define HW_LOCK_RESOURCE_RECOVERY_LEADER_1 9 356 #define HW_LOCK_RESOURCE_DRV_FLAGS 10 357 #define HW_LOCK_RESOURCE_RECOVERY_REG 11 358 #define HW_LOCK_RESOURCE_NVRAM 12 359 #define HW_LOCK_RESOURCE_DCBX_ADMIN_MIB 13 360 #define HW_LOCK_RESOURCE_SMBUS 14 361 #define HW_LOCK_RESOURCE_RESERVED_15 15 362 #define HW_LOCK_RESOURCE_RESERVED_16 16 363 #define HW_LOCK_RESOURCE_RESERVED_17 17 364 #define HW_LOCK_RESOURCE_RESERVED_18 18 365 #define HW_LOCK_RESOURCE_RESERVED_19 19 366 #define HW_LOCK_RESOURCE_RESERVED_20 20 367 #define HW_LOCK_RESOURCE_RESERVED_21 21 368 #define HW_LOCK_RESOURCE_RESERVED_22 22 369 #define HW_LOCK_RESOURCE_RESERVED_23 23 370 #define HW_LOCK_RESOURCE_RESERVED_24 24 371 #define HW_LOCK_RESOURCE_RESERVED_25 25 372 #define HW_LOCK_RESOURCE_RESERVED_26 26 373 #define HW_LOCK_RESOURCE_OEM_0 27 374 #define HW_LOCK_RESOURCE_OEM_1 28 375 #define HW_LOCK_RESOURCE_OEM_2 29 376 #define HW_LOCK_RESOURCE_OEM_3 30 377 #define HW_LOCK_RESOURCE_OEM_4 31 378 #define HW_LOCK_MAX_RESOURCE_VALUE 31 379