1 /* $OpenBSD: hifn7751.c,v 1.120 2002/05/17 00:33:34 deraadt Exp $ */
2
3 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 * Invertex AEON / Hifn 7751 driver
7 * Copyright (c) 1999 Invertex Inc. All rights reserved.
8 * Copyright (c) 1999 Theo de Raadt
9 * Copyright (c) 2000-2001 Network Security Technologies, Inc.
10 * http://www.netsec.net
11 * Copyright (c) 2003 Hifn Inc.
12 *
13 * This driver is based on a previous driver by Invertex, for which they
14 * requested: Please send any comments, feedback, bug-fixes, or feature
15 * requests to software@invertex.com.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
19 * are met:
20 *
21 * 1. Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution.
26 * 3. The name of the author may not be used to endorse or promote products
27 * derived from this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
30 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
31 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
32 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
33 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
34 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
38 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Effort sponsored in part by the Defense Advanced Research Projects
41 * Agency (DARPA) and Air Force Research Laboratory, Air Force
42 * Materiel Command, USAF, under agreement number F30602-01-2-0537.
43 */
44
45 #include <sys/cdefs.h>
46 /*
47 * Driver for various Hifn encryption processors.
48 */
49 #include "opt_hifn.h"
50
51 #include <sys/param.h>
52 #include <sys/systm.h>
53 #include <sys/proc.h>
54 #include <sys/errno.h>
55 #include <sys/malloc.h>
56 #include <sys/kernel.h>
57 #include <sys/module.h>
58 #include <sys/mbuf.h>
59 #include <sys/lock.h>
60 #include <sys/mutex.h>
61 #include <sys/sysctl.h>
62 #include <sys/uio.h>
63
64 #include <vm/vm.h>
65 #include <vm/pmap.h>
66
67 #include <machine/bus.h>
68 #include <machine/resource.h>
69 #include <sys/bus.h>
70 #include <sys/rman.h>
71
72 #include <opencrypto/cryptodev.h>
73 #include <opencrypto/xform_auth.h>
74 #include <sys/random.h>
75 #include <sys/kobj.h>
76
77 #include "cryptodev_if.h"
78
79 #include <dev/pci/pcivar.h>
80 #include <dev/pci/pcireg.h>
81
82 #ifdef HIFN_RNDTEST
83 #include <dev/rndtest/rndtest.h>
84 #endif
85 #include <dev/hifn/hifn7751reg.h>
86 #include <dev/hifn/hifn7751var.h>
87
88 #ifdef HIFN_VULCANDEV
89 #include <sys/conf.h>
90 #include <sys/uio.h>
91
92 static struct cdevsw vulcanpk_cdevsw; /* forward declaration */
93 #endif
94
95 /*
96 * Prototypes and count for the pci_device structure
97 */
98 static int hifn_probe(device_t);
99 static int hifn_attach(device_t);
100 static int hifn_detach(device_t);
101 static int hifn_suspend(device_t);
102 static int hifn_resume(device_t);
103 static int hifn_shutdown(device_t);
104
105 static int hifn_probesession(device_t, const struct crypto_session_params *);
106 static int hifn_newsession(device_t, crypto_session_t,
107 const struct crypto_session_params *);
108 static int hifn_process(device_t, struct cryptop *, int);
109
110 static device_method_t hifn_methods[] = {
111 /* Device interface */
112 DEVMETHOD(device_probe, hifn_probe),
113 DEVMETHOD(device_attach, hifn_attach),
114 DEVMETHOD(device_detach, hifn_detach),
115 DEVMETHOD(device_suspend, hifn_suspend),
116 DEVMETHOD(device_resume, hifn_resume),
117 DEVMETHOD(device_shutdown, hifn_shutdown),
118
119 /* crypto device methods */
120 DEVMETHOD(cryptodev_probesession, hifn_probesession),
121 DEVMETHOD(cryptodev_newsession, hifn_newsession),
122 DEVMETHOD(cryptodev_process, hifn_process),
123
124 DEVMETHOD_END
125 };
126
127 static driver_t hifn_driver = {
128 "hifn",
129 hifn_methods,
130 sizeof (struct hifn_softc)
131 };
132
133 DRIVER_MODULE(hifn, pci, hifn_driver, 0, 0);
134 MODULE_DEPEND(hifn, crypto, 1, 1, 1);
135 #ifdef HIFN_RNDTEST
136 MODULE_DEPEND(hifn, rndtest, 1, 1, 1);
137 #endif
138
139 static void hifn_reset_board(struct hifn_softc *, int);
140 static void hifn_reset_puc(struct hifn_softc *);
141 static void hifn_puc_wait(struct hifn_softc *);
142 static int hifn_enable_crypto(struct hifn_softc *);
143 static void hifn_set_retry(struct hifn_softc *sc);
144 static void hifn_init_dma(struct hifn_softc *);
145 static void hifn_init_pci_registers(struct hifn_softc *);
146 static int hifn_sramsize(struct hifn_softc *);
147 static int hifn_dramsize(struct hifn_softc *);
148 static int hifn_ramtype(struct hifn_softc *);
149 static void hifn_sessions(struct hifn_softc *);
150 static void hifn_intr(void *);
151 static u_int hifn_write_command(struct hifn_command *, u_int8_t *);
152 static u_int32_t hifn_next_signature(u_int32_t a, u_int cnt);
153 static void hifn_callback(struct hifn_softc *, struct hifn_command *, u_int8_t *);
154 static int hifn_crypto(struct hifn_softc *, struct hifn_command *, struct cryptop *, int);
155 static int hifn_readramaddr(struct hifn_softc *, int, u_int8_t *);
156 static int hifn_writeramaddr(struct hifn_softc *, int, u_int8_t *);
157 static int hifn_dmamap_load_src(struct hifn_softc *, struct hifn_command *);
158 static int hifn_dmamap_load_dst(struct hifn_softc *, struct hifn_command *);
159 static int hifn_init_pubrng(struct hifn_softc *);
160 static void hifn_rng(void *);
161 static void hifn_tick(void *);
162 static void hifn_abort(struct hifn_softc *);
163 static void hifn_alloc_slot(struct hifn_softc *, int *, int *, int *, int *);
164
165 static void hifn_write_reg_0(struct hifn_softc *, bus_size_t, u_int32_t);
166 static void hifn_write_reg_1(struct hifn_softc *, bus_size_t, u_int32_t);
167
168 static __inline u_int32_t
READ_REG_0(struct hifn_softc * sc,bus_size_t reg)169 READ_REG_0(struct hifn_softc *sc, bus_size_t reg)
170 {
171 u_int32_t v = bus_space_read_4(sc->sc_st0, sc->sc_sh0, reg);
172 sc->sc_bar0_lastreg = (bus_size_t) -1;
173 return (v);
174 }
175 #define WRITE_REG_0(sc, reg, val) hifn_write_reg_0(sc, reg, val)
176
177 static __inline u_int32_t
READ_REG_1(struct hifn_softc * sc,bus_size_t reg)178 READ_REG_1(struct hifn_softc *sc, bus_size_t reg)
179 {
180 u_int32_t v = bus_space_read_4(sc->sc_st1, sc->sc_sh1, reg);
181 sc->sc_bar1_lastreg = (bus_size_t) -1;
182 return (v);
183 }
184 #define WRITE_REG_1(sc, reg, val) hifn_write_reg_1(sc, reg, val)
185
186 static SYSCTL_NODE(_hw, OID_AUTO, hifn, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
187 "Hifn driver parameters");
188
189 #ifdef HIFN_DEBUG
190 static int hifn_debug = 0;
191 SYSCTL_INT(_hw_hifn, OID_AUTO, debug, CTLFLAG_RW, &hifn_debug,
192 0, "control debugging msgs");
193 #endif
194
195 static struct hifn_stats hifnstats;
196 SYSCTL_STRUCT(_hw_hifn, OID_AUTO, stats, CTLFLAG_RD, &hifnstats,
197 hifn_stats, "driver statistics");
198 static int hifn_maxbatch = 1;
199 SYSCTL_INT(_hw_hifn, OID_AUTO, maxbatch, CTLFLAG_RW, &hifn_maxbatch,
200 0, "max ops to batch w/o interrupt");
201
202 /*
203 * Probe for a supported device. The PCI vendor and device
204 * IDs are used to detect devices we know how to handle.
205 */
206 static int
hifn_probe(device_t dev)207 hifn_probe(device_t dev)
208 {
209 if (pci_get_vendor(dev) == PCI_VENDOR_INVERTEX &&
210 pci_get_device(dev) == PCI_PRODUCT_INVERTEX_AEON)
211 return (BUS_PROBE_DEFAULT);
212 if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
213 (pci_get_device(dev) == PCI_PRODUCT_HIFN_7751 ||
214 pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 ||
215 pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 ||
216 pci_get_device(dev) == PCI_PRODUCT_HIFN_7956 ||
217 pci_get_device(dev) == PCI_PRODUCT_HIFN_7811))
218 return (BUS_PROBE_DEFAULT);
219 if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC &&
220 pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751)
221 return (BUS_PROBE_DEFAULT);
222 return (ENXIO);
223 }
224
225 static void
hifn_dmamap_cb(void * arg,bus_dma_segment_t * segs,int nseg,int error)226 hifn_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
227 {
228 bus_addr_t *paddr = (bus_addr_t*) arg;
229 *paddr = segs->ds_addr;
230 }
231
232 static const char*
hifn_partname(struct hifn_softc * sc)233 hifn_partname(struct hifn_softc *sc)
234 {
235 /* XXX sprintf numbers when not decoded */
236 switch (pci_get_vendor(sc->sc_dev)) {
237 case PCI_VENDOR_HIFN:
238 switch (pci_get_device(sc->sc_dev)) {
239 case PCI_PRODUCT_HIFN_6500: return "Hifn 6500";
240 case PCI_PRODUCT_HIFN_7751: return "Hifn 7751";
241 case PCI_PRODUCT_HIFN_7811: return "Hifn 7811";
242 case PCI_PRODUCT_HIFN_7951: return "Hifn 7951";
243 case PCI_PRODUCT_HIFN_7955: return "Hifn 7955";
244 case PCI_PRODUCT_HIFN_7956: return "Hifn 7956";
245 }
246 return "Hifn unknown-part";
247 case PCI_VENDOR_INVERTEX:
248 switch (pci_get_device(sc->sc_dev)) {
249 case PCI_PRODUCT_INVERTEX_AEON: return "Invertex AEON";
250 }
251 return "Invertex unknown-part";
252 case PCI_VENDOR_NETSEC:
253 switch (pci_get_device(sc->sc_dev)) {
254 case PCI_PRODUCT_NETSEC_7751: return "NetSec 7751";
255 }
256 return "NetSec unknown-part";
257 }
258 return "Unknown-vendor unknown-part";
259 }
260
261 static void
default_harvest(struct rndtest_state * rsp,void * buf,u_int count)262 default_harvest(struct rndtest_state *rsp, void *buf, u_int count)
263 {
264 /* MarkM: FIX!! Check that this does not swamp the harvester! */
265 random_harvest_queue(buf, count, RANDOM_PURE_HIFN);
266 }
267
268 static u_int
checkmaxmin(device_t dev,const char * what,u_int v,u_int min,u_int max)269 checkmaxmin(device_t dev, const char *what, u_int v, u_int min, u_int max)
270 {
271 if (v > max) {
272 device_printf(dev, "Warning, %s %u out of range, "
273 "using max %u\n", what, v, max);
274 v = max;
275 } else if (v < min) {
276 device_printf(dev, "Warning, %s %u out of range, "
277 "using min %u\n", what, v, min);
278 v = min;
279 }
280 return v;
281 }
282
283 /*
284 * Select PLL configuration for 795x parts. This is complicated in
285 * that we cannot determine the optimal parameters without user input.
286 * The reference clock is derived from an external clock through a
287 * multiplier. The external clock is either the host bus (i.e. PCI)
288 * or an external clock generator. When using the PCI bus we assume
289 * the clock is either 33 or 66 MHz; for an external source we cannot
290 * tell the speed.
291 *
292 * PLL configuration is done with a string: "pci" for PCI bus, or "ext"
293 * for an external source, followed by the frequency. We calculate
294 * the appropriate multiplier and PLL register contents accordingly.
295 * When no configuration is given we default to "pci66" since that
296 * always will allow the card to work. If a card is using the PCI
297 * bus clock and in a 33MHz slot then it will be operating at half
298 * speed until the correct information is provided.
299 *
300 * We use a default setting of "ext66" because according to Mike Ham
301 * of HiFn, almost every board in existence has an external crystal
302 * populated at 66Mhz. Using PCI can be a problem on modern motherboards,
303 * because PCI33 can have clocks from 0 to 33Mhz, and some have
304 * non-PCI-compliant spread-spectrum clocks, which can confuse the pll.
305 */
306 static void
hifn_getpllconfig(device_t dev,u_int * pll)307 hifn_getpllconfig(device_t dev, u_int *pll)
308 {
309 const char *pllspec;
310 u_int freq, mul, fl, fh;
311 u_int32_t pllconfig;
312 char *nxt;
313
314 if (resource_string_value("hifn", device_get_unit(dev),
315 "pllconfig", &pllspec))
316 pllspec = "ext66";
317 fl = 33, fh = 66;
318 pllconfig = 0;
319 if (strncmp(pllspec, "ext", 3) == 0) {
320 pllspec += 3;
321 pllconfig |= HIFN_PLL_REF_SEL;
322 switch (pci_get_device(dev)) {
323 case PCI_PRODUCT_HIFN_7955:
324 case PCI_PRODUCT_HIFN_7956:
325 fl = 20, fh = 100;
326 break;
327 #ifdef notyet
328 case PCI_PRODUCT_HIFN_7954:
329 fl = 20, fh = 66;
330 break;
331 #endif
332 }
333 } else if (strncmp(pllspec, "pci", 3) == 0)
334 pllspec += 3;
335 freq = strtoul(pllspec, &nxt, 10);
336 if (nxt == pllspec)
337 freq = 66;
338 else
339 freq = checkmaxmin(dev, "frequency", freq, fl, fh);
340 /*
341 * Calculate multiplier. We target a Fck of 266 MHz,
342 * allowing only even values, possibly rounded down.
343 * Multipliers > 8 must set the charge pump current.
344 */
345 mul = checkmaxmin(dev, "PLL divisor", (266 / freq) &~ 1, 2, 12);
346 pllconfig |= (mul / 2 - 1) << HIFN_PLL_ND_SHIFT;
347 if (mul > 8)
348 pllconfig |= HIFN_PLL_IS;
349 *pll = pllconfig;
350 }
351
352 /*
353 * Attach an interface that successfully probed.
354 */
355 static int
hifn_attach(device_t dev)356 hifn_attach(device_t dev)
357 {
358 struct hifn_softc *sc = device_get_softc(dev);
359 caddr_t kva;
360 int rseg, rid;
361 char rbase;
362 uint16_t rev;
363
364 sc->sc_dev = dev;
365
366 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), "hifn driver", MTX_DEF);
367
368 /* XXX handle power management */
369
370 /*
371 * The 7951 and 795x have a random number generator and
372 * public key support; note this.
373 */
374 if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
375 (pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 ||
376 pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 ||
377 pci_get_device(dev) == PCI_PRODUCT_HIFN_7956))
378 sc->sc_flags = HIFN_HAS_RNG | HIFN_HAS_PUBLIC;
379 /*
380 * The 7811 has a random number generator and
381 * we also note it's identity 'cuz of some quirks.
382 */
383 if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
384 pci_get_device(dev) == PCI_PRODUCT_HIFN_7811)
385 sc->sc_flags |= HIFN_IS_7811 | HIFN_HAS_RNG;
386
387 /*
388 * The 795x parts support AES.
389 */
390 if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
391 (pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 ||
392 pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) {
393 sc->sc_flags |= HIFN_IS_7956 | HIFN_HAS_AES;
394 /*
395 * Select PLL configuration. This depends on the
396 * bus and board design and must be manually configured
397 * if the default setting is unacceptable.
398 */
399 hifn_getpllconfig(dev, &sc->sc_pllconfig);
400 }
401
402 /*
403 * Setup PCI resources. Note that we record the bus
404 * tag and handle for each register mapping, this is
405 * used by the READ_REG_0, WRITE_REG_0, READ_REG_1,
406 * and WRITE_REG_1 macros throughout the driver.
407 */
408 pci_enable_busmaster(dev);
409
410 rid = HIFN_BAR0;
411 sc->sc_bar0res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
412 RF_ACTIVE);
413 if (sc->sc_bar0res == NULL) {
414 device_printf(dev, "cannot map bar%d register space\n", 0);
415 goto fail_pci;
416 }
417 sc->sc_st0 = rman_get_bustag(sc->sc_bar0res);
418 sc->sc_sh0 = rman_get_bushandle(sc->sc_bar0res);
419 sc->sc_bar0_lastreg = (bus_size_t) -1;
420
421 rid = HIFN_BAR1;
422 sc->sc_bar1res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
423 RF_ACTIVE);
424 if (sc->sc_bar1res == NULL) {
425 device_printf(dev, "cannot map bar%d register space\n", 1);
426 goto fail_io0;
427 }
428 sc->sc_st1 = rman_get_bustag(sc->sc_bar1res);
429 sc->sc_sh1 = rman_get_bushandle(sc->sc_bar1res);
430 sc->sc_bar1_lastreg = (bus_size_t) -1;
431
432 hifn_set_retry(sc);
433
434 /*
435 * Setup the area where the Hifn DMA's descriptors
436 * and associated data structures.
437 */
438 if (bus_dma_tag_create(bus_get_dma_tag(dev), /* PCI parent */
439 1, 0, /* alignment,boundary */
440 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
441 BUS_SPACE_MAXADDR, /* highaddr */
442 NULL, NULL, /* filter, filterarg */
443 HIFN_MAX_DMALEN, /* maxsize */
444 MAX_SCATTER, /* nsegments */
445 HIFN_MAX_SEGLEN, /* maxsegsize */
446 BUS_DMA_ALLOCNOW, /* flags */
447 NULL, /* lockfunc */
448 NULL, /* lockarg */
449 &sc->sc_dmat)) {
450 device_printf(dev, "cannot allocate DMA tag\n");
451 goto fail_io1;
452 }
453 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &sc->sc_dmamap)) {
454 device_printf(dev, "cannot create dma map\n");
455 bus_dma_tag_destroy(sc->sc_dmat);
456 goto fail_io1;
457 }
458 if (bus_dmamem_alloc(sc->sc_dmat, (void**) &kva, BUS_DMA_NOWAIT, &sc->sc_dmamap)) {
459 device_printf(dev, "cannot alloc dma buffer\n");
460 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap);
461 bus_dma_tag_destroy(sc->sc_dmat);
462 goto fail_io1;
463 }
464 if (bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, kva,
465 sizeof (*sc->sc_dma),
466 hifn_dmamap_cb, &sc->sc_dma_physaddr,
467 BUS_DMA_NOWAIT)) {
468 device_printf(dev, "cannot load dma map\n");
469 bus_dmamem_free(sc->sc_dmat, kva, sc->sc_dmamap);
470 bus_dma_tag_destroy(sc->sc_dmat);
471 goto fail_io1;
472 }
473 sc->sc_dma = (struct hifn_dma *)kva;
474 bzero(sc->sc_dma, sizeof(*sc->sc_dma));
475
476 KASSERT(sc->sc_st0 != 0, ("hifn_attach: null bar0 tag!"));
477 KASSERT(sc->sc_sh0 != 0, ("hifn_attach: null bar0 handle!"));
478 KASSERT(sc->sc_st1 != 0, ("hifn_attach: null bar1 tag!"));
479 KASSERT(sc->sc_sh1 != 0, ("hifn_attach: null bar1 handle!"));
480
481 /*
482 * Reset the board and do the ``secret handshake''
483 * to enable the crypto support. Then complete the
484 * initialization procedure by setting up the interrupt
485 * and hooking in to the system crypto support so we'll
486 * get used for system services like the crypto device,
487 * IPsec, RNG device, etc.
488 */
489 hifn_reset_board(sc, 0);
490
491 if (hifn_enable_crypto(sc) != 0) {
492 device_printf(dev, "crypto enabling failed\n");
493 goto fail_mem;
494 }
495 hifn_reset_puc(sc);
496
497 hifn_init_dma(sc);
498 hifn_init_pci_registers(sc);
499
500 /* XXX can't dynamically determine ram type for 795x; force dram */
501 if (sc->sc_flags & HIFN_IS_7956)
502 sc->sc_drammodel = 1;
503 else if (hifn_ramtype(sc))
504 goto fail_mem;
505
506 if (sc->sc_drammodel == 0)
507 hifn_sramsize(sc);
508 else
509 hifn_dramsize(sc);
510
511 /*
512 * Workaround for NetSec 7751 rev A: half ram size because two
513 * of the address lines were left floating
514 */
515 if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC &&
516 pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751 &&
517 pci_get_revid(dev) == 0x61) /*XXX???*/
518 sc->sc_ramsize >>= 1;
519
520 /*
521 * Arrange the interrupt line.
522 */
523 rid = 0;
524 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
525 RF_SHAREABLE|RF_ACTIVE);
526 if (sc->sc_irq == NULL) {
527 device_printf(dev, "could not map interrupt\n");
528 goto fail_mem;
529 }
530 /*
531 * NB: Network code assumes we are blocked with splimp()
532 * so make sure the IRQ is marked appropriately.
533 */
534 if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE,
535 NULL, hifn_intr, sc, &sc->sc_intrhand)) {
536 device_printf(dev, "could not setup interrupt\n");
537 goto fail_intr2;
538 }
539
540 hifn_sessions(sc);
541
542 /*
543 * NB: Keep only the low 16 bits; this masks the chip id
544 * from the 7951.
545 */
546 rev = READ_REG_1(sc, HIFN_1_REVID) & 0xffff;
547
548 rseg = sc->sc_ramsize / 1024;
549 rbase = 'K';
550 if (sc->sc_ramsize >= (1024 * 1024)) {
551 rbase = 'M';
552 rseg /= 1024;
553 }
554 device_printf(sc->sc_dev, "%s, rev %u, %d%cB %cram",
555 hifn_partname(sc), rev,
556 rseg, rbase, sc->sc_drammodel ? 'd' : 's');
557 if (sc->sc_flags & HIFN_IS_7956)
558 printf(", pll=0x%x<%s clk, %ux mult>",
559 sc->sc_pllconfig,
560 sc->sc_pllconfig & HIFN_PLL_REF_SEL ? "ext" : "pci",
561 2 + 2*((sc->sc_pllconfig & HIFN_PLL_ND) >> 11));
562 printf("\n");
563
564 WRITE_REG_0(sc, HIFN_0_PUCNFG,
565 READ_REG_0(sc, HIFN_0_PUCNFG) | HIFN_PUCNFG_CHIPID);
566 sc->sc_ena = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA;
567
568 switch (sc->sc_ena) {
569 case HIFN_PUSTAT_ENA_2:
570 case HIFN_PUSTAT_ENA_1:
571 sc->sc_cid = crypto_get_driverid(dev,
572 sizeof(struct hifn_session), CRYPTOCAP_F_HARDWARE);
573 if (sc->sc_cid < 0) {
574 device_printf(dev, "could not get crypto driver id\n");
575 goto fail_intr;
576 }
577 break;
578 }
579
580 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
581 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
582
583 if (sc->sc_flags & (HIFN_HAS_PUBLIC | HIFN_HAS_RNG))
584 hifn_init_pubrng(sc);
585
586 callout_init(&sc->sc_tickto, 1);
587 callout_reset(&sc->sc_tickto, hz, hifn_tick, sc);
588
589 return (0);
590
591 fail_intr:
592 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand);
593 fail_intr2:
594 /* XXX don't store rid */
595 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
596 fail_mem:
597 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap);
598 bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap);
599 bus_dma_tag_destroy(sc->sc_dmat);
600
601 /* Turn off DMA polling */
602 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
603 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
604 fail_io1:
605 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res);
606 fail_io0:
607 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res);
608 fail_pci:
609 mtx_destroy(&sc->sc_mtx);
610 return (ENXIO);
611 }
612
613 /*
614 * Detach an interface that successfully probed.
615 */
616 static int
hifn_detach(device_t dev)617 hifn_detach(device_t dev)
618 {
619 struct hifn_softc *sc = device_get_softc(dev);
620
621 KASSERT(sc != NULL, ("hifn_detach: null software carrier!"));
622
623 /* disable interrupts */
624 WRITE_REG_1(sc, HIFN_1_DMA_IER, 0);
625
626 /*XXX other resources */
627 callout_stop(&sc->sc_tickto);
628 callout_stop(&sc->sc_rngto);
629 #ifdef HIFN_RNDTEST
630 if (sc->sc_rndtest)
631 rndtest_detach(sc->sc_rndtest);
632 #endif
633
634 /* Turn off DMA polling */
635 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
636 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
637
638 crypto_unregister_all(sc->sc_cid);
639
640 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand);
641 /* XXX don't store rid */
642 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
643
644 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap);
645 bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap);
646 bus_dma_tag_destroy(sc->sc_dmat);
647
648 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res);
649 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res);
650
651 mtx_destroy(&sc->sc_mtx);
652
653 return (0);
654 }
655
656 /*
657 * Stop all chip I/O so that the kernel's probe routines don't
658 * get confused by errant DMAs when rebooting.
659 */
660 static int
hifn_shutdown(device_t dev)661 hifn_shutdown(device_t dev)
662 {
663 #ifdef notyet
664 hifn_stop(device_get_softc(dev));
665 #endif
666 return (0);
667 }
668
669 /*
670 * Device suspend routine. Stop the interface and save some PCI
671 * settings in case the BIOS doesn't restore them properly on
672 * resume.
673 */
674 static int
hifn_suspend(device_t dev)675 hifn_suspend(device_t dev)
676 {
677 struct hifn_softc *sc = device_get_softc(dev);
678 #ifdef notyet
679 hifn_stop(sc);
680 #endif
681 sc->sc_suspended = 1;
682
683 return (0);
684 }
685
686 /*
687 * Device resume routine. Restore some PCI settings in case the BIOS
688 * doesn't, re-enable busmastering, and restart the interface if
689 * appropriate.
690 */
691 static int
hifn_resume(device_t dev)692 hifn_resume(device_t dev)
693 {
694 struct hifn_softc *sc = device_get_softc(dev);
695 #ifdef notyet
696 /* reinitialize interface if necessary */
697 if (ifp->if_flags & IFF_UP)
698 rl_init(sc);
699 #endif
700 sc->sc_suspended = 0;
701
702 return (0);
703 }
704
705 static int
hifn_init_pubrng(struct hifn_softc * sc)706 hifn_init_pubrng(struct hifn_softc *sc)
707 {
708 u_int32_t r;
709 int i;
710
711 #ifdef HIFN_RNDTEST
712 sc->sc_rndtest = rndtest_attach(sc->sc_dev);
713 if (sc->sc_rndtest)
714 sc->sc_harvest = rndtest_harvest;
715 else
716 sc->sc_harvest = default_harvest;
717 #else
718 sc->sc_harvest = default_harvest;
719 #endif
720 if ((sc->sc_flags & HIFN_IS_7811) == 0) {
721 /* Reset 7951 public key/rng engine */
722 WRITE_REG_1(sc, HIFN_1_PUB_RESET,
723 READ_REG_1(sc, HIFN_1_PUB_RESET) | HIFN_PUBRST_RESET);
724
725 for (i = 0; i < 100; i++) {
726 DELAY(1000);
727 if ((READ_REG_1(sc, HIFN_1_PUB_RESET) &
728 HIFN_PUBRST_RESET) == 0)
729 break;
730 }
731
732 if (i == 100) {
733 device_printf(sc->sc_dev, "public key init failed\n");
734 return (1);
735 }
736 }
737
738 /* Enable the rng, if available */
739 if (sc->sc_flags & HIFN_HAS_RNG) {
740 if (sc->sc_flags & HIFN_IS_7811) {
741 r = READ_REG_1(sc, HIFN_1_7811_RNGENA);
742 if (r & HIFN_7811_RNGENA_ENA) {
743 r &= ~HIFN_7811_RNGENA_ENA;
744 WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r);
745 }
746 WRITE_REG_1(sc, HIFN_1_7811_RNGCFG,
747 HIFN_7811_RNGCFG_DEFL);
748 r |= HIFN_7811_RNGENA_ENA;
749 WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r);
750 } else
751 WRITE_REG_1(sc, HIFN_1_RNG_CONFIG,
752 READ_REG_1(sc, HIFN_1_RNG_CONFIG) |
753 HIFN_RNGCFG_ENA);
754
755 sc->sc_rngfirst = 1;
756 if (hz >= 100)
757 sc->sc_rnghz = hz / 100;
758 else
759 sc->sc_rnghz = 1;
760 callout_init(&sc->sc_rngto, 1);
761 callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc);
762 }
763
764 /* Enable public key engine, if available */
765 if (sc->sc_flags & HIFN_HAS_PUBLIC) {
766 WRITE_REG_1(sc, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE);
767 sc->sc_dmaier |= HIFN_DMAIER_PUBDONE;
768 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
769 #ifdef HIFN_VULCANDEV
770 sc->sc_pkdev = make_dev(&vulcanpk_cdevsw, 0,
771 UID_ROOT, GID_WHEEL, 0666,
772 "vulcanpk");
773 sc->sc_pkdev->si_drv1 = sc;
774 #endif
775 }
776
777 return (0);
778 }
779
780 static void
hifn_rng(void * vsc)781 hifn_rng(void *vsc)
782 {
783 #define RANDOM_BITS(n) (n)*sizeof (u_int32_t), (n)*sizeof (u_int32_t)*NBBY, 0
784 struct hifn_softc *sc = vsc;
785 u_int32_t sts, num[2];
786 int i;
787
788 if (sc->sc_flags & HIFN_IS_7811) {
789 /* ONLY VALID ON 7811!!!! */
790 for (i = 0; i < 5; i++) {
791 sts = READ_REG_1(sc, HIFN_1_7811_RNGSTS);
792 if (sts & HIFN_7811_RNGSTS_UFL) {
793 device_printf(sc->sc_dev,
794 "RNG underflow: disabling\n");
795 return;
796 }
797 if ((sts & HIFN_7811_RNGSTS_RDY) == 0)
798 break;
799
800 /*
801 * There are at least two words in the RNG FIFO
802 * at this point.
803 */
804 num[0] = READ_REG_1(sc, HIFN_1_7811_RNGDAT);
805 num[1] = READ_REG_1(sc, HIFN_1_7811_RNGDAT);
806 /* NB: discard first data read */
807 if (sc->sc_rngfirst)
808 sc->sc_rngfirst = 0;
809 else
810 (*sc->sc_harvest)(sc->sc_rndtest,
811 num, sizeof (num));
812 }
813 } else {
814 num[0] = READ_REG_1(sc, HIFN_1_RNG_DATA);
815
816 /* NB: discard first data read */
817 if (sc->sc_rngfirst)
818 sc->sc_rngfirst = 0;
819 else
820 (*sc->sc_harvest)(sc->sc_rndtest,
821 num, sizeof (num[0]));
822 }
823
824 callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc);
825 #undef RANDOM_BITS
826 }
827
828 static void
hifn_puc_wait(struct hifn_softc * sc)829 hifn_puc_wait(struct hifn_softc *sc)
830 {
831 int i;
832 int reg = HIFN_0_PUCTRL;
833
834 if (sc->sc_flags & HIFN_IS_7956) {
835 reg = HIFN_0_PUCTRL2;
836 }
837
838 for (i = 5000; i > 0; i--) {
839 DELAY(1);
840 if (!(READ_REG_0(sc, reg) & HIFN_PUCTRL_RESET))
841 break;
842 }
843 if (!i)
844 device_printf(sc->sc_dev, "proc unit did not reset\n");
845 }
846
847 /*
848 * Reset the processing unit.
849 */
850 static void
hifn_reset_puc(struct hifn_softc * sc)851 hifn_reset_puc(struct hifn_softc *sc)
852 {
853 /* Reset processing unit */
854 int reg = HIFN_0_PUCTRL;
855
856 if (sc->sc_flags & HIFN_IS_7956) {
857 reg = HIFN_0_PUCTRL2;
858 }
859 WRITE_REG_0(sc, reg, HIFN_PUCTRL_DMAENA);
860
861 hifn_puc_wait(sc);
862 }
863
864 /*
865 * Set the Retry and TRDY registers; note that we set them to
866 * zero because the 7811 locks up when forced to retry (section
867 * 3.6 of "Specification Update SU-0014-04". Not clear if we
868 * should do this for all Hifn parts, but it doesn't seem to hurt.
869 */
870 static void
hifn_set_retry(struct hifn_softc * sc)871 hifn_set_retry(struct hifn_softc *sc)
872 {
873 /* NB: RETRY only responds to 8-bit reads/writes */
874 pci_write_config(sc->sc_dev, HIFN_RETRY_TIMEOUT, 0, 1);
875 pci_write_config(sc->sc_dev, HIFN_TRDY_TIMEOUT, 0, 1);
876 }
877
878 /*
879 * Resets the board. Values in the registers are left as is
880 * from the reset (i.e. initial values are assigned elsewhere).
881 */
882 static void
hifn_reset_board(struct hifn_softc * sc,int full)883 hifn_reset_board(struct hifn_softc *sc, int full)
884 {
885 u_int32_t reg;
886
887 /*
888 * Set polling in the DMA configuration register to zero. 0x7 avoids
889 * resetting the board and zeros out the other fields.
890 */
891 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
892 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
893
894 /*
895 * Now that polling has been disabled, we have to wait 1 ms
896 * before resetting the board.
897 */
898 DELAY(1000);
899
900 /* Reset the DMA unit */
901 if (full) {
902 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE);
903 DELAY(1000);
904 } else {
905 WRITE_REG_1(sc, HIFN_1_DMA_CNFG,
906 HIFN_DMACNFG_MODE | HIFN_DMACNFG_MSTRESET);
907 hifn_reset_puc(sc);
908 }
909
910 KASSERT(sc->sc_dma != NULL, ("hifn_reset_board: null DMA tag!"));
911 bzero(sc->sc_dma, sizeof(*sc->sc_dma));
912
913 /* Bring dma unit out of reset */
914 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
915 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
916
917 hifn_puc_wait(sc);
918 hifn_set_retry(sc);
919
920 if (sc->sc_flags & HIFN_IS_7811) {
921 for (reg = 0; reg < 1000; reg++) {
922 if (READ_REG_1(sc, HIFN_1_7811_MIPSRST) &
923 HIFN_MIPSRST_CRAMINIT)
924 break;
925 DELAY(1000);
926 }
927 if (reg == 1000)
928 printf(": cram init timeout\n");
929 } else {
930 /* set up DMA configuration register #2 */
931 /* turn off all PK and BAR0 swaps */
932 WRITE_REG_1(sc, HIFN_1_DMA_CNFG2,
933 (3 << HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT)|
934 (3 << HIFN_DMACNFG2_INIT_READ_BURST_SHIFT)|
935 (2 << HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT)|
936 (2 << HIFN_DMACNFG2_TGT_READ_BURST_SHIFT));
937 }
938
939 }
940
941 static u_int32_t
hifn_next_signature(u_int32_t a,u_int cnt)942 hifn_next_signature(u_int32_t a, u_int cnt)
943 {
944 int i;
945 u_int32_t v;
946
947 for (i = 0; i < cnt; i++) {
948
949 /* get the parity */
950 v = a & 0x80080125;
951 v ^= v >> 16;
952 v ^= v >> 8;
953 v ^= v >> 4;
954 v ^= v >> 2;
955 v ^= v >> 1;
956
957 a = (v & 1) ^ (a << 1);
958 }
959
960 return a;
961 }
962
963 struct pci2id {
964 u_short pci_vendor;
965 u_short pci_prod;
966 char card_id[13];
967 };
968 static struct pci2id pci2id[] = {
969 {
970 PCI_VENDOR_HIFN,
971 PCI_PRODUCT_HIFN_7951,
972 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
973 0x00, 0x00, 0x00, 0x00, 0x00 }
974 }, {
975 PCI_VENDOR_HIFN,
976 PCI_PRODUCT_HIFN_7955,
977 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
978 0x00, 0x00, 0x00, 0x00, 0x00 }
979 }, {
980 PCI_VENDOR_HIFN,
981 PCI_PRODUCT_HIFN_7956,
982 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
983 0x00, 0x00, 0x00, 0x00, 0x00 }
984 }, {
985 PCI_VENDOR_NETSEC,
986 PCI_PRODUCT_NETSEC_7751,
987 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
988 0x00, 0x00, 0x00, 0x00, 0x00 }
989 }, {
990 PCI_VENDOR_INVERTEX,
991 PCI_PRODUCT_INVERTEX_AEON,
992 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
993 0x00, 0x00, 0x00, 0x00, 0x00 }
994 }, {
995 PCI_VENDOR_HIFN,
996 PCI_PRODUCT_HIFN_7811,
997 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
998 0x00, 0x00, 0x00, 0x00, 0x00 }
999 }, {
1000 /*
1001 * Other vendors share this PCI ID as well, such as
1002 * http://www.powercrypt.com, and obviously they also
1003 * use the same key.
1004 */
1005 PCI_VENDOR_HIFN,
1006 PCI_PRODUCT_HIFN_7751,
1007 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1008 0x00, 0x00, 0x00, 0x00, 0x00 }
1009 },
1010 };
1011
1012 /*
1013 * Checks to see if crypto is already enabled. If crypto isn't enable,
1014 * "hifn_enable_crypto" is called to enable it. The check is important,
1015 * as enabling crypto twice will lock the board.
1016 */
1017 static int
hifn_enable_crypto(struct hifn_softc * sc)1018 hifn_enable_crypto(struct hifn_softc *sc)
1019 {
1020 u_int32_t dmacfg, ramcfg, encl, addr, i;
1021 char *offtbl = NULL;
1022
1023 for (i = 0; i < nitems(pci2id); i++) {
1024 if (pci2id[i].pci_vendor == pci_get_vendor(sc->sc_dev) &&
1025 pci2id[i].pci_prod == pci_get_device(sc->sc_dev)) {
1026 offtbl = pci2id[i].card_id;
1027 break;
1028 }
1029 }
1030 if (offtbl == NULL) {
1031 device_printf(sc->sc_dev, "Unknown card!\n");
1032 return (1);
1033 }
1034
1035 ramcfg = READ_REG_0(sc, HIFN_0_PUCNFG);
1036 dmacfg = READ_REG_1(sc, HIFN_1_DMA_CNFG);
1037
1038 /*
1039 * The RAM config register's encrypt level bit needs to be set before
1040 * every read performed on the encryption level register.
1041 */
1042 WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID);
1043
1044 encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA;
1045
1046 /*
1047 * Make sure we don't re-unlock. Two unlocks kills chip until the
1048 * next reboot.
1049 */
1050 if (encl == HIFN_PUSTAT_ENA_1 || encl == HIFN_PUSTAT_ENA_2) {
1051 #ifdef HIFN_DEBUG
1052 if (hifn_debug)
1053 device_printf(sc->sc_dev,
1054 "Strong crypto already enabled!\n");
1055 #endif
1056 goto report;
1057 }
1058
1059 if (encl != 0 && encl != HIFN_PUSTAT_ENA_0) {
1060 #ifdef HIFN_DEBUG
1061 if (hifn_debug)
1062 device_printf(sc->sc_dev,
1063 "Unknown encryption level 0x%x\n", encl);
1064 #endif
1065 return 1;
1066 }
1067
1068 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_UNLOCK |
1069 HIFN_DMACNFG_MSTRESET | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
1070 DELAY(1000);
1071 addr = READ_REG_1(sc, HIFN_UNLOCK_SECRET1);
1072 DELAY(1000);
1073 WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, 0);
1074 DELAY(1000);
1075
1076 for (i = 0; i <= 12; i++) {
1077 addr = hifn_next_signature(addr, offtbl[i] + 0x101);
1078 WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, addr);
1079
1080 DELAY(1000);
1081 }
1082
1083 WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID);
1084 encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA;
1085
1086 #ifdef HIFN_DEBUG
1087 if (hifn_debug) {
1088 if (encl != HIFN_PUSTAT_ENA_1 && encl != HIFN_PUSTAT_ENA_2)
1089 device_printf(sc->sc_dev, "Engine is permanently "
1090 "locked until next system reset!\n");
1091 else
1092 device_printf(sc->sc_dev, "Engine enabled "
1093 "successfully!\n");
1094 }
1095 #endif
1096
1097 report:
1098 WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg);
1099 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, dmacfg);
1100
1101 switch (encl) {
1102 case HIFN_PUSTAT_ENA_1:
1103 case HIFN_PUSTAT_ENA_2:
1104 break;
1105 case HIFN_PUSTAT_ENA_0:
1106 default:
1107 device_printf(sc->sc_dev, "disabled");
1108 break;
1109 }
1110
1111 return 0;
1112 }
1113
1114 /*
1115 * Give initial values to the registers listed in the "Register Space"
1116 * section of the HIFN Software Development reference manual.
1117 */
1118 static void
hifn_init_pci_registers(struct hifn_softc * sc)1119 hifn_init_pci_registers(struct hifn_softc *sc)
1120 {
1121 /* write fixed values needed by the Initialization registers */
1122 WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA);
1123 WRITE_REG_0(sc, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD);
1124 WRITE_REG_0(sc, HIFN_0_PUIER, HIFN_PUIER_DSTOVER);
1125
1126 /* write all 4 ring address registers */
1127 WRITE_REG_1(sc, HIFN_1_DMA_CRAR, sc->sc_dma_physaddr +
1128 offsetof(struct hifn_dma, cmdr[0]));
1129 WRITE_REG_1(sc, HIFN_1_DMA_SRAR, sc->sc_dma_physaddr +
1130 offsetof(struct hifn_dma, srcr[0]));
1131 WRITE_REG_1(sc, HIFN_1_DMA_DRAR, sc->sc_dma_physaddr +
1132 offsetof(struct hifn_dma, dstr[0]));
1133 WRITE_REG_1(sc, HIFN_1_DMA_RRAR, sc->sc_dma_physaddr +
1134 offsetof(struct hifn_dma, resr[0]));
1135
1136 DELAY(2000);
1137
1138 /* write status register */
1139 WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1140 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS |
1141 HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS |
1142 HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST |
1143 HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER |
1144 HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST |
1145 HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER |
1146 HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST |
1147 HIFN_DMACSR_S_WAIT |
1148 HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST |
1149 HIFN_DMACSR_C_WAIT |
1150 HIFN_DMACSR_ENGINE |
1151 ((sc->sc_flags & HIFN_HAS_PUBLIC) ?
1152 HIFN_DMACSR_PUBDONE : 0) |
1153 ((sc->sc_flags & HIFN_IS_7811) ?
1154 HIFN_DMACSR_ILLW | HIFN_DMACSR_ILLR : 0));
1155
1156 sc->sc_d_busy = sc->sc_r_busy = sc->sc_s_busy = sc->sc_c_busy = 0;
1157 sc->sc_dmaier |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT |
1158 HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER |
1159 HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT |
1160 ((sc->sc_flags & HIFN_IS_7811) ?
1161 HIFN_DMAIER_ILLW | HIFN_DMAIER_ILLR : 0);
1162 sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT;
1163 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
1164
1165
1166 if (sc->sc_flags & HIFN_IS_7956) {
1167 u_int32_t pll;
1168
1169 WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING |
1170 HIFN_PUCNFG_TCALLPHASES |
1171 HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32);
1172
1173 /* turn off the clocks and insure bypass is set */
1174 pll = READ_REG_1(sc, HIFN_1_PLL);
1175 pll = (pll &~ (HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL))
1176 | HIFN_PLL_BP | HIFN_PLL_MBSET;
1177 WRITE_REG_1(sc, HIFN_1_PLL, pll);
1178 DELAY(10*1000); /* 10ms */
1179
1180 /* change configuration */
1181 pll = (pll &~ HIFN_PLL_CONFIG) | sc->sc_pllconfig;
1182 WRITE_REG_1(sc, HIFN_1_PLL, pll);
1183 DELAY(10*1000); /* 10ms */
1184
1185 /* disable bypass */
1186 pll &= ~HIFN_PLL_BP;
1187 WRITE_REG_1(sc, HIFN_1_PLL, pll);
1188 /* enable clocks with new configuration */
1189 pll |= HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL;
1190 WRITE_REG_1(sc, HIFN_1_PLL, pll);
1191 } else {
1192 WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING |
1193 HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES |
1194 HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 |
1195 (sc->sc_drammodel ? HIFN_PUCNFG_DRAM : HIFN_PUCNFG_SRAM));
1196 }
1197
1198 WRITE_REG_0(sc, HIFN_0_PUISR, HIFN_PUISR_DSTOVER);
1199 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
1200 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST |
1201 ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) |
1202 ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL));
1203 }
1204
1205 /*
1206 * The maximum number of sessions supported by the card
1207 * is dependent on the amount of context ram, which
1208 * encryption algorithms are enabled, and how compression
1209 * is configured. This should be configured before this
1210 * routine is called.
1211 */
1212 static void
hifn_sessions(struct hifn_softc * sc)1213 hifn_sessions(struct hifn_softc *sc)
1214 {
1215 u_int32_t pucnfg;
1216 int ctxsize;
1217
1218 pucnfg = READ_REG_0(sc, HIFN_0_PUCNFG);
1219
1220 if (pucnfg & HIFN_PUCNFG_COMPSING) {
1221 if (pucnfg & HIFN_PUCNFG_ENCCNFG)
1222 ctxsize = 128;
1223 else
1224 ctxsize = 512;
1225 /*
1226 * 7955/7956 has internal context memory of 32K
1227 */
1228 if (sc->sc_flags & HIFN_IS_7956)
1229 sc->sc_maxses = 32768 / ctxsize;
1230 else
1231 sc->sc_maxses = 1 +
1232 ((sc->sc_ramsize - 32768) / ctxsize);
1233 } else
1234 sc->sc_maxses = sc->sc_ramsize / 16384;
1235
1236 if (sc->sc_maxses > 2048)
1237 sc->sc_maxses = 2048;
1238 }
1239
1240 /*
1241 * Determine ram type (sram or dram). Board should be just out of a reset
1242 * state when this is called.
1243 */
1244 static int
hifn_ramtype(struct hifn_softc * sc)1245 hifn_ramtype(struct hifn_softc *sc)
1246 {
1247 u_int8_t data[8], dataexpect[8];
1248 int i;
1249
1250 for (i = 0; i < sizeof(data); i++)
1251 data[i] = dataexpect[i] = 0x55;
1252 if (hifn_writeramaddr(sc, 0, data))
1253 return (-1);
1254 if (hifn_readramaddr(sc, 0, data))
1255 return (-1);
1256 if (bcmp(data, dataexpect, sizeof(data)) != 0) {
1257 sc->sc_drammodel = 1;
1258 return (0);
1259 }
1260
1261 for (i = 0; i < sizeof(data); i++)
1262 data[i] = dataexpect[i] = 0xaa;
1263 if (hifn_writeramaddr(sc, 0, data))
1264 return (-1);
1265 if (hifn_readramaddr(sc, 0, data))
1266 return (-1);
1267 if (bcmp(data, dataexpect, sizeof(data)) != 0) {
1268 sc->sc_drammodel = 1;
1269 return (0);
1270 }
1271
1272 return (0);
1273 }
1274
1275 #define HIFN_SRAM_MAX (32 << 20)
1276 #define HIFN_SRAM_STEP_SIZE 16384
1277 #define HIFN_SRAM_GRANULARITY (HIFN_SRAM_MAX / HIFN_SRAM_STEP_SIZE)
1278
1279 static int
hifn_sramsize(struct hifn_softc * sc)1280 hifn_sramsize(struct hifn_softc *sc)
1281 {
1282 u_int32_t a;
1283 u_int8_t data[8];
1284 u_int8_t dataexpect[sizeof(data)];
1285 int32_t i;
1286
1287 for (i = 0; i < sizeof(data); i++)
1288 data[i] = dataexpect[i] = i ^ 0x5a;
1289
1290 for (i = HIFN_SRAM_GRANULARITY - 1; i >= 0; i--) {
1291 a = i * HIFN_SRAM_STEP_SIZE;
1292 bcopy(&i, data, sizeof(i));
1293 hifn_writeramaddr(sc, a, data);
1294 }
1295
1296 for (i = 0; i < HIFN_SRAM_GRANULARITY; i++) {
1297 a = i * HIFN_SRAM_STEP_SIZE;
1298 bcopy(&i, dataexpect, sizeof(i));
1299 if (hifn_readramaddr(sc, a, data) < 0)
1300 return (0);
1301 if (bcmp(data, dataexpect, sizeof(data)) != 0)
1302 return (0);
1303 sc->sc_ramsize = a + HIFN_SRAM_STEP_SIZE;
1304 }
1305
1306 return (0);
1307 }
1308
1309 /*
1310 * XXX For dram boards, one should really try all of the
1311 * HIFN_PUCNFG_DSZ_*'s. This just assumes that PUCNFG
1312 * is already set up correctly.
1313 */
1314 static int
hifn_dramsize(struct hifn_softc * sc)1315 hifn_dramsize(struct hifn_softc *sc)
1316 {
1317 u_int32_t cnfg;
1318
1319 if (sc->sc_flags & HIFN_IS_7956) {
1320 /*
1321 * 7955/7956 have a fixed internal ram of only 32K.
1322 */
1323 sc->sc_ramsize = 32768;
1324 } else {
1325 cnfg = READ_REG_0(sc, HIFN_0_PUCNFG) &
1326 HIFN_PUCNFG_DRAMMASK;
1327 sc->sc_ramsize = 1 << ((cnfg >> 13) + 18);
1328 }
1329 return (0);
1330 }
1331
1332 static void
hifn_alloc_slot(struct hifn_softc * sc,int * cmdp,int * srcp,int * dstp,int * resp)1333 hifn_alloc_slot(struct hifn_softc *sc, int *cmdp, int *srcp, int *dstp, int *resp)
1334 {
1335 struct hifn_dma *dma = sc->sc_dma;
1336
1337 if (sc->sc_cmdi == HIFN_D_CMD_RSIZE) {
1338 sc->sc_cmdi = 0;
1339 dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID |
1340 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1341 HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE,
1342 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1343 }
1344 *cmdp = sc->sc_cmdi++;
1345 sc->sc_cmdk = sc->sc_cmdi;
1346
1347 if (sc->sc_srci == HIFN_D_SRC_RSIZE) {
1348 sc->sc_srci = 0;
1349 dma->srcr[HIFN_D_SRC_RSIZE].l = htole32(HIFN_D_VALID |
1350 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1351 HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE,
1352 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1353 }
1354 *srcp = sc->sc_srci++;
1355 sc->sc_srck = sc->sc_srci;
1356
1357 if (sc->sc_dsti == HIFN_D_DST_RSIZE) {
1358 sc->sc_dsti = 0;
1359 dma->dstr[HIFN_D_DST_RSIZE].l = htole32(HIFN_D_VALID |
1360 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1361 HIFN_DSTR_SYNC(sc, HIFN_D_DST_RSIZE,
1362 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1363 }
1364 *dstp = sc->sc_dsti++;
1365 sc->sc_dstk = sc->sc_dsti;
1366
1367 if (sc->sc_resi == HIFN_D_RES_RSIZE) {
1368 sc->sc_resi = 0;
1369 dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID |
1370 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1371 HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE,
1372 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1373 }
1374 *resp = sc->sc_resi++;
1375 sc->sc_resk = sc->sc_resi;
1376 }
1377
1378 static int
hifn_writeramaddr(struct hifn_softc * sc,int addr,u_int8_t * data)1379 hifn_writeramaddr(struct hifn_softc *sc, int addr, u_int8_t *data)
1380 {
1381 struct hifn_dma *dma = sc->sc_dma;
1382 hifn_base_command_t wc;
1383 const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ;
1384 int r, cmdi, resi, srci, dsti;
1385
1386 wc.masks = htole16(3 << 13);
1387 wc.session_num = htole16(addr >> 14);
1388 wc.total_source_count = htole16(8);
1389 wc.total_dest_count = htole16(addr & 0x3fff);
1390
1391 hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi);
1392
1393 WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1394 HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA |
1395 HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA);
1396
1397 /* build write command */
1398 bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND);
1399 *(hifn_base_command_t *)dma->command_bufs[cmdi] = wc;
1400 bcopy(data, &dma->test_src, sizeof(dma->test_src));
1401
1402 dma->srcr[srci].p = htole32(sc->sc_dma_physaddr
1403 + offsetof(struct hifn_dma, test_src));
1404 dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr
1405 + offsetof(struct hifn_dma, test_dst));
1406
1407 dma->cmdr[cmdi].l = htole32(16 | masks);
1408 dma->srcr[srci].l = htole32(8 | masks);
1409 dma->dstr[dsti].l = htole32(4 | masks);
1410 dma->resr[resi].l = htole32(4 | masks);
1411
1412 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1413 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1414
1415 for (r = 10000; r >= 0; r--) {
1416 DELAY(10);
1417 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1418 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1419 if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0)
1420 break;
1421 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1422 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1423 }
1424 if (r == 0) {
1425 device_printf(sc->sc_dev, "writeramaddr -- "
1426 "result[%d](addr %d) still valid\n", resi, addr);
1427 r = -1;
1428 return (-1);
1429 } else
1430 r = 0;
1431
1432 WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1433 HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS |
1434 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS);
1435
1436 return (r);
1437 }
1438
1439 static int
hifn_readramaddr(struct hifn_softc * sc,int addr,u_int8_t * data)1440 hifn_readramaddr(struct hifn_softc *sc, int addr, u_int8_t *data)
1441 {
1442 struct hifn_dma *dma = sc->sc_dma;
1443 hifn_base_command_t rc;
1444 const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ;
1445 int r, cmdi, srci, dsti, resi;
1446
1447 rc.masks = htole16(2 << 13);
1448 rc.session_num = htole16(addr >> 14);
1449 rc.total_source_count = htole16(addr & 0x3fff);
1450 rc.total_dest_count = htole16(8);
1451
1452 hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi);
1453
1454 WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1455 HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA |
1456 HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA);
1457
1458 bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND);
1459 *(hifn_base_command_t *)dma->command_bufs[cmdi] = rc;
1460
1461 dma->srcr[srci].p = htole32(sc->sc_dma_physaddr +
1462 offsetof(struct hifn_dma, test_src));
1463 dma->test_src = 0;
1464 dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr +
1465 offsetof(struct hifn_dma, test_dst));
1466 dma->test_dst = 0;
1467 dma->cmdr[cmdi].l = htole32(8 | masks);
1468 dma->srcr[srci].l = htole32(8 | masks);
1469 dma->dstr[dsti].l = htole32(8 | masks);
1470 dma->resr[resi].l = htole32(HIFN_MAX_RESULT | masks);
1471
1472 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1473 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1474
1475 for (r = 10000; r >= 0; r--) {
1476 DELAY(10);
1477 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1478 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1479 if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0)
1480 break;
1481 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1482 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1483 }
1484 if (r == 0) {
1485 device_printf(sc->sc_dev, "readramaddr -- "
1486 "result[%d](addr %d) still valid\n", resi, addr);
1487 r = -1;
1488 } else {
1489 r = 0;
1490 bcopy(&dma->test_dst, data, sizeof(dma->test_dst));
1491 }
1492
1493 WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1494 HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS |
1495 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS);
1496
1497 return (r);
1498 }
1499
1500 /*
1501 * Initialize the descriptor rings.
1502 */
1503 static void
hifn_init_dma(struct hifn_softc * sc)1504 hifn_init_dma(struct hifn_softc *sc)
1505 {
1506 struct hifn_dma *dma = sc->sc_dma;
1507 int i;
1508
1509 hifn_set_retry(sc);
1510
1511 /* initialize static pointer values */
1512 for (i = 0; i < HIFN_D_CMD_RSIZE; i++)
1513 dma->cmdr[i].p = htole32(sc->sc_dma_physaddr +
1514 offsetof(struct hifn_dma, command_bufs[i][0]));
1515 for (i = 0; i < HIFN_D_RES_RSIZE; i++)
1516 dma->resr[i].p = htole32(sc->sc_dma_physaddr +
1517 offsetof(struct hifn_dma, result_bufs[i][0]));
1518
1519 dma->cmdr[HIFN_D_CMD_RSIZE].p =
1520 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, cmdr[0]));
1521 dma->srcr[HIFN_D_SRC_RSIZE].p =
1522 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, srcr[0]));
1523 dma->dstr[HIFN_D_DST_RSIZE].p =
1524 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, dstr[0]));
1525 dma->resr[HIFN_D_RES_RSIZE].p =
1526 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, resr[0]));
1527
1528 sc->sc_cmdu = sc->sc_srcu = sc->sc_dstu = sc->sc_resu = 0;
1529 sc->sc_cmdi = sc->sc_srci = sc->sc_dsti = sc->sc_resi = 0;
1530 sc->sc_cmdk = sc->sc_srck = sc->sc_dstk = sc->sc_resk = 0;
1531 }
1532
1533 /*
1534 * Writes out the raw command buffer space. Returns the
1535 * command buffer size.
1536 */
1537 static u_int
hifn_write_command(struct hifn_command * cmd,u_int8_t * buf)1538 hifn_write_command(struct hifn_command *cmd, u_int8_t *buf)
1539 {
1540 struct cryptop *crp;
1541 u_int8_t *buf_pos;
1542 hifn_base_command_t *base_cmd;
1543 hifn_mac_command_t *mac_cmd;
1544 hifn_crypt_command_t *cry_cmd;
1545 int using_mac, using_crypt, ivlen;
1546 u_int32_t dlen, slen;
1547
1548 crp = cmd->crp;
1549 buf_pos = buf;
1550 using_mac = cmd->base_masks & HIFN_BASE_CMD_MAC;
1551 using_crypt = cmd->base_masks & HIFN_BASE_CMD_CRYPT;
1552
1553 base_cmd = (hifn_base_command_t *)buf_pos;
1554 base_cmd->masks = htole16(cmd->base_masks);
1555 slen = cmd->src_mapsize;
1556 if (cmd->sloplen)
1557 dlen = cmd->dst_mapsize - cmd->sloplen + sizeof(u_int32_t);
1558 else
1559 dlen = cmd->dst_mapsize;
1560 base_cmd->total_source_count = htole16(slen & HIFN_BASE_CMD_LENMASK_LO);
1561 base_cmd->total_dest_count = htole16(dlen & HIFN_BASE_CMD_LENMASK_LO);
1562 dlen >>= 16;
1563 slen >>= 16;
1564 base_cmd->session_num = htole16(
1565 ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) |
1566 ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M));
1567 buf_pos += sizeof(hifn_base_command_t);
1568
1569 if (using_mac) {
1570 mac_cmd = (hifn_mac_command_t *)buf_pos;
1571 dlen = crp->crp_aad_length + crp->crp_payload_length;
1572 mac_cmd->source_count = htole16(dlen & 0xffff);
1573 dlen >>= 16;
1574 mac_cmd->masks = htole16(cmd->mac_masks |
1575 ((dlen << HIFN_MAC_CMD_SRCLEN_S) & HIFN_MAC_CMD_SRCLEN_M));
1576 if (crp->crp_aad_length != 0)
1577 mac_cmd->header_skip = htole16(crp->crp_aad_start);
1578 else
1579 mac_cmd->header_skip = htole16(crp->crp_payload_start);
1580 mac_cmd->reserved = 0;
1581 buf_pos += sizeof(hifn_mac_command_t);
1582 }
1583
1584 if (using_crypt) {
1585 cry_cmd = (hifn_crypt_command_t *)buf_pos;
1586 dlen = crp->crp_payload_length;
1587 cry_cmd->source_count = htole16(dlen & 0xffff);
1588 dlen >>= 16;
1589 cry_cmd->masks = htole16(cmd->cry_masks |
1590 ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) & HIFN_CRYPT_CMD_SRCLEN_M));
1591 cry_cmd->header_skip = htole16(crp->crp_payload_length);
1592 cry_cmd->reserved = 0;
1593 buf_pos += sizeof(hifn_crypt_command_t);
1594 }
1595
1596 if (using_mac && cmd->mac_masks & HIFN_MAC_CMD_NEW_KEY) {
1597 bcopy(cmd->mac, buf_pos, HIFN_MAC_KEY_LENGTH);
1598 buf_pos += HIFN_MAC_KEY_LENGTH;
1599 }
1600
1601 if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_KEY) {
1602 switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) {
1603 case HIFN_CRYPT_CMD_ALG_AES:
1604 /*
1605 * AES keys are variable 128, 192 and
1606 * 256 bits (16, 24 and 32 bytes).
1607 */
1608 bcopy(cmd->ck, buf_pos, cmd->cklen);
1609 buf_pos += cmd->cklen;
1610 break;
1611 }
1612 }
1613
1614 if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_IV) {
1615 switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) {
1616 case HIFN_CRYPT_CMD_ALG_AES:
1617 ivlen = HIFN_AES_IV_LENGTH;
1618 break;
1619 default:
1620 ivlen = HIFN_IV_LENGTH;
1621 break;
1622 }
1623 bcopy(cmd->iv, buf_pos, ivlen);
1624 buf_pos += ivlen;
1625 }
1626
1627 if ((cmd->base_masks & (HIFN_BASE_CMD_MAC|HIFN_BASE_CMD_CRYPT)) == 0) {
1628 bzero(buf_pos, 8);
1629 buf_pos += 8;
1630 }
1631
1632 return (buf_pos - buf);
1633 }
1634
1635 static int
hifn_dmamap_aligned(struct hifn_operand * op)1636 hifn_dmamap_aligned(struct hifn_operand *op)
1637 {
1638 int i;
1639
1640 for (i = 0; i < op->nsegs; i++) {
1641 if (op->segs[i].ds_addr & 3)
1642 return (0);
1643 if ((i != (op->nsegs - 1)) && (op->segs[i].ds_len & 3))
1644 return (0);
1645 }
1646 return (1);
1647 }
1648
1649 static __inline int
hifn_dmamap_dstwrap(struct hifn_softc * sc,int idx)1650 hifn_dmamap_dstwrap(struct hifn_softc *sc, int idx)
1651 {
1652 struct hifn_dma *dma = sc->sc_dma;
1653
1654 if (++idx == HIFN_D_DST_RSIZE) {
1655 dma->dstr[idx].l = htole32(HIFN_D_VALID | HIFN_D_JUMP |
1656 HIFN_D_MASKDONEIRQ);
1657 HIFN_DSTR_SYNC(sc, idx,
1658 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1659 idx = 0;
1660 }
1661 return (idx);
1662 }
1663
1664 static int
hifn_dmamap_load_dst(struct hifn_softc * sc,struct hifn_command * cmd)1665 hifn_dmamap_load_dst(struct hifn_softc *sc, struct hifn_command *cmd)
1666 {
1667 struct hifn_dma *dma = sc->sc_dma;
1668 struct hifn_operand *dst = &cmd->dst;
1669 u_int32_t p, l;
1670 int idx, used = 0, i;
1671
1672 idx = sc->sc_dsti;
1673 for (i = 0; i < dst->nsegs - 1; i++) {
1674 dma->dstr[idx].p = htole32(dst->segs[i].ds_addr);
1675 dma->dstr[idx].l = htole32(HIFN_D_VALID |
1676 HIFN_D_MASKDONEIRQ | dst->segs[i].ds_len);
1677 HIFN_DSTR_SYNC(sc, idx,
1678 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1679 used++;
1680
1681 idx = hifn_dmamap_dstwrap(sc, idx);
1682 }
1683
1684 if (cmd->sloplen == 0) {
1685 p = dst->segs[i].ds_addr;
1686 l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST |
1687 dst->segs[i].ds_len;
1688 } else {
1689 p = sc->sc_dma_physaddr +
1690 offsetof(struct hifn_dma, slop[cmd->slopidx]);
1691 l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST |
1692 sizeof(u_int32_t);
1693
1694 if ((dst->segs[i].ds_len - cmd->sloplen) != 0) {
1695 dma->dstr[idx].p = htole32(dst->segs[i].ds_addr);
1696 dma->dstr[idx].l = htole32(HIFN_D_VALID |
1697 HIFN_D_MASKDONEIRQ |
1698 (dst->segs[i].ds_len - cmd->sloplen));
1699 HIFN_DSTR_SYNC(sc, idx,
1700 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1701 used++;
1702
1703 idx = hifn_dmamap_dstwrap(sc, idx);
1704 }
1705 }
1706 dma->dstr[idx].p = htole32(p);
1707 dma->dstr[idx].l = htole32(l);
1708 HIFN_DSTR_SYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1709 used++;
1710
1711 idx = hifn_dmamap_dstwrap(sc, idx);
1712
1713 sc->sc_dsti = idx;
1714 sc->sc_dstu += used;
1715 return (idx);
1716 }
1717
1718 static __inline int
hifn_dmamap_srcwrap(struct hifn_softc * sc,int idx)1719 hifn_dmamap_srcwrap(struct hifn_softc *sc, int idx)
1720 {
1721 struct hifn_dma *dma = sc->sc_dma;
1722
1723 if (++idx == HIFN_D_SRC_RSIZE) {
1724 dma->srcr[idx].l = htole32(HIFN_D_VALID |
1725 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1726 HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE,
1727 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1728 idx = 0;
1729 }
1730 return (idx);
1731 }
1732
1733 static int
hifn_dmamap_load_src(struct hifn_softc * sc,struct hifn_command * cmd)1734 hifn_dmamap_load_src(struct hifn_softc *sc, struct hifn_command *cmd)
1735 {
1736 struct hifn_dma *dma = sc->sc_dma;
1737 struct hifn_operand *src = &cmd->src;
1738 int idx, i;
1739 u_int32_t last = 0;
1740
1741 idx = sc->sc_srci;
1742 for (i = 0; i < src->nsegs; i++) {
1743 if (i == src->nsegs - 1)
1744 last = HIFN_D_LAST;
1745
1746 dma->srcr[idx].p = htole32(src->segs[i].ds_addr);
1747 dma->srcr[idx].l = htole32(src->segs[i].ds_len |
1748 HIFN_D_VALID | HIFN_D_MASKDONEIRQ | last);
1749 HIFN_SRCR_SYNC(sc, idx,
1750 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1751
1752 idx = hifn_dmamap_srcwrap(sc, idx);
1753 }
1754 sc->sc_srci = idx;
1755 sc->sc_srcu += src->nsegs;
1756 return (idx);
1757 }
1758
1759 static void
hifn_op_cb(void * arg,bus_dma_segment_t * seg,int nsegs,int error)1760 hifn_op_cb(void* arg, bus_dma_segment_t *seg, int nsegs, int error)
1761 {
1762 struct hifn_operand *op = arg;
1763
1764 KASSERT(nsegs <= MAX_SCATTER,
1765 ("hifn_op_cb: too many DMA segments (%u > %u) "
1766 "returned when mapping operand", nsegs, MAX_SCATTER));
1767 op->nsegs = nsegs;
1768 bcopy(seg, op->segs, nsegs * sizeof (seg[0]));
1769 }
1770
1771 static int
hifn_crypto(struct hifn_softc * sc,struct hifn_command * cmd,struct cryptop * crp,int hint)1772 hifn_crypto(
1773 struct hifn_softc *sc,
1774 struct hifn_command *cmd,
1775 struct cryptop *crp,
1776 int hint)
1777 {
1778 struct hifn_dma *dma = sc->sc_dma;
1779 u_int32_t cmdlen, csr;
1780 int cmdi, resi, err = 0;
1781
1782 /*
1783 * need 1 cmd, and 1 res
1784 *
1785 * NB: check this first since it's easy.
1786 */
1787 HIFN_LOCK(sc);
1788 if ((sc->sc_cmdu + 1) > HIFN_D_CMD_RSIZE ||
1789 (sc->sc_resu + 1) > HIFN_D_RES_RSIZE) {
1790 #ifdef HIFN_DEBUG
1791 if (hifn_debug) {
1792 device_printf(sc->sc_dev,
1793 "cmd/result exhaustion, cmdu %u resu %u\n",
1794 sc->sc_cmdu, sc->sc_resu);
1795 }
1796 #endif
1797 hifnstats.hst_nomem_cr++;
1798 HIFN_UNLOCK(sc);
1799 return (ERESTART);
1800 }
1801
1802 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->src_map)) {
1803 hifnstats.hst_nomem_map++;
1804 HIFN_UNLOCK(sc);
1805 return (ENOMEM);
1806 }
1807
1808 if (bus_dmamap_load_crp(sc->sc_dmat, cmd->src_map, crp, hifn_op_cb,
1809 &cmd->src, BUS_DMA_NOWAIT)) {
1810 hifnstats.hst_nomem_load++;
1811 err = ENOMEM;
1812 goto err_srcmap1;
1813 }
1814 cmd->src_mapsize = crypto_buffer_len(&crp->crp_buf);
1815
1816 if (hifn_dmamap_aligned(&cmd->src)) {
1817 cmd->sloplen = cmd->src_mapsize & 3;
1818 cmd->dst = cmd->src;
1819 } else if (crp->crp_buf.cb_type == CRYPTO_BUF_MBUF) {
1820 int totlen, len;
1821 struct mbuf *m, *m0, *mlast;
1822
1823 KASSERT(cmd->dst_m == NULL,
1824 ("hifn_crypto: dst_m initialized improperly"));
1825 hifnstats.hst_unaligned++;
1826
1827 /*
1828 * Source is not aligned on a longword boundary.
1829 * Copy the data to insure alignment. If we fail
1830 * to allocate mbufs or clusters while doing this
1831 * we return ERESTART so the operation is requeued
1832 * at the crypto later, but only if there are
1833 * ops already posted to the hardware; otherwise we
1834 * have no guarantee that we'll be re-entered.
1835 */
1836 totlen = cmd->src_mapsize;
1837 if (crp->crp_buf.cb_mbuf->m_flags & M_PKTHDR) {
1838 len = MHLEN;
1839 MGETHDR(m0, M_NOWAIT, MT_DATA);
1840 if (m0 && !m_dup_pkthdr(m0, crp->crp_buf.cb_mbuf,
1841 M_NOWAIT)) {
1842 m_free(m0);
1843 m0 = NULL;
1844 }
1845 } else {
1846 len = MLEN;
1847 MGET(m0, M_NOWAIT, MT_DATA);
1848 }
1849 if (m0 == NULL) {
1850 hifnstats.hst_nomem_mbuf++;
1851 err = sc->sc_cmdu ? ERESTART : ENOMEM;
1852 goto err_srcmap;
1853 }
1854 if (totlen >= MINCLSIZE) {
1855 if (!(MCLGET(m0, M_NOWAIT))) {
1856 hifnstats.hst_nomem_mcl++;
1857 err = sc->sc_cmdu ? ERESTART : ENOMEM;
1858 m_freem(m0);
1859 goto err_srcmap;
1860 }
1861 len = MCLBYTES;
1862 }
1863 totlen -= len;
1864 m0->m_pkthdr.len = m0->m_len = len;
1865 mlast = m0;
1866
1867 while (totlen > 0) {
1868 MGET(m, M_NOWAIT, MT_DATA);
1869 if (m == NULL) {
1870 hifnstats.hst_nomem_mbuf++;
1871 err = sc->sc_cmdu ? ERESTART : ENOMEM;
1872 m_freem(m0);
1873 goto err_srcmap;
1874 }
1875 len = MLEN;
1876 if (totlen >= MINCLSIZE) {
1877 if (!(MCLGET(m, M_NOWAIT))) {
1878 hifnstats.hst_nomem_mcl++;
1879 err = sc->sc_cmdu ? ERESTART : ENOMEM;
1880 mlast->m_next = m;
1881 m_freem(m0);
1882 goto err_srcmap;
1883 }
1884 len = MCLBYTES;
1885 }
1886
1887 m->m_len = len;
1888 m0->m_pkthdr.len += len;
1889 totlen -= len;
1890
1891 mlast->m_next = m;
1892 mlast = m;
1893 }
1894 cmd->dst_m = m0;
1895
1896 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT,
1897 &cmd->dst_map)) {
1898 hifnstats.hst_nomem_map++;
1899 err = ENOMEM;
1900 goto err_srcmap;
1901 }
1902
1903 if (bus_dmamap_load_mbuf_sg(sc->sc_dmat, cmd->dst_map, m0,
1904 cmd->dst_segs, &cmd->dst_nsegs, 0)) {
1905 hifnstats.hst_nomem_map++;
1906 err = ENOMEM;
1907 goto err_dstmap1;
1908 }
1909 cmd->dst_mapsize = m0->m_pkthdr.len;
1910 } else {
1911 err = EINVAL;
1912 goto err_srcmap;
1913 }
1914
1915 #ifdef HIFN_DEBUG
1916 if (hifn_debug) {
1917 device_printf(sc->sc_dev,
1918 "Entering cmd: stat %8x ien %8x u %d/%d/%d/%d n %d/%d\n",
1919 READ_REG_1(sc, HIFN_1_DMA_CSR),
1920 READ_REG_1(sc, HIFN_1_DMA_IER),
1921 sc->sc_cmdu, sc->sc_srcu, sc->sc_dstu, sc->sc_resu,
1922 cmd->src_nsegs, cmd->dst_nsegs);
1923 }
1924 #endif
1925
1926 if (cmd->src_map == cmd->dst_map) {
1927 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
1928 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1929 } else {
1930 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
1931 BUS_DMASYNC_PREWRITE);
1932 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map,
1933 BUS_DMASYNC_PREREAD);
1934 }
1935
1936 /*
1937 * need N src, and N dst
1938 */
1939 if ((sc->sc_srcu + cmd->src_nsegs) > HIFN_D_SRC_RSIZE ||
1940 (sc->sc_dstu + cmd->dst_nsegs + 1) > HIFN_D_DST_RSIZE) {
1941 #ifdef HIFN_DEBUG
1942 if (hifn_debug) {
1943 device_printf(sc->sc_dev,
1944 "src/dst exhaustion, srcu %u+%u dstu %u+%u\n",
1945 sc->sc_srcu, cmd->src_nsegs,
1946 sc->sc_dstu, cmd->dst_nsegs);
1947 }
1948 #endif
1949 hifnstats.hst_nomem_sd++;
1950 err = ERESTART;
1951 goto err_dstmap;
1952 }
1953
1954 if (sc->sc_cmdi == HIFN_D_CMD_RSIZE) {
1955 sc->sc_cmdi = 0;
1956 dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID |
1957 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1958 HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE,
1959 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1960 }
1961 cmdi = sc->sc_cmdi++;
1962 cmdlen = hifn_write_command(cmd, dma->command_bufs[cmdi]);
1963 HIFN_CMD_SYNC(sc, cmdi, BUS_DMASYNC_PREWRITE);
1964
1965 /* .p for command/result already set */
1966 dma->cmdr[cmdi].l = htole32(cmdlen | HIFN_D_VALID | HIFN_D_LAST |
1967 HIFN_D_MASKDONEIRQ);
1968 HIFN_CMDR_SYNC(sc, cmdi,
1969 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1970 sc->sc_cmdu++;
1971
1972 /*
1973 * We don't worry about missing an interrupt (which a "command wait"
1974 * interrupt salvages us from), unless there is more than one command
1975 * in the queue.
1976 */
1977 if (sc->sc_cmdu > 1) {
1978 sc->sc_dmaier |= HIFN_DMAIER_C_WAIT;
1979 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
1980 }
1981
1982 hifnstats.hst_ipackets++;
1983 hifnstats.hst_ibytes += cmd->src_mapsize;
1984
1985 hifn_dmamap_load_src(sc, cmd);
1986
1987 /*
1988 * Unlike other descriptors, we don't mask done interrupt from
1989 * result descriptor.
1990 */
1991 #ifdef HIFN_DEBUG
1992 if (hifn_debug)
1993 printf("load res\n");
1994 #endif
1995 if (sc->sc_resi == HIFN_D_RES_RSIZE) {
1996 sc->sc_resi = 0;
1997 dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID |
1998 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1999 HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE,
2000 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2001 }
2002 resi = sc->sc_resi++;
2003 KASSERT(sc->sc_hifn_commands[resi] == NULL,
2004 ("hifn_crypto: command slot %u busy", resi));
2005 sc->sc_hifn_commands[resi] = cmd;
2006 HIFN_RES_SYNC(sc, resi, BUS_DMASYNC_PREREAD);
2007 if ((hint & CRYPTO_HINT_MORE) && sc->sc_curbatch < hifn_maxbatch) {
2008 dma->resr[resi].l = htole32(HIFN_MAX_RESULT |
2009 HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ);
2010 sc->sc_curbatch++;
2011 if (sc->sc_curbatch > hifnstats.hst_maxbatch)
2012 hifnstats.hst_maxbatch = sc->sc_curbatch;
2013 hifnstats.hst_totbatch++;
2014 } else {
2015 dma->resr[resi].l = htole32(HIFN_MAX_RESULT |
2016 HIFN_D_VALID | HIFN_D_LAST);
2017 sc->sc_curbatch = 0;
2018 }
2019 HIFN_RESR_SYNC(sc, resi,
2020 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2021 sc->sc_resu++;
2022
2023 if (cmd->sloplen)
2024 cmd->slopidx = resi;
2025
2026 hifn_dmamap_load_dst(sc, cmd);
2027
2028 csr = 0;
2029 if (sc->sc_c_busy == 0) {
2030 csr |= HIFN_DMACSR_C_CTRL_ENA;
2031 sc->sc_c_busy = 1;
2032 }
2033 if (sc->sc_s_busy == 0) {
2034 csr |= HIFN_DMACSR_S_CTRL_ENA;
2035 sc->sc_s_busy = 1;
2036 }
2037 if (sc->sc_r_busy == 0) {
2038 csr |= HIFN_DMACSR_R_CTRL_ENA;
2039 sc->sc_r_busy = 1;
2040 }
2041 if (sc->sc_d_busy == 0) {
2042 csr |= HIFN_DMACSR_D_CTRL_ENA;
2043 sc->sc_d_busy = 1;
2044 }
2045 if (csr)
2046 WRITE_REG_1(sc, HIFN_1_DMA_CSR, csr);
2047
2048 #ifdef HIFN_DEBUG
2049 if (hifn_debug) {
2050 device_printf(sc->sc_dev, "command: stat %8x ier %8x\n",
2051 READ_REG_1(sc, HIFN_1_DMA_CSR),
2052 READ_REG_1(sc, HIFN_1_DMA_IER));
2053 }
2054 #endif
2055
2056 sc->sc_active = 5;
2057 HIFN_UNLOCK(sc);
2058 KASSERT(err == 0, ("hifn_crypto: success with error %u", err));
2059 return (err); /* success */
2060
2061 err_dstmap:
2062 if (cmd->src_map != cmd->dst_map)
2063 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map);
2064 err_dstmap1:
2065 if (cmd->src_map != cmd->dst_map)
2066 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map);
2067 err_srcmap:
2068 if (crp->crp_buf.cb_type == CRYPTO_BUF_MBUF) {
2069 if (cmd->dst_m != NULL)
2070 m_freem(cmd->dst_m);
2071 }
2072 bus_dmamap_unload(sc->sc_dmat, cmd->src_map);
2073 err_srcmap1:
2074 bus_dmamap_destroy(sc->sc_dmat, cmd->src_map);
2075 HIFN_UNLOCK(sc);
2076 return (err);
2077 }
2078
2079 static void
hifn_tick(void * vsc)2080 hifn_tick(void* vsc)
2081 {
2082 struct hifn_softc *sc = vsc;
2083
2084 HIFN_LOCK(sc);
2085 if (sc->sc_active == 0) {
2086 u_int32_t r = 0;
2087
2088 if (sc->sc_cmdu == 0 && sc->sc_c_busy) {
2089 sc->sc_c_busy = 0;
2090 r |= HIFN_DMACSR_C_CTRL_DIS;
2091 }
2092 if (sc->sc_srcu == 0 && sc->sc_s_busy) {
2093 sc->sc_s_busy = 0;
2094 r |= HIFN_DMACSR_S_CTRL_DIS;
2095 }
2096 if (sc->sc_dstu == 0 && sc->sc_d_busy) {
2097 sc->sc_d_busy = 0;
2098 r |= HIFN_DMACSR_D_CTRL_DIS;
2099 }
2100 if (sc->sc_resu == 0 && sc->sc_r_busy) {
2101 sc->sc_r_busy = 0;
2102 r |= HIFN_DMACSR_R_CTRL_DIS;
2103 }
2104 if (r)
2105 WRITE_REG_1(sc, HIFN_1_DMA_CSR, r);
2106 } else
2107 sc->sc_active--;
2108 HIFN_UNLOCK(sc);
2109 callout_reset(&sc->sc_tickto, hz, hifn_tick, sc);
2110 }
2111
2112 static void
hifn_intr(void * arg)2113 hifn_intr(void *arg)
2114 {
2115 struct hifn_softc *sc = arg;
2116 struct hifn_dma *dma;
2117 u_int32_t dmacsr, restart;
2118 int i, u;
2119
2120 dmacsr = READ_REG_1(sc, HIFN_1_DMA_CSR);
2121
2122 /* Nothing in the DMA unit interrupted */
2123 if ((dmacsr & sc->sc_dmaier) == 0)
2124 return;
2125
2126 HIFN_LOCK(sc);
2127
2128 dma = sc->sc_dma;
2129
2130 #ifdef HIFN_DEBUG
2131 if (hifn_debug) {
2132 device_printf(sc->sc_dev,
2133 "irq: stat %08x ien %08x damier %08x i %d/%d/%d/%d k %d/%d/%d/%d u %d/%d/%d/%d\n",
2134 dmacsr, READ_REG_1(sc, HIFN_1_DMA_IER), sc->sc_dmaier,
2135 sc->sc_cmdi, sc->sc_srci, sc->sc_dsti, sc->sc_resi,
2136 sc->sc_cmdk, sc->sc_srck, sc->sc_dstk, sc->sc_resk,
2137 sc->sc_cmdu, sc->sc_srcu, sc->sc_dstu, sc->sc_resu);
2138 }
2139 #endif
2140
2141 WRITE_REG_1(sc, HIFN_1_DMA_CSR, dmacsr & sc->sc_dmaier);
2142
2143 if ((sc->sc_flags & HIFN_HAS_PUBLIC) &&
2144 (dmacsr & HIFN_DMACSR_PUBDONE))
2145 WRITE_REG_1(sc, HIFN_1_PUB_STATUS,
2146 READ_REG_1(sc, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE);
2147
2148 restart = dmacsr & (HIFN_DMACSR_D_OVER | HIFN_DMACSR_R_OVER);
2149 if (restart)
2150 device_printf(sc->sc_dev, "overrun %x\n", dmacsr);
2151
2152 if (sc->sc_flags & HIFN_IS_7811) {
2153 if (dmacsr & HIFN_DMACSR_ILLR)
2154 device_printf(sc->sc_dev, "illegal read\n");
2155 if (dmacsr & HIFN_DMACSR_ILLW)
2156 device_printf(sc->sc_dev, "illegal write\n");
2157 }
2158
2159 restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT |
2160 HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT);
2161 if (restart) {
2162 device_printf(sc->sc_dev, "abort, resetting.\n");
2163 hifnstats.hst_abort++;
2164 hifn_abort(sc);
2165 HIFN_UNLOCK(sc);
2166 return;
2167 }
2168
2169 if ((dmacsr & HIFN_DMACSR_C_WAIT) && (sc->sc_cmdu == 0)) {
2170 /*
2171 * If no slots to process and we receive a "waiting on
2172 * command" interrupt, we disable the "waiting on command"
2173 * (by clearing it).
2174 */
2175 sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT;
2176 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
2177 }
2178
2179 /* clear the rings */
2180 i = sc->sc_resk; u = sc->sc_resu;
2181 while (u != 0) {
2182 HIFN_RESR_SYNC(sc, i,
2183 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2184 if (dma->resr[i].l & htole32(HIFN_D_VALID)) {
2185 HIFN_RESR_SYNC(sc, i,
2186 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2187 break;
2188 }
2189
2190 if (i != HIFN_D_RES_RSIZE) {
2191 struct hifn_command *cmd;
2192 u_int8_t *macbuf = NULL;
2193
2194 HIFN_RES_SYNC(sc, i, BUS_DMASYNC_POSTREAD);
2195 cmd = sc->sc_hifn_commands[i];
2196 KASSERT(cmd != NULL,
2197 ("hifn_intr: null command slot %u", i));
2198 sc->sc_hifn_commands[i] = NULL;
2199
2200 if (cmd->base_masks & HIFN_BASE_CMD_MAC) {
2201 macbuf = dma->result_bufs[i];
2202 macbuf += 12;
2203 }
2204
2205 hifn_callback(sc, cmd, macbuf);
2206 hifnstats.hst_opackets++;
2207 u--;
2208 }
2209
2210 if (++i == (HIFN_D_RES_RSIZE + 1))
2211 i = 0;
2212 }
2213 sc->sc_resk = i; sc->sc_resu = u;
2214
2215 i = sc->sc_srck; u = sc->sc_srcu;
2216 while (u != 0) {
2217 if (i == HIFN_D_SRC_RSIZE)
2218 i = 0;
2219 HIFN_SRCR_SYNC(sc, i,
2220 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2221 if (dma->srcr[i].l & htole32(HIFN_D_VALID)) {
2222 HIFN_SRCR_SYNC(sc, i,
2223 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2224 break;
2225 }
2226 i++, u--;
2227 }
2228 sc->sc_srck = i; sc->sc_srcu = u;
2229
2230 i = sc->sc_cmdk; u = sc->sc_cmdu;
2231 while (u != 0) {
2232 HIFN_CMDR_SYNC(sc, i,
2233 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2234 if (dma->cmdr[i].l & htole32(HIFN_D_VALID)) {
2235 HIFN_CMDR_SYNC(sc, i,
2236 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2237 break;
2238 }
2239 if (i != HIFN_D_CMD_RSIZE) {
2240 u--;
2241 HIFN_CMD_SYNC(sc, i, BUS_DMASYNC_POSTWRITE);
2242 }
2243 if (++i == (HIFN_D_CMD_RSIZE + 1))
2244 i = 0;
2245 }
2246 sc->sc_cmdk = i; sc->sc_cmdu = u;
2247
2248 HIFN_UNLOCK(sc);
2249
2250 if (sc->sc_needwakeup) { /* XXX check high watermark */
2251 int wakeup = sc->sc_needwakeup & CRYPTO_SYMQ;
2252 #ifdef HIFN_DEBUG
2253 if (hifn_debug)
2254 device_printf(sc->sc_dev,
2255 "wakeup crypto (%x) u %d/%d/%d/%d\n",
2256 sc->sc_needwakeup,
2257 sc->sc_cmdu, sc->sc_srcu, sc->sc_dstu, sc->sc_resu);
2258 #endif
2259 sc->sc_needwakeup &= ~wakeup;
2260 crypto_unblock(sc->sc_cid, wakeup);
2261 }
2262 }
2263
2264 static bool
hifn_auth_supported(struct hifn_softc * sc,const struct crypto_session_params * csp)2265 hifn_auth_supported(struct hifn_softc *sc,
2266 const struct crypto_session_params *csp)
2267 {
2268
2269 switch (sc->sc_ena) {
2270 case HIFN_PUSTAT_ENA_2:
2271 case HIFN_PUSTAT_ENA_1:
2272 break;
2273 default:
2274 return (false);
2275 }
2276
2277 switch (csp->csp_auth_alg) {
2278 case CRYPTO_SHA1:
2279 break;
2280 case CRYPTO_SHA1_HMAC:
2281 if (csp->csp_auth_klen > HIFN_MAC_KEY_LENGTH)
2282 return (false);
2283 break;
2284 default:
2285 return (false);
2286 }
2287
2288 return (true);
2289 }
2290
2291 static bool
hifn_cipher_supported(struct hifn_softc * sc,const struct crypto_session_params * csp)2292 hifn_cipher_supported(struct hifn_softc *sc,
2293 const struct crypto_session_params *csp)
2294 {
2295
2296 if (csp->csp_cipher_klen == 0)
2297 return (false);
2298 if (csp->csp_ivlen > HIFN_MAX_IV_LENGTH)
2299 return (false);
2300 switch (sc->sc_ena) {
2301 case HIFN_PUSTAT_ENA_2:
2302 switch (csp->csp_cipher_alg) {
2303 case CRYPTO_AES_CBC:
2304 if ((sc->sc_flags & HIFN_HAS_AES) == 0)
2305 return (false);
2306 switch (csp->csp_cipher_klen) {
2307 case 128:
2308 case 192:
2309 case 256:
2310 break;
2311 default:
2312 return (false);
2313 }
2314 return (true);
2315 }
2316 }
2317 return (false);
2318 }
2319
2320 static int
hifn_probesession(device_t dev,const struct crypto_session_params * csp)2321 hifn_probesession(device_t dev, const struct crypto_session_params *csp)
2322 {
2323 struct hifn_softc *sc;
2324
2325 sc = device_get_softc(dev);
2326 if (csp->csp_flags != 0)
2327 return (EINVAL);
2328 switch (csp->csp_mode) {
2329 case CSP_MODE_DIGEST:
2330 if (!hifn_auth_supported(sc, csp))
2331 return (EINVAL);
2332 break;
2333 case CSP_MODE_CIPHER:
2334 if (!hifn_cipher_supported(sc, csp))
2335 return (EINVAL);
2336 break;
2337 case CSP_MODE_ETA:
2338 if (!hifn_auth_supported(sc, csp) ||
2339 !hifn_cipher_supported(sc, csp))
2340 return (EINVAL);
2341 break;
2342 default:
2343 return (EINVAL);
2344 }
2345
2346 return (CRYPTODEV_PROBE_HARDWARE);
2347 }
2348
2349 /*
2350 * Allocate a new 'session'.
2351 */
2352 static int
hifn_newsession(device_t dev,crypto_session_t cses,const struct crypto_session_params * csp)2353 hifn_newsession(device_t dev, crypto_session_t cses,
2354 const struct crypto_session_params *csp)
2355 {
2356 struct hifn_session *ses;
2357
2358 ses = crypto_get_driver_session(cses);
2359
2360 if (csp->csp_auth_alg != 0) {
2361 if (csp->csp_auth_mlen == 0)
2362 ses->hs_mlen = crypto_auth_hash(csp)->hashsize;
2363 else
2364 ses->hs_mlen = csp->csp_auth_mlen;
2365 }
2366
2367 return (0);
2368 }
2369
2370 /*
2371 * XXX freesession routine should run a zero'd mac/encrypt key into context
2372 * ram. to blow away any keys already stored there.
2373 */
2374
2375 static int
hifn_process(device_t dev,struct cryptop * crp,int hint)2376 hifn_process(device_t dev, struct cryptop *crp, int hint)
2377 {
2378 const struct crypto_session_params *csp;
2379 struct hifn_softc *sc = device_get_softc(dev);
2380 struct hifn_command *cmd = NULL;
2381 const void *mackey;
2382 int err, keylen;
2383 struct hifn_session *ses;
2384
2385 ses = crypto_get_driver_session(crp->crp_session);
2386
2387 cmd = malloc(sizeof(struct hifn_command), M_DEVBUF, M_NOWAIT | M_ZERO);
2388 if (cmd == NULL) {
2389 hifnstats.hst_nomem++;
2390 err = ENOMEM;
2391 goto errout;
2392 }
2393
2394 csp = crypto_get_params(crp->crp_session);
2395
2396 /*
2397 * The driver only supports ETA requests where there is no
2398 * gap between the AAD and payload.
2399 */
2400 if (csp->csp_mode == CSP_MODE_ETA && crp->crp_aad_length != 0 &&
2401 crp->crp_aad_start + crp->crp_aad_length !=
2402 crp->crp_payload_start) {
2403 err = EINVAL;
2404 goto errout;
2405 }
2406
2407 switch (csp->csp_mode) {
2408 case CSP_MODE_CIPHER:
2409 case CSP_MODE_ETA:
2410 if (!CRYPTO_OP_IS_ENCRYPT(crp->crp_op))
2411 cmd->base_masks |= HIFN_BASE_CMD_DECODE;
2412 cmd->base_masks |= HIFN_BASE_CMD_CRYPT;
2413 switch (csp->csp_cipher_alg) {
2414 case CRYPTO_AES_CBC:
2415 cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_AES |
2416 HIFN_CRYPT_CMD_MODE_CBC |
2417 HIFN_CRYPT_CMD_NEW_IV;
2418 break;
2419 default:
2420 err = EINVAL;
2421 goto errout;
2422 }
2423 crypto_read_iv(crp, cmd->iv);
2424
2425 if (crp->crp_cipher_key != NULL)
2426 cmd->ck = crp->crp_cipher_key;
2427 else
2428 cmd->ck = csp->csp_cipher_key;
2429 cmd->cklen = csp->csp_cipher_klen;
2430 cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY;
2431
2432 /*
2433 * Need to specify the size for the AES key in the masks.
2434 */
2435 if ((cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) ==
2436 HIFN_CRYPT_CMD_ALG_AES) {
2437 switch (cmd->cklen) {
2438 case 16:
2439 cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_128;
2440 break;
2441 case 24:
2442 cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_192;
2443 break;
2444 case 32:
2445 cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_256;
2446 break;
2447 default:
2448 err = EINVAL;
2449 goto errout;
2450 }
2451 }
2452 break;
2453 }
2454
2455 switch (csp->csp_mode) {
2456 case CSP_MODE_DIGEST:
2457 case CSP_MODE_ETA:
2458 cmd->base_masks |= HIFN_BASE_CMD_MAC;
2459
2460 switch (csp->csp_auth_alg) {
2461 case CRYPTO_SHA1:
2462 cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 |
2463 HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH |
2464 HIFN_MAC_CMD_POS_IPSEC;
2465 break;
2466 case CRYPTO_SHA1_HMAC:
2467 cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 |
2468 HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC |
2469 HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC;
2470 break;
2471 }
2472
2473 if (csp->csp_auth_alg == CRYPTO_SHA1_HMAC) {
2474 cmd->mac_masks |= HIFN_MAC_CMD_NEW_KEY;
2475 if (crp->crp_auth_key != NULL)
2476 mackey = crp->crp_auth_key;
2477 else
2478 mackey = csp->csp_auth_key;
2479 keylen = csp->csp_auth_klen;
2480 bcopy(mackey, cmd->mac, keylen);
2481 bzero(cmd->mac + keylen, HIFN_MAC_KEY_LENGTH - keylen);
2482 }
2483 }
2484
2485 cmd->crp = crp;
2486 cmd->session = ses;
2487 cmd->softc = sc;
2488
2489 err = hifn_crypto(sc, cmd, crp, hint);
2490 if (!err) {
2491 return 0;
2492 } else if (err == ERESTART) {
2493 /*
2494 * There weren't enough resources to dispatch the request
2495 * to the part. Notify the caller so they'll requeue this
2496 * request and resubmit it again soon.
2497 */
2498 #ifdef HIFN_DEBUG
2499 if (hifn_debug)
2500 device_printf(sc->sc_dev, "requeue request\n");
2501 #endif
2502 free(cmd, M_DEVBUF);
2503 sc->sc_needwakeup |= CRYPTO_SYMQ;
2504 return (err);
2505 }
2506
2507 errout:
2508 if (cmd != NULL)
2509 free(cmd, M_DEVBUF);
2510 if (err == EINVAL)
2511 hifnstats.hst_invalid++;
2512 else
2513 hifnstats.hst_nomem++;
2514 crp->crp_etype = err;
2515 crypto_done(crp);
2516 return (0);
2517 }
2518
2519 static void
hifn_abort(struct hifn_softc * sc)2520 hifn_abort(struct hifn_softc *sc)
2521 {
2522 struct hifn_dma *dma = sc->sc_dma;
2523 struct hifn_command *cmd;
2524 struct cryptop *crp;
2525 int i, u;
2526
2527 i = sc->sc_resk; u = sc->sc_resu;
2528 while (u != 0) {
2529 cmd = sc->sc_hifn_commands[i];
2530 KASSERT(cmd != NULL, ("hifn_abort: null command slot %u", i));
2531 sc->sc_hifn_commands[i] = NULL;
2532 crp = cmd->crp;
2533
2534 if ((dma->resr[i].l & htole32(HIFN_D_VALID)) == 0) {
2535 /* Salvage what we can. */
2536 u_int8_t *macbuf;
2537
2538 if (cmd->base_masks & HIFN_BASE_CMD_MAC) {
2539 macbuf = dma->result_bufs[i];
2540 macbuf += 12;
2541 } else
2542 macbuf = NULL;
2543 hifnstats.hst_opackets++;
2544 hifn_callback(sc, cmd, macbuf);
2545 } else {
2546 if (cmd->src_map == cmd->dst_map) {
2547 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2548 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2549 } else {
2550 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2551 BUS_DMASYNC_POSTWRITE);
2552 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map,
2553 BUS_DMASYNC_POSTREAD);
2554 }
2555
2556 if (cmd->dst_m != NULL) {
2557 m_freem(cmd->dst_m);
2558 }
2559
2560 /* non-shared buffers cannot be restarted */
2561 if (cmd->src_map != cmd->dst_map) {
2562 /*
2563 * XXX should be EAGAIN, delayed until
2564 * after the reset.
2565 */
2566 crp->crp_etype = ENOMEM;
2567 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map);
2568 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map);
2569 } else
2570 crp->crp_etype = ENOMEM;
2571
2572 bus_dmamap_unload(sc->sc_dmat, cmd->src_map);
2573 bus_dmamap_destroy(sc->sc_dmat, cmd->src_map);
2574
2575 free(cmd, M_DEVBUF);
2576 if (crp->crp_etype != EAGAIN)
2577 crypto_done(crp);
2578 }
2579
2580 if (++i == HIFN_D_RES_RSIZE)
2581 i = 0;
2582 u--;
2583 }
2584 sc->sc_resk = i; sc->sc_resu = u;
2585
2586 hifn_reset_board(sc, 1);
2587 hifn_init_dma(sc);
2588 hifn_init_pci_registers(sc);
2589 }
2590
2591 static void
hifn_callback(struct hifn_softc * sc,struct hifn_command * cmd,u_int8_t * macbuf)2592 hifn_callback(struct hifn_softc *sc, struct hifn_command *cmd, u_int8_t *macbuf)
2593 {
2594 struct hifn_dma *dma = sc->sc_dma;
2595 struct cryptop *crp = cmd->crp;
2596 uint8_t macbuf2[SHA1_HASH_LEN];
2597 struct mbuf *m;
2598 int totlen, i, u;
2599
2600 if (cmd->src_map == cmd->dst_map) {
2601 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2602 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2603 } else {
2604 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2605 BUS_DMASYNC_POSTWRITE);
2606 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map,
2607 BUS_DMASYNC_POSTREAD);
2608 }
2609
2610 if (crp->crp_buf.cb_type == CRYPTO_BUF_MBUF) {
2611 if (cmd->dst_m != NULL) {
2612 totlen = cmd->src_mapsize;
2613 for (m = cmd->dst_m; m != NULL; m = m->m_next) {
2614 if (totlen < m->m_len) {
2615 m->m_len = totlen;
2616 totlen = 0;
2617 } else
2618 totlen -= m->m_len;
2619 }
2620 cmd->dst_m->m_pkthdr.len =
2621 crp->crp_buf.cb_mbuf->m_pkthdr.len;
2622 m_freem(crp->crp_buf.cb_mbuf);
2623 crp->crp_buf.cb_mbuf = cmd->dst_m;
2624 }
2625 }
2626
2627 if (cmd->sloplen != 0) {
2628 crypto_copyback(crp, cmd->src_mapsize - cmd->sloplen,
2629 cmd->sloplen, &dma->slop[cmd->slopidx]);
2630 }
2631
2632 i = sc->sc_dstk; u = sc->sc_dstu;
2633 while (u != 0) {
2634 if (i == HIFN_D_DST_RSIZE)
2635 i = 0;
2636 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
2637 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2638 if (dma->dstr[i].l & htole32(HIFN_D_VALID)) {
2639 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
2640 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2641 break;
2642 }
2643 i++, u--;
2644 }
2645 sc->sc_dstk = i; sc->sc_dstu = u;
2646
2647 hifnstats.hst_obytes += cmd->dst_mapsize;
2648
2649 if (macbuf != NULL) {
2650 if (crp->crp_op & CRYPTO_OP_VERIFY_DIGEST) {
2651 crypto_copydata(crp, crp->crp_digest_start,
2652 cmd->session->hs_mlen, macbuf2);
2653 if (timingsafe_bcmp(macbuf, macbuf2,
2654 cmd->session->hs_mlen) != 0)
2655 crp->crp_etype = EBADMSG;
2656 } else
2657 crypto_copyback(crp, crp->crp_digest_start,
2658 cmd->session->hs_mlen, macbuf);
2659 }
2660
2661 if (cmd->src_map != cmd->dst_map) {
2662 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map);
2663 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map);
2664 }
2665 bus_dmamap_unload(sc->sc_dmat, cmd->src_map);
2666 bus_dmamap_destroy(sc->sc_dmat, cmd->src_map);
2667 free(cmd, M_DEVBUF);
2668 crypto_done(crp);
2669 }
2670
2671 /*
2672 * 7811 PB3 rev/2 parts lock-up on burst writes to Group 0
2673 * and Group 1 registers; avoid conditions that could create
2674 * burst writes by doing a read in between the writes.
2675 *
2676 * NB: The read we interpose is always to the same register;
2677 * we do this because reading from an arbitrary (e.g. last)
2678 * register may not always work.
2679 */
2680 static void
hifn_write_reg_0(struct hifn_softc * sc,bus_size_t reg,u_int32_t val)2681 hifn_write_reg_0(struct hifn_softc *sc, bus_size_t reg, u_int32_t val)
2682 {
2683 if (sc->sc_flags & HIFN_IS_7811) {
2684 if (sc->sc_bar0_lastreg == reg - 4)
2685 bus_space_read_4(sc->sc_st0, sc->sc_sh0, HIFN_0_PUCNFG);
2686 sc->sc_bar0_lastreg = reg;
2687 }
2688 bus_space_write_4(sc->sc_st0, sc->sc_sh0, reg, val);
2689 }
2690
2691 static void
hifn_write_reg_1(struct hifn_softc * sc,bus_size_t reg,u_int32_t val)2692 hifn_write_reg_1(struct hifn_softc *sc, bus_size_t reg, u_int32_t val)
2693 {
2694 if (sc->sc_flags & HIFN_IS_7811) {
2695 if (sc->sc_bar1_lastreg == reg - 4)
2696 bus_space_read_4(sc->sc_st1, sc->sc_sh1, HIFN_1_REVID);
2697 sc->sc_bar1_lastreg = reg;
2698 }
2699 bus_space_write_4(sc->sc_st1, sc->sc_sh1, reg, val);
2700 }
2701
2702 #ifdef HIFN_VULCANDEV
2703 /*
2704 * this code provides support for mapping the PK engine's register
2705 * into a userspace program.
2706 *
2707 */
2708 static int
vulcanpk_mmap(struct cdev * dev,vm_ooffset_t offset,vm_paddr_t * paddr,int nprot,vm_memattr_t * memattr)2709 vulcanpk_mmap(struct cdev *dev, vm_ooffset_t offset,
2710 vm_paddr_t *paddr, int nprot, vm_memattr_t *memattr)
2711 {
2712 struct hifn_softc *sc;
2713 vm_paddr_t pd;
2714 void *b;
2715
2716 sc = dev->si_drv1;
2717
2718 pd = rman_get_start(sc->sc_bar1res);
2719 b = rman_get_virtual(sc->sc_bar1res);
2720
2721 #if 0
2722 printf("vpk mmap: %p(%016llx) offset=%lld\n", b,
2723 (unsigned long long)pd, offset);
2724 hexdump(b, HIFN_1_PUB_MEMEND, "vpk", 0);
2725 #endif
2726
2727 if (offset == 0) {
2728 *paddr = pd;
2729 return (0);
2730 }
2731 return (-1);
2732 }
2733
2734 static struct cdevsw vulcanpk_cdevsw = {
2735 .d_version = D_VERSION,
2736 .d_mmap = vulcanpk_mmap,
2737 .d_name = "vulcanpk",
2738 };
2739 #endif /* HIFN_VULCANDEV */
2740