1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2012-2016 Ruslan Bukin <br@bsdpad.com> 5 * Copyright (c) 2023-2024 Florian Walpen <dev@submerge.ch> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #define PCI_VENDOR_XILINX 0x10ee 31 #define PCI_VENDOR_RME 0x1d18 /* Newer firmware versions. */ 32 #define PCI_DEVICE_XILINX_HDSPE 0x3fc6 /* AIO, MADI, AES, RayDAT */ 33 #define PCI_CLASS_REVISION 0x08 34 #define PCI_REVISION_AIO 212 35 #define PCI_REVISION_RAYDAT 211 36 37 #define HDSPE_AIO 0 38 #define HDSPE_RAYDAT 1 39 40 /* Hardware mixer */ 41 #define HDSPE_OUT_ENABLE_BASE 512 42 #define HDSPE_IN_ENABLE_BASE 768 43 #define HDSPE_MIXER_BASE 32768 44 #define HDSPE_MAX_GAIN 32768 45 46 /* Buffer */ 47 #define HDSPE_PAGE_ADDR_BUF_OUT 8192 48 #define HDSPE_PAGE_ADDR_BUF_IN (HDSPE_PAGE_ADDR_BUF_OUT + 64 * 16 * 4) 49 #define HDSPE_BUF_POSITION_MASK 0x000FFC0 50 51 /* Frequency */ 52 #define HDSPE_FREQ_0 (1 << 6) 53 #define HDSPE_FREQ_1 (1 << 7) 54 #define HDSPE_FREQ_DOUBLE (1 << 8) 55 #define HDSPE_FREQ_QUAD (1 << 31) 56 57 #define HDSPE_FREQ_32000 HDSPE_FREQ_0 58 #define HDSPE_FREQ_44100 HDSPE_FREQ_1 59 #define HDSPE_FREQ_48000 (HDSPE_FREQ_0 | HDSPE_FREQ_1) 60 #define HDSPE_FREQ_MASK (HDSPE_FREQ_0 | HDSPE_FREQ_1 | \ 61 HDSPE_FREQ_DOUBLE | HDSPE_FREQ_QUAD) 62 #define HDSPE_FREQ_MASK_DEFAULT HDSPE_FREQ_48000 63 #define HDSPE_FREQ_REG 256 64 #define HDSPE_FREQ_AIO 104857600000000ULL 65 66 #define HDSPE_SPEED_DEFAULT 48000 67 68 /* Latency */ 69 #define HDSPE_LAT_0 (1 << 1) 70 #define HDSPE_LAT_1 (1 << 2) 71 #define HDSPE_LAT_2 (1 << 3) 72 #define HDSPE_LAT_MASK (HDSPE_LAT_0 | HDSPE_LAT_1 | HDSPE_LAT_2) 73 #define HDSPE_LAT_BYTES_MAX (4096 * 4) 74 #define HDSPE_LAT_BYTES_MIN (32 * 4) 75 #define hdspe_encode_latency(x) (((x)<<1) & HDSPE_LAT_MASK) 76 77 /* Register addresses */ 78 #define HDSPE_SETTINGS_REG 0 79 #define HDSPE_CONTROL_REG 64 80 #define HDSPE_STATUS_REG 0 81 #define HDSPE_STATUS1_REG 64 82 #define HDSPE_STATUS2_REG 192 83 84 /* Settings register flags */ 85 #define HDSPE_SETTINGS_INPUT_GAIN0 (1 << 20) 86 #define HDSPE_SETTINGS_INPUT_GAIN1 (1 << 21) 87 #define HDSPE_SETTINGS_OUTPUT_GAIN0 (1 << 22) 88 #define HDSPE_SETTINGS_OUTPUT_GAIN1 (1 << 23) 89 #define HDSPE_SETTINGS_PHONES_GAIN0 (1 << 24) 90 #define HDSPE_SETTINGS_PHONES_GAIN1 (1 << 25) 91 92 /* Analog input gain level */ 93 #define HDSPE_INPUT_LEVEL_MASK (HDSPE_SETTINGS_INPUT_GAIN0 | \ 94 HDSPE_SETTINGS_INPUT_GAIN1) 95 #define HDSPE_INPUT_LEVEL_LOWGAIN 0 96 #define HDSPE_INPUT_LEVEL_PLUS4DBU (HDSPE_SETTINGS_INPUT_GAIN0) 97 #define HDSPE_INPUT_LEVEL_MINUS10DBV (HDSPE_SETTINGS_INPUT_GAIN1) 98 99 /* Analog output gain level */ 100 #define HDSPE_OUTPUT_LEVEL_MASK (HDSPE_SETTINGS_OUTPUT_GAIN0 | \ 101 HDSPE_SETTINGS_OUTPUT_GAIN1) 102 #define HDSPE_OUTPUT_LEVEL_HIGHGAIN 0 103 #define HDSPE_OUTPUT_LEVEL_PLUS4DBU (HDSPE_SETTINGS_OUTPUT_GAIN0) 104 #define HDSPE_OUTPUT_LEVEL_MINUS10DBV (HDSPE_SETTINGS_OUTPUT_GAIN1) 105 106 /* Phones output gain level */ 107 #define HDSPE_PHONES_LEVEL_MASK (HDSPE_SETTINGS_PHONES_GAIN0 | \ 108 HDSPE_SETTINGS_PHONES_GAIN1) 109 #define HDSPE_PHONES_LEVEL_HIGHGAIN 0 110 #define HDSPE_PHONES_LEVEL_PLUS4DBU (HDSPE_SETTINGS_PHONES_GAIN0) 111 #define HDSPE_PHONES_LEVEL_MINUS10DBV (HDSPE_SETTINGS_PHONES_GAIN1) 112 113 /* Control register flags */ 114 #define HDSPE_ENABLE (1 << 0) 115 116 /* Interrupts */ 117 #define HDSPE_AUDIO_IRQ_PENDING (1 << 0) 118 #define HDSPE_AUDIO_INT_ENABLE (1 << 5) 119 #define HDSPE_INTERRUPT_ACK 96 120 121 /* Channels */ 122 #define HDSPE_MAX_SLOTS 64 /* Mono channels */ 123 #define HDSPE_MAX_CHANS (HDSPE_MAX_SLOTS / 2) /* Stereo pairs */ 124 125 #define HDSPE_CHANBUF_SAMPLES (16 * 1024) 126 #define HDSPE_CHANBUF_SIZE (4 * HDSPE_CHANBUF_SAMPLES) 127 #define HDSPE_DMASEGSIZE (HDSPE_CHANBUF_SIZE * HDSPE_MAX_SLOTS) 128 129 #define HDSPE_CHAN_AIO_LINE (1 << 0) 130 #define HDSPE_CHAN_AIO_EXT (1 << 1) 131 #define HDSPE_CHAN_AIO_PHONE (1 << 2) 132 #define HDSPE_CHAN_AIO_AES (1 << 3) 133 #define HDSPE_CHAN_AIO_SPDIF (1 << 4) 134 #define HDSPE_CHAN_AIO_ADAT (1 << 5) 135 #define HDSPE_CHAN_AIO_ALL_REC (HDSPE_CHAN_AIO_LINE | \ 136 HDSPE_CHAN_AIO_EXT | \ 137 HDSPE_CHAN_AIO_AES | \ 138 HDSPE_CHAN_AIO_SPDIF | \ 139 HDSPE_CHAN_AIO_ADAT) 140 #define HDSPE_CHAN_AIO_ALL (HDSPE_CHAN_AIO_ALL_REC | \ 141 HDSPE_CHAN_AIO_PHONE) \ 142 143 #define HDSPE_CHAN_RAY_AES (1 << 6) 144 #define HDSPE_CHAN_RAY_SPDIF (1 << 7) 145 #define HDSPE_CHAN_RAY_ADAT1 (1 << 8) 146 #define HDSPE_CHAN_RAY_ADAT2 (1 << 9) 147 #define HDSPE_CHAN_RAY_ADAT3 (1 << 10) 148 #define HDSPE_CHAN_RAY_ADAT4 (1 << 11) 149 #define HDSPE_CHAN_RAY_ALL (HDSPE_CHAN_RAY_AES | \ 150 HDSPE_CHAN_RAY_SPDIF | \ 151 HDSPE_CHAN_RAY_ADAT1 | \ 152 HDSPE_CHAN_RAY_ADAT2 | \ 153 HDSPE_CHAN_RAY_ADAT3 | \ 154 HDSPE_CHAN_RAY_ADAT4) 155 156 struct hdspe_channel { 157 uint32_t ports; 158 char *descr; 159 }; 160 161 /* Clock sources */ 162 #define HDSPE_SETTING_MASTER (1 << 0) 163 #define HDSPE_SETTING_CLOCK_MASK 0x1f 164 165 #define HDSPE_STATUS1_CLOCK_SHIFT 28 166 #define HDSPE_STATUS1_CLOCK_MASK (0x0f << HDSPE_STATUS1_CLOCK_SHIFT) 167 #define HDSPE_STATUS1_CLOCK(n) (((n) << HDSPE_STATUS1_CLOCK_SHIFT) & \ 168 HDSPE_STATUS1_CLOCK_MASK) 169 170 struct hdspe_clock_source { 171 char *name; 172 uint32_t setting; 173 uint32_t status; 174 uint32_t lock_bit; 175 uint32_t sync_bit; 176 }; 177 178 static MALLOC_DEFINE(M_HDSPE, "hdspe", "hdspe audio"); 179 180 /* Channel registers */ 181 struct sc_chinfo { 182 struct snd_dbuf *buffer; 183 struct pcm_channel *channel; 184 struct sc_pcminfo *parent; 185 186 /* Channel information */ 187 struct pcmchan_caps *caps; 188 uint32_t cap_fmts[4]; 189 uint32_t dir; 190 uint32_t format; 191 uint32_t ports; 192 uint32_t lvol; 193 uint32_t rvol; 194 195 /* Buffer */ 196 uint32_t *data; 197 uint32_t size; 198 uint32_t position; 199 200 /* Flags */ 201 uint32_t run; 202 }; 203 204 /* PCM device private data */ 205 struct sc_pcminfo { 206 device_t dev; 207 uint32_t (*ih) (struct sc_pcminfo *scp); 208 uint32_t chnum; 209 struct sc_chinfo chan[HDSPE_MAX_CHANS]; 210 struct sc_info *sc; 211 struct hdspe_channel *hc; 212 }; 213 214 /* HDSPe device private data */ 215 struct sc_info { 216 device_t dev; 217 struct mtx *lock; 218 219 uint32_t ctrl_register; 220 uint32_t settings_register; 221 uint32_t type; 222 223 /* Control/Status register */ 224 struct resource *cs; 225 int csid; 226 bus_space_tag_t cst; 227 bus_space_handle_t csh; 228 229 struct resource *irq; 230 int irqid; 231 void *ih; 232 bus_dma_tag_t dmat; 233 234 /* Play/Record DMA buffers */ 235 uint32_t *pbuf; 236 uint32_t *rbuf; 237 uint32_t bufsize; 238 bus_dmamap_t pmap; 239 bus_dmamap_t rmap; 240 uint32_t period; 241 uint32_t speed; 242 uint32_t force_period; 243 uint32_t force_speed; 244 }; 245 246 #define hdspe_read_1(sc, regno) \ 247 bus_space_read_1((sc)->cst, (sc)->csh, (regno)) 248 #define hdspe_read_2(sc, regno) \ 249 bus_space_read_2((sc)->cst, (sc)->csh, (regno)) 250 #define hdspe_read_4(sc, regno) \ 251 bus_space_read_4((sc)->cst, (sc)->csh, (regno)) 252 253 #define hdspe_write_1(sc, regno, data) \ 254 bus_space_write_1((sc)->cst, (sc)->csh, (regno), (data)) 255 #define hdspe_write_2(sc, regno, data) \ 256 bus_space_write_2((sc)->cst, (sc)->csh, (regno), (data)) 257 #define hdspe_write_4(sc, regno, data) \ 258 bus_space_write_4((sc)->cst, (sc)->csh, (regno), (data)) 259