| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | display_mode_core.c | 2721 TruncToValidBPP(dml_float_t LinkBitRate,dml_uint_t Lanes,dml_uint_t HTotal,dml_uint_t HActive,dml_float_t PixelClock,dml_float_t DesiredBPP,dml_bool_t DSCEnable,enum dml_output_encoder_class Output,enum dml_output_format_class Format,dml_uint_t DSCInputBitPerComponent,dml_uint_t DSCSlices,dml_uint_t AudioRate,dml_uint_t AudioLayout,enum dml_odm_mode ODMModeNoDSC,enum dml_odm_mode ODMModeDSC,dml_uint_t * RequiredSlots) TruncToValidBPP() argument
4311 CalculateSwathWidth(dml_bool_t ForceSingleDPP,dml_uint_t NumberOfActiveSurfaces,enum dml_source_format_class SourcePixelFormat[],enum dml_rotation_angle SourceScan[],dml_bool_t ViewportStationary[],dml_uint_t ViewportWidth[],dml_uint_t ViewportHeight[],dml_uint_t ViewportXStart[],dml_uint_t ViewportYStart[],dml_uint_t ViewportXStartC[],dml_uint_t ViewportYStartC[],dml_uint_t SurfaceWidthY[],dml_uint_t SurfaceWidthC[],dml_uint_t SurfaceHeightY[],dml_uint_t SurfaceHeightC[],enum dml_odm_mode ODMMode[],dml_uint_t BytePerPixY[],dml_uint_t BytePerPixC[],dml_uint_t Read256BytesBlockHeightY[],dml_uint_t Read256BytesBlockHeightC[],dml_uint_t Read256BytesBlockWidthY[],dml_uint_t Read256BytesBlockWidthC[],dml_uint_t BlendingAndTiming[],dml_uint_t HActive[],dml_float_t HRatio[],dml_uint_t DPPPerSurface[],dml_uint_t SwathWidthSingleDPPY[],dml_uint_t SwathWidthSingleDPPC[],dml_uint_t SwathWidthY[],dml_uint_t SwathWidthC[],dml_uint_t MaximumSwathHeightY[],dml_uint_t MaximumSwathHeightC[],dml_uint_t swath_width_luma_ub[],dml_uint_t swath_width_chroma_ub[]) CalculateSwathWidth() argument
4598 RequiredDTBCLK(dml_bool_t DSCEnable,dml_float_t PixelClock,enum dml_output_format_class OutputFormat,dml_float_t OutputBpp,dml_uint_t DSCSlices,dml_uint_t HTotal,dml_uint_t HActive,dml_uint_t AudioRate,dml_uint_t AudioLayout) RequiredDTBCLK() argument
5367 CalculateOutputLink(dml_float_t PHYCLKPerState,dml_float_t PHYCLKD18PerState,dml_float_t PHYCLKD32PerState,dml_float_t Downspreading,dml_bool_t IsMainSurfaceUsingTheIndicatedTiming,enum dml_output_encoder_class Output,enum dml_output_format_class OutputFormat,dml_uint_t HTotal,dml_uint_t HActive,dml_float_t PixelClockBackEnd,dml_float_t ForcedOutputLinkBPP,dml_uint_t DSCInputBitPerComponent,dml_uint_t NumberOfDSCSlices,dml_float_t AudioSampleRate,dml_uint_t AudioSampleLayout,enum dml_odm_mode ODMModeNoDSC,enum dml_odm_mode ODMModeDSC,enum dml_dsc_enable DSCEnable,dml_uint_t OutputLinkDPLanes,enum dml_output_link_dp_rate OutputLinkDPRate,dml_bool_t * RequiresDSC,dml_bool_t * RequiresFEC,dml_float_t * OutBpp,enum dml_output_type_and_rate__type * OutputType,enum dml_output_type_and_rate__rate * OutputRate,dml_uint_t * RequiredSlots) CalculateOutputLink() argument
5526 CalculateODMMode(dml_uint_t MaximumPixelsPerLinePerDSCUnit,dml_uint_t HActive,enum dml_output_encoder_class Output,enum dml_output_format_class OutputFormat,enum dml_odm_use_policy ODMUse,dml_float_t StateDispclk,dml_float_t MaxDispclk,dml_bool_t DSCEnable,dml_uint_t TotalNumberOfActiveDPP,dml_uint_t MaxNumDPP,dml_float_t PixelClock,dml_float_t DISPCLKDPPCLKDSCCLKDownSpreading,dml_float_t DISPCLKRampingMargin,dml_float_t DISPCLKDPPCLKVCOSpeed,dml_uint_t NumberOfDSCSlices,dml_bool_t * TotalAvailablePipesSupport,dml_uint_t * NumberOfDPP,enum dml_odm_mode * ODMMode,dml_float_t * RequiredDISPCLKPerSurface) CalculateODMMode() argument
5892 DSCDelayRequirement(dml_bool_t DSCEnabled,enum dml_odm_mode ODMMode,dml_uint_t DSCInputBitPerComponent,dml_float_t OutputBpp,dml_uint_t HActive,dml_uint_t HTotal,dml_uint_t NumberOfDSCSlices,enum dml_output_format_class OutputFormat,enum dml_output_encoder_class Output,dml_float_t PixelClock,dml_float_t PixelClockBackEnd) DSCDelayRequirement() argument
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| H A D | display_mode_core_structs.h | 468 dml_uint_t HActive; member
610 dml_uint_t HActive[__DML_NUM_PLANES__]; member
1501 dml_uint_t *HActive; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/ |
| H A D | dml2_core_dcn4_calcs.c | 1271 TruncToValidBPP(struct dml2_core_shared_TruncToValidBPP_locals * l,double LinkBitRate,unsigned int Lanes,unsigned int HTotal,unsigned int HActive,double PixelClock,double DesiredBPP,bool DSCEnable,enum dml2_output_encoder_class Output,enum dml2_output_format_class Format,unsigned int DSCInputBitPerComponent,unsigned int DSCSlices,unsigned int AudioRate,unsigned int AudioLayout,enum dml2_odm_mode ODMModeNoDSC,enum dml2_odm_mode ODMModeDSC,unsigned int * RequiredSlots) TruncToValidBPP() argument
3963 DecideODMMode(unsigned int HActive,double MaxDispclk,unsigned int MaximumPixelsPerLinePerDSCUnit,enum dml2_output_format_class OutFormat,bool UseDSC,unsigned int NumberOfDSCSlices,double SurfaceRequiredDISPCLKWithoutODMCombine,double SurfaceRequiredDISPCLKWithODMCombineTwoToOne,double SurfaceRequiredDISPCLKWithODMCombineThreeToOne,double SurfaceRequiredDISPCLKWithODMCombineFourToOne) DecideODMMode() argument
4061 ValidateODMMode(enum dml2_odm_mode ODMMode,double MaxDispclk,unsigned int HActive,enum dml2_output_format_class OutFormat,bool UseDSC,unsigned int NumberOfDSCSlices,unsigned int TotalNumberOfActiveDPP,unsigned int TotalNumberOfActiveOPP,unsigned int MaxNumDPP,unsigned int MaxNumOPP,double DISPCLKRequired,unsigned int NumberOfDPPRequired,unsigned int MaxHActiveForDSC,unsigned int MaxDSCSlices,unsigned int MaxHActiveFor420) ValidateODMMode() argument
4123 CalculateODMMode(unsigned int MaximumPixelsPerLinePerDSCUnit,unsigned int HActive,enum dml2_output_format_class OutFormat,enum dml2_output_encoder_class Output,enum dml2_odm_mode ODMUse,double MaxDispclk,bool DSCEnable,unsigned int TotalNumberOfActiveDPP,unsigned int TotalNumberOfActiveOPP,unsigned int MaxNumDPP,unsigned int MaxNumOPP,double PixelClock,unsigned int NumberOfDSCSlices,bool * TotalAvailablePipesSupport,unsigned int * NumberOfDPP,enum dml2_odm_mode * ODMMode,double * RequiredDISPCLKPerSurface) CalculateODMMode() argument
4232 CalculateOutputLink(struct dml2_core_internal_scratch * s,double PHYCLK,double PHYCLKD18,double PHYCLKD32,double Downspreading,enum dml2_output_encoder_class Output,enum dml2_output_format_class OutputFormat,unsigned int HTotal,unsigned int HActive,double PixelClockBackEnd,double ForcedOutputLinkBPP,unsigned int DSCInputBitPerComponent,unsigned int NumberOfDSCSlices,double AudioSampleRate,unsigned int AudioSampleLayout,enum dml2_odm_mode ODMModeNoDSC,enum dml2_odm_mode ODMModeDSC,enum dml2_dsc_enable_option DSCEnable,unsigned int OutputLinkDPLanes,enum dml2_output_link_dp_rate OutputLinkDPRate,bool * RequiresDSC,bool * RequiresFEC,double * OutBpp,enum dml2_core_internal_output_type * OutputType,enum dml2_core_internal_output_type_rate * OutputRate,unsigned int * RequiredSlots) CalculateOutputLink() argument
4493 RequiredDTBCLK(bool DSCEnable,double PixelClock,enum dml2_output_format_class OutputFormat,double OutputBpp,unsigned int DSCSlices,unsigned int HTotal,unsigned int HActive,unsigned int AudioRate,unsigned int AudioLayout) RequiredDTBCLK() argument
4514 DSCDelayRequirement(bool DSCEnabled,enum dml2_odm_mode ODMMode,unsigned int DSCInputBitPerComponent,double OutputBpp,unsigned int HActive,unsigned int HTotal,unsigned int NumberOfDSCSlices,enum dml2_output_format_class OutputFormat,enum dml2_output_encoder_class Output,double PixelClock,double PixelClockBackEnd) DSCDelayRequirement() argument
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| H A D | dml2_core_shared_types.h | 126 unsigned int HActive; global() member
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_structs.h | 116 unsigned int HActive; member
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| H A D | display_mode_vba.h | 496 unsigned int HActive[DC__NUM_DPP__MAX]; member
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