1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DISPLAY_DEVICE_H__ 7 #define __INTEL_DISPLAY_DEVICE_H__ 8 9 #include <linux/bitops.h> 10 #include <linux/types.h> 11 12 #include "intel_display_conversion.h" 13 #include "intel_display_limits.h" 14 15 struct drm_printer; 16 struct intel_display; 17 struct pci_dev; 18 19 /* 20 * Display platforms and subplatforms. Keep platforms in display version based 21 * order, chronological order within a version, and subplatforms next to the 22 * platform. 23 */ 24 #define INTEL_DISPLAY_PLATFORMS(func) \ 25 /* Platform group aliases */ \ 26 func(g4x) /* g45 and gm45 */ \ 27 func(mobile) /* mobile platforms */ \ 28 func(dgfx) /* discrete graphics */ \ 29 /* Display ver 2 */ \ 30 func(i830) \ 31 func(i845g) \ 32 func(i85x) \ 33 func(i865g) \ 34 /* Display ver 3 */ \ 35 func(i915g) \ 36 func(i915gm) \ 37 func(i945g) \ 38 func(i945gm) \ 39 func(g33) \ 40 func(pineview) \ 41 /* Display ver 4 */ \ 42 func(i965g) \ 43 func(i965gm) \ 44 func(g45) \ 45 func(gm45) \ 46 /* Display ver 5 */ \ 47 func(ironlake) \ 48 /* Display ver 6 */ \ 49 func(sandybridge) \ 50 /* Display ver 7 */ \ 51 func(ivybridge) \ 52 func(valleyview) \ 53 func(haswell) \ 54 func(haswell_ult) \ 55 func(haswell_ulx) \ 56 /* Display ver 8 */ \ 57 func(broadwell) \ 58 func(broadwell_ult) \ 59 func(broadwell_ulx) \ 60 func(cherryview) \ 61 /* Display ver 9 */ \ 62 func(skylake) \ 63 func(skylake_ult) \ 64 func(skylake_ulx) \ 65 func(broxton) \ 66 func(kabylake) \ 67 func(kabylake_ult) \ 68 func(kabylake_ulx) \ 69 func(geminilake) \ 70 func(coffeelake) \ 71 func(coffeelake_ult) \ 72 func(coffeelake_ulx) \ 73 func(cometlake) \ 74 func(cometlake_ult) \ 75 func(cometlake_ulx) \ 76 /* Display ver 11 */ \ 77 func(icelake) \ 78 func(icelake_port_f) \ 79 func(jasperlake) \ 80 func(elkhartlake) \ 81 /* Display ver 12 */ \ 82 func(tigerlake) \ 83 func(tigerlake_uy) \ 84 func(rocketlake) \ 85 func(dg1) \ 86 func(alderlake_s) \ 87 func(alderlake_s_raptorlake_s) \ 88 /* Display ver 13 */ \ 89 func(alderlake_p) \ 90 func(alderlake_p_alderlake_n) \ 91 func(alderlake_p_raptorlake_p) \ 92 func(alderlake_p_raptorlake_u) \ 93 func(dg2) \ 94 func(dg2_g10) \ 95 func(dg2_g11) \ 96 func(dg2_g12) \ 97 /* Display ver 14 (based on GMD ID) */ \ 98 func(meteorlake) \ 99 func(meteorlake_u) \ 100 /* Display ver 20 (based on GMD ID) */ \ 101 func(lunarlake) \ 102 /* Display ver 14.1 (based on GMD ID) */ \ 103 func(battlemage) \ 104 /* Display ver 30 (based on GMD ID) */ \ 105 func(pantherlake) 106 107 #define __MEMBER(name) unsigned long name:1; 108 #define __COUNT(x) 1 + 109 110 #define __NUM_PLATFORMS (INTEL_DISPLAY_PLATFORMS(__COUNT) 0) 111 112 struct intel_display_platforms { 113 union { 114 struct { 115 INTEL_DISPLAY_PLATFORMS(__MEMBER); 116 }; 117 DECLARE_BITMAP(bitmap, __NUM_PLATFORMS); 118 }; 119 }; 120 121 #undef __MEMBER 122 #undef __COUNT 123 #undef __NUM_PLATFORMS 124 125 #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \ 126 /* Keep in alphabetical order */ \ 127 func(cursor_needs_physical); \ 128 func(has_cdclk_crawl); \ 129 func(has_cdclk_squash); \ 130 func(has_ddi); \ 131 func(has_dp_mst); \ 132 func(has_dsb); \ 133 func(has_fpga_dbg); \ 134 func(has_gmch); \ 135 func(has_hotplug); \ 136 func(has_hti); \ 137 func(has_ipc); \ 138 func(has_overlay); \ 139 func(has_psr); \ 140 func(has_psr_hw_tracking); \ 141 func(overlay_needs_physical); \ 142 func(supports_tv); 143 144 #define HAS_4TILE(__display) ((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14) 145 #define HAS_ASYNC_FLIPS(__display) (DISPLAY_VER(__display) >= 5) 146 #define HAS_AS_SDP(__display) (DISPLAY_VER(__display) >= 13) 147 #define HAS_BIGJOINER(__display) (DISPLAY_VER(__display) >= 11 && HAS_DSC(__display)) 148 #define HAS_CDCLK_CRAWL(__display) (DISPLAY_INFO(__display)->has_cdclk_crawl) 149 #define HAS_CDCLK_SQUASH(__display) (DISPLAY_INFO(__display)->has_cdclk_squash) 150 #define HAS_CMRR(__display) (DISPLAY_VER(__display) >= 20) 151 #define HAS_CMTG(__display) (!(__display)->platform.dg2 && DISPLAY_VER(__display) >= 13) 152 #define HAS_CUR_FBC(__display) (!HAS_GMCH(__display) && IS_DISPLAY_VER(__display, 7, 13)) 153 #define HAS_D12_PLANE_MINIMIZATION(__display) ((__display)->platform.rocketlake || (__display)->platform.alderlake_s) 154 #define HAS_DBUF_OVERLAP_DETECTION(__display) (DISPLAY_RUNTIME_INFO(__display)->has_dbuf_overlap_detection) 155 #define HAS_DDI(__display) (DISPLAY_INFO(__display)->has_ddi) 156 #define HAS_DISPLAY(__display) (DISPLAY_RUNTIME_INFO(__display)->pipe_mask != 0) 157 #define HAS_DMC(__display) (DISPLAY_RUNTIME_INFO(__display)->has_dmc) 158 #define HAS_DMC_WAKELOCK(__display) (DISPLAY_VER(__display) >= 20) 159 #define HAS_DOUBLE_BUFFERED_M_N(__display) (DISPLAY_VER(__display) >= 9 || (__display)->platform.broadwell) 160 #define HAS_DOUBLE_WIDE(__display) (DISPLAY_VER(__display) < 4) 161 #define HAS_DP20(__display) ((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14) 162 #define HAS_DPT(__display) (DISPLAY_VER(__display) >= 13) 163 #define HAS_DP_MST(__display) (DISPLAY_INFO(__display)->has_dp_mst) 164 #define HAS_DSB(__display) (DISPLAY_INFO(__display)->has_dsb) 165 #define HAS_DSC(__display) (DISPLAY_RUNTIME_INFO(__display)->has_dsc) 166 #define HAS_DSC_3ENGINES(__display) (DISPLAY_VERx100(__display) == 1401 && HAS_DSC(__display)) 167 #define HAS_DSC_MST(__display) (DISPLAY_VER(__display) >= 12 && HAS_DSC(__display)) 168 #define HAS_FBC(__display) (DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0) 169 #define HAS_FBC_DIRTY_RECT(__display) (DISPLAY_VER(__display) >= 30) 170 #define HAS_FPGA_DBG_UNCLAIMED(__display) (DISPLAY_INFO(__display)->has_fpga_dbg) 171 #define HAS_FW_BLC(__display) (DISPLAY_VER(__display) >= 3) 172 #define HAS_GMBUS_BURST_READ(__display) (DISPLAY_VER(__display) >= 10 || (__display)->platform.kabylake) 173 #define HAS_GMBUS_IRQ(__display) (DISPLAY_VER(__display) >= 4) 174 #define HAS_GMCH(__display) (DISPLAY_INFO(__display)->has_gmch) 175 #define HAS_HOTPLUG(__display) (DISPLAY_INFO(__display)->has_hotplug) 176 #define HAS_HW_SAGV_WM(__display) (DISPLAY_VER(__display) >= 13 && !(__display)->platform.dgfx) 177 #define HAS_IPC(__display) (DISPLAY_INFO(__display)->has_ipc) 178 #define HAS_IPS(__display) ((__display)->platform.haswell_ult || (__display)->platform.broadwell) 179 #define HAS_LRR(__display) (DISPLAY_VER(__display) >= 12) 180 #define HAS_LSPCON(__display) (IS_DISPLAY_VER(__display, 9, 10)) 181 #define HAS_MBUS_JOINING(__display) ((__display)->platform.alderlake_p || DISPLAY_VER(__display) >= 14) 182 #define HAS_MSO(__display) (DISPLAY_VER(__display) >= 12) 183 #define HAS_OVERLAY(__display) (DISPLAY_INFO(__display)->has_overlay) 184 #define HAS_PSR(__display) (DISPLAY_INFO(__display)->has_psr) 185 #define HAS_PSR_HW_TRACKING(__display) (DISPLAY_INFO(__display)->has_psr_hw_tracking) 186 #define HAS_PSR2_SEL_FETCH(__display) (DISPLAY_VER(__display) >= 12) 187 #define HAS_SAGV(__display) (DISPLAY_VER(__display) >= 9 && \ 188 !(__display)->platform.broxton && !(__display)->platform.geminilake) 189 #define HAS_TRANSCODER(__display, trans) ((DISPLAY_RUNTIME_INFO(__display)->cpu_transcoder_mask & \ 190 BIT(trans)) != 0) 191 #define HAS_UNCOMPRESSED_JOINER(__display) (DISPLAY_VER(__display) >= 13) 192 #define HAS_ULTRAJOINER(__display) ((DISPLAY_VER(__display) >= 20 || \ 193 ((__display)->platform.dgfx && DISPLAY_VER(__display) == 14)) && \ 194 HAS_DSC(__display)) 195 #define HAS_VRR(__display) (DISPLAY_VER(__display) >= 11) 196 #define INTEL_NUM_PIPES(__display) (hweight8(DISPLAY_RUNTIME_INFO(__display)->pipe_mask)) 197 #define OVERLAY_NEEDS_PHYSICAL(__display) (DISPLAY_INFO(__display)->overlay_needs_physical) 198 #define SUPPORTS_TV(__display) (DISPLAY_INFO(__display)->supports_tv) 199 200 /* Check that device has a display IP version within the specific range. */ 201 #define IS_DISPLAY_VERx100(__display, from, until) ( \ 202 BUILD_BUG_ON_ZERO((from) < 200) + \ 203 (DISPLAY_VERx100(__display) >= (from) && \ 204 DISPLAY_VERx100(__display) <= (until))) 205 206 /* 207 * Check if a device has a specific IP version as well as a stepping within the 208 * specified range [from, until). The lower bound is inclusive, the upper 209 * bound is exclusive. The most common use-case of this macro is for checking 210 * bounds for workarounds, which usually have a stepping ("from") at which the 211 * hardware issue is first present and another stepping ("until") at which a 212 * hardware fix is present and the software workaround is no longer necessary. 213 * E.g., 214 * 215 * IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B2) 216 * IS_DISPLAY_VERx100_STEP(display, 1400, STEP_C0, STEP_FOREVER) 217 * 218 * "STEP_FOREVER" can be passed as "until" for workarounds that have no upper 219 * stepping bound for the specified IP version. 220 */ 221 #define IS_DISPLAY_VERx100_STEP(__display, ipver, from, until) \ 222 (IS_DISPLAY_VERx100((__display), (ipver), (ipver)) && \ 223 IS_DISPLAY_STEP((__display), (from), (until))) 224 225 #define DISPLAY_INFO(__display) (__to_intel_display(__display)->info.__device_info) 226 #define DISPLAY_RUNTIME_INFO(__display) (&__to_intel_display(__display)->info.__runtime_info) 227 228 #define DISPLAY_VER(__display) (DISPLAY_RUNTIME_INFO(__display)->ip.ver) 229 #define DISPLAY_VERx100(__display) (DISPLAY_RUNTIME_INFO(__display)->ip.ver * 100 + \ 230 DISPLAY_RUNTIME_INFO(__display)->ip.rel) 231 #define IS_DISPLAY_VER(__display, from, until) \ 232 (DISPLAY_VER(__display) >= (from) && DISPLAY_VER(__display) <= (until)) 233 234 #define INTEL_DISPLAY_STEP(__display) (DISPLAY_RUNTIME_INFO(__display)->step) 235 236 #define IS_DISPLAY_STEP(__display, since, until) \ 237 (drm_WARN_ON(__to_intel_display(__display)->drm, INTEL_DISPLAY_STEP(__display) == STEP_NONE), \ 238 INTEL_DISPLAY_STEP(__display) >= (since) && INTEL_DISPLAY_STEP(__display) < (until)) 239 240 #define ARLS_HOST_BRIDGE_PCI_ID1 0x7D1C 241 #define ARLS_HOST_BRIDGE_PCI_ID2 0x7D2D 242 #define ARLS_HOST_BRIDGE_PCI_ID3 0x7D2E 243 #define ARLS_HOST_BRIDGE_PCI_ID4 0x7D2F 244 245 #define IS_ARROWLAKE_S_BY_HOST_BRIDGE_ID(id) \ 246 (((id) == ARLS_HOST_BRIDGE_PCI_ID1) || \ 247 ((id) == ARLS_HOST_BRIDGE_PCI_ID2) || \ 248 ((id) == ARLS_HOST_BRIDGE_PCI_ID3) || \ 249 ((id) == ARLS_HOST_BRIDGE_PCI_ID4)) 250 251 struct intel_display_runtime_info { 252 struct intel_display_ip_ver { 253 u16 ver; 254 u16 rel; 255 u16 step; /* hardware */ 256 } ip; 257 int step; /* symbolic */ 258 259 u32 rawclk_freq; 260 261 u8 pipe_mask; 262 u8 cpu_transcoder_mask; 263 u16 port_mask; 264 265 u8 num_sprites[I915_MAX_PIPES]; 266 u8 num_scalers[I915_MAX_PIPES]; 267 268 u8 fbc_mask; 269 270 bool has_hdcp; 271 bool has_dmc; 272 bool has_dsc; 273 bool edp_typec_support; 274 bool has_dbuf_overlap_detection; 275 }; 276 277 struct intel_display_device_info { 278 /* Initial runtime info. */ 279 const struct intel_display_runtime_info __runtime_defaults; 280 281 u8 abox_mask; 282 283 struct { 284 u16 size; /* in blocks */ 285 u8 slice_mask; 286 } dbuf; 287 288 #define DEFINE_FLAG(name) u8 name:1 289 DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG); 290 #undef DEFINE_FLAG 291 292 /* Global register offset for the display engine */ 293 u32 mmio_offset; 294 295 /* Register offsets for the various display pipes and transcoders */ 296 u32 pipe_offsets[I915_MAX_TRANSCODERS]; 297 u32 trans_offsets[I915_MAX_TRANSCODERS]; 298 u32 cursor_offsets[I915_MAX_PIPES]; 299 300 struct { 301 u32 degamma_lut_size; 302 u32 gamma_lut_size; 303 u32 degamma_lut_tests; 304 u32 gamma_lut_tests; 305 } color; 306 }; 307 308 bool intel_display_device_enabled(struct intel_display *display); 309 struct intel_display *intel_display_device_probe(struct pci_dev *pdev); 310 void intel_display_device_remove(struct intel_display *display); 311 void intel_display_device_info_runtime_init(struct intel_display *display); 312 313 void intel_display_device_info_print(const struct intel_display_device_info *info, 314 const struct intel_display_runtime_info *runtime, 315 struct drm_printer *p); 316 317 #endif 318