1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DISPLAY_DEVICE_H__ 7 #define __INTEL_DISPLAY_DEVICE_H__ 8 9 #include <linux/bitops.h> 10 #include <linux/types.h> 11 12 #include "intel_display_conversion.h" 13 #include "intel_display_limits.h" 14 15 struct drm_i915_private; 16 struct drm_printer; 17 18 /* 19 * Display platforms and subplatforms. Keep platforms in display version based 20 * order, chronological order within a version, and subplatforms next to the 21 * platform. 22 */ 23 #define INTEL_DISPLAY_PLATFORMS(func) \ 24 /* Display ver 2 */ \ 25 func(i830) \ 26 func(i845g) \ 27 func(i85x) \ 28 func(i865g) \ 29 /* Display ver 3 */ \ 30 func(i915g) \ 31 func(i915gm) \ 32 func(i945g) \ 33 func(i945gm) \ 34 func(g33) \ 35 func(pineview) \ 36 /* Display ver 4 */ \ 37 func(i965g) \ 38 func(i965gm) \ 39 func(g45) \ 40 func(gm45) \ 41 func(g4x) /* group alias for g45 and gm45 */ \ 42 /* Display ver 5 */ \ 43 func(ironlake) \ 44 /* Display ver 6 */ \ 45 func(sandybridge) \ 46 /* Display ver 7 */ \ 47 func(ivybridge) \ 48 func(valleyview) \ 49 func(haswell) \ 50 func(haswell_ult) \ 51 func(haswell_ulx) \ 52 /* Display ver 8 */ \ 53 func(broadwell) \ 54 func(broadwell_ult) \ 55 func(broadwell_ulx) \ 56 func(cherryview) \ 57 /* Display ver 9 */ \ 58 func(skylake) \ 59 func(skylake_ult) \ 60 func(skylake_ulx) \ 61 func(broxton) \ 62 func(kabylake) \ 63 func(kabylake_ult) \ 64 func(kabylake_ulx) \ 65 func(geminilake) \ 66 func(coffeelake) \ 67 func(coffeelake_ult) \ 68 func(coffeelake_ulx) \ 69 func(cometlake) \ 70 func(cometlake_ult) \ 71 func(cometlake_ulx) \ 72 /* Display ver 11 */ \ 73 func(icelake) \ 74 func(icelake_port_f) \ 75 func(jasperlake) \ 76 func(elkhartlake) \ 77 /* Display ver 12 */ \ 78 func(tigerlake) \ 79 func(tigerlake_uy) \ 80 func(rocketlake) \ 81 func(dg1) \ 82 func(alderlake_s) \ 83 func(alderlake_s_raptorlake_s) \ 84 /* Display ver 13 */ \ 85 func(alderlake_p) \ 86 func(alderlake_p_alderlake_n) \ 87 func(alderlake_p_raptorlake_p) \ 88 func(alderlake_p_raptorlake_u) \ 89 func(dg2) \ 90 func(dg2_g10) \ 91 func(dg2_g11) \ 92 func(dg2_g12) \ 93 /* Display ver 14 (based on GMD ID) */ \ 94 func(meteorlake) \ 95 /* Display ver 20 (based on GMD ID) */ \ 96 func(lunarlake) \ 97 /* Display ver 14.1 (based on GMD ID) */ \ 98 func(battlemage) \ 99 /* Display ver 30 (based on GMD ID) */ \ 100 func(pantherlake) 101 102 #define __MEMBER(name) unsigned long name:1; 103 #define __COUNT(x) 1 + 104 105 #define __NUM_PLATFORMS (INTEL_DISPLAY_PLATFORMS(__COUNT) 0) 106 107 struct intel_display_platforms { 108 union { 109 struct { 110 INTEL_DISPLAY_PLATFORMS(__MEMBER); 111 }; 112 DECLARE_BITMAP(bitmap, __NUM_PLATFORMS); 113 }; 114 }; 115 116 #undef __MEMBER 117 #undef __COUNT 118 #undef __NUM_PLATFORMS 119 120 #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \ 121 /* Keep in alphabetical order */ \ 122 func(cursor_needs_physical); \ 123 func(has_cdclk_crawl); \ 124 func(has_cdclk_squash); \ 125 func(has_ddi); \ 126 func(has_dp_mst); \ 127 func(has_dsb); \ 128 func(has_fpga_dbg); \ 129 func(has_gmch); \ 130 func(has_hotplug); \ 131 func(has_hti); \ 132 func(has_ipc); \ 133 func(has_overlay); \ 134 func(has_psr); \ 135 func(has_psr_hw_tracking); \ 136 func(overlay_needs_physical); \ 137 func(supports_tv); 138 139 #define HAS_4TILE(i915) (IS_DG2(i915) || DISPLAY_VER(i915) >= 14) 140 #define HAS_ASYNC_FLIPS(i915) (DISPLAY_VER(i915) >= 5) 141 #define HAS_BIGJOINER(i915) (DISPLAY_VER(i915) >= 11 && HAS_DSC(i915)) 142 #define HAS_CDCLK_CRAWL(i915) (DISPLAY_INFO(i915)->has_cdclk_crawl) 143 #define HAS_CDCLK_SQUASH(i915) (DISPLAY_INFO(i915)->has_cdclk_squash) 144 #define HAS_CUR_FBC(i915) (!HAS_GMCH(i915) && IS_DISPLAY_VER(i915, 7, 13)) 145 #define HAS_D12_PLANE_MINIMIZATION(i915) (IS_ROCKETLAKE(i915) || IS_ALDERLAKE_S(i915)) 146 #define HAS_DBUF_OVERLAP_DETECTION(__i915) (DISPLAY_RUNTIME_INFO(__i915)->has_dbuf_overlap_detection) 147 #define HAS_DDI(i915) (DISPLAY_INFO(i915)->has_ddi) 148 #define HAS_DISPLAY(i915) (DISPLAY_RUNTIME_INFO(i915)->pipe_mask != 0) 149 #define HAS_DMC(i915) (DISPLAY_RUNTIME_INFO(i915)->has_dmc) 150 #define HAS_DOUBLE_BUFFERED_M_N(i915) (DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915)) 151 #define HAS_DP_MST(i915) (DISPLAY_INFO(i915)->has_dp_mst) 152 #define HAS_DP20(i915) (IS_DG2(i915) || DISPLAY_VER(i915) >= 14) 153 #define HAS_DPT(i915) (DISPLAY_VER(i915) >= 13) 154 #define HAS_DSB(i915) (DISPLAY_INFO(i915)->has_dsb) 155 #define HAS_DSC(__i915) (DISPLAY_RUNTIME_INFO(__i915)->has_dsc) 156 #define HAS_DSC_MST(__i915) (DISPLAY_VER(__i915) >= 12 && HAS_DSC(__i915)) 157 #define HAS_FBC(i915) (DISPLAY_RUNTIME_INFO(i915)->fbc_mask != 0) 158 #define HAS_FPGA_DBG_UNCLAIMED(i915) (DISPLAY_INFO(i915)->has_fpga_dbg) 159 #define HAS_FW_BLC(i915) (DISPLAY_VER(i915) >= 3) 160 #define HAS_GMBUS_IRQ(i915) (DISPLAY_VER(i915) >= 4) 161 #define HAS_GMBUS_BURST_READ(i915) (DISPLAY_VER(i915) >= 10 || IS_KABYLAKE(i915)) 162 #define HAS_GMCH(i915) (DISPLAY_INFO(i915)->has_gmch) 163 #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915)) 164 #define HAS_IPC(i915) (DISPLAY_INFO(i915)->has_ipc) 165 #define HAS_IPS(i915) (IS_HASWELL_ULT(i915) || IS_BROADWELL(i915)) 166 #define HAS_LRR(i915) (DISPLAY_VER(i915) >= 12) 167 #define HAS_LSPCON(i915) (IS_DISPLAY_VER(i915, 9, 10)) 168 #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14) 169 #define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12) 170 #define HAS_OVERLAY(i915) (DISPLAY_INFO(i915)->has_overlay) 171 #define HAS_PSR(i915) (DISPLAY_INFO(i915)->has_psr) 172 #define HAS_PSR_HW_TRACKING(i915) (DISPLAY_INFO(i915)->has_psr_hw_tracking) 173 #define HAS_PSR2_SEL_FETCH(i915) (DISPLAY_VER(i915) >= 12) 174 #define HAS_SAGV(i915) (DISPLAY_VER(i915) >= 9 && !IS_BROXTON(i915) && !IS_GEMINILAKE(i915)) 175 #define HAS_TRANSCODER(i915, trans) ((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & \ 176 BIT(trans)) != 0) 177 #define HAS_UNCOMPRESSED_JOINER(i915) (DISPLAY_VER(i915) >= 13) 178 #define HAS_ULTRAJOINER(i915) ((DISPLAY_VER(i915) >= 20 || \ 179 (IS_DGFX(i915) && DISPLAY_VER(i915) == 14)) && \ 180 HAS_DSC(i915)) 181 #define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11) 182 #define HAS_AS_SDP(i915) (DISPLAY_VER(i915) >= 13) 183 #define HAS_CMRR(i915) (DISPLAY_VER(i915) >= 20) 184 #define INTEL_NUM_PIPES(i915) (hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask)) 185 #define I915_HAS_HOTPLUG(i915) (DISPLAY_INFO(i915)->has_hotplug) 186 #define OVERLAY_NEEDS_PHYSICAL(i915) (DISPLAY_INFO(i915)->overlay_needs_physical) 187 #define SUPPORTS_TV(i915) (DISPLAY_INFO(i915)->supports_tv) 188 189 /* Check that device has a display IP version within the specific range. */ 190 #define IS_DISPLAY_VERx100(__i915, from, until) ( \ 191 BUILD_BUG_ON_ZERO((from) < 200) + \ 192 (DISPLAY_VERx100(__i915) >= (from) && \ 193 DISPLAY_VERx100(__i915) <= (until))) 194 195 /* 196 * Check if a device has a specific IP version as well as a stepping within the 197 * specified range [from, until). The lower bound is inclusive, the upper 198 * bound is exclusive. The most common use-case of this macro is for checking 199 * bounds for workarounds, which usually have a stepping ("from") at which the 200 * hardware issue is first present and another stepping ("until") at which a 201 * hardware fix is present and the software workaround is no longer necessary. 202 * E.g., 203 * 204 * IS_DISPLAY_VERx100_STEP(i915, 1400, STEP_A0, STEP_B2) 205 * IS_DISPLAY_VERx100_STEP(i915, 1400, STEP_C0, STEP_FOREVER) 206 * 207 * "STEP_FOREVER" can be passed as "until" for workarounds that have no upper 208 * stepping bound for the specified IP version. 209 */ 210 #define IS_DISPLAY_VERx100_STEP(__i915, ipver, from, until) \ 211 (IS_DISPLAY_VERx100((__i915), (ipver), (ipver)) && \ 212 IS_DISPLAY_STEP((__i915), (from), (until))) 213 214 #define DISPLAY_INFO(i915) (__to_intel_display(i915)->info.__device_info) 215 #define DISPLAY_RUNTIME_INFO(i915) (&__to_intel_display(i915)->info.__runtime_info) 216 217 #define DISPLAY_VER(i915) (DISPLAY_RUNTIME_INFO(i915)->ip.ver) 218 #define DISPLAY_VERx100(i915) (DISPLAY_RUNTIME_INFO(i915)->ip.ver * 100 + \ 219 DISPLAY_RUNTIME_INFO(i915)->ip.rel) 220 #define IS_DISPLAY_VER(i915, from, until) \ 221 (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until)) 222 223 #define INTEL_DISPLAY_STEP(__i915) (DISPLAY_RUNTIME_INFO(__i915)->step) 224 225 #define IS_DISPLAY_STEP(__i915, since, until) \ 226 (drm_WARN_ON(__to_intel_display(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \ 227 INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) < (until)) 228 229 struct intel_display_runtime_info { 230 struct intel_display_ip_ver { 231 u16 ver; 232 u16 rel; 233 u16 step; /* hardware */ 234 } ip; 235 int step; /* symbolic */ 236 237 u32 rawclk_freq; 238 239 u8 pipe_mask; 240 u8 cpu_transcoder_mask; 241 u16 port_mask; 242 243 u8 num_sprites[I915_MAX_PIPES]; 244 u8 num_scalers[I915_MAX_PIPES]; 245 246 u8 fbc_mask; 247 248 bool has_hdcp; 249 bool has_dmc; 250 bool has_dsc; 251 bool edp_typec_support; 252 bool has_dbuf_overlap_detection; 253 }; 254 255 struct intel_display_device_info { 256 /* Initial runtime info. */ 257 const struct intel_display_runtime_info __runtime_defaults; 258 259 u8 abox_mask; 260 261 struct { 262 u16 size; /* in blocks */ 263 u8 slice_mask; 264 } dbuf; 265 266 #define DEFINE_FLAG(name) u8 name:1 267 DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG); 268 #undef DEFINE_FLAG 269 270 /* Global register offset for the display engine */ 271 u32 mmio_offset; 272 273 /* Register offsets for the various display pipes and transcoders */ 274 u32 pipe_offsets[I915_MAX_TRANSCODERS]; 275 u32 trans_offsets[I915_MAX_TRANSCODERS]; 276 u32 cursor_offsets[I915_MAX_PIPES]; 277 278 struct { 279 u32 degamma_lut_size; 280 u32 gamma_lut_size; 281 u32 degamma_lut_tests; 282 u32 gamma_lut_tests; 283 } color; 284 }; 285 286 bool intel_display_device_enabled(struct drm_i915_private *i915); 287 void intel_display_device_probe(struct drm_i915_private *i915); 288 void intel_display_device_remove(struct drm_i915_private *i915); 289 void intel_display_device_info_runtime_init(struct drm_i915_private *i915); 290 291 void intel_display_device_info_print(const struct intel_display_device_info *info, 292 const struct intel_display_runtime_info *runtime, 293 struct drm_printer *p); 294 295 #endif 296