1 #ifndef __src_nvidia_arch_nvalloc_common_inc_rmgspseq_h__ 2 #define __src_nvidia_arch_nvalloc_common_inc_rmgspseq_h__ 3 4 /* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */ 5 6 /* 7 * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 8 * SPDX-License-Identifier: MIT 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a 11 * copy of this software and associated documentation files (the "Software"), 12 * to deal in the Software without restriction, including without limitation 13 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 14 * and/or sell copies of the Software, and to permit persons to whom the 15 * Software is furnished to do so, subject to the following conditions: 16 * 17 * The above copyright notice and this permission notice shall be included in 18 * all copies or substantial portions of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 25 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 26 * DEALINGS IN THE SOFTWARE. 27 */ 28 29 typedef enum GSP_SEQ_BUF_OPCODE 30 { 31 GSP_SEQ_BUF_OPCODE_REG_WRITE = 0, 32 GSP_SEQ_BUF_OPCODE_REG_MODIFY, 33 GSP_SEQ_BUF_OPCODE_REG_POLL, 34 GSP_SEQ_BUF_OPCODE_DELAY_US, 35 GSP_SEQ_BUF_OPCODE_REG_STORE, 36 GSP_SEQ_BUF_OPCODE_CORE_RESET, 37 GSP_SEQ_BUF_OPCODE_CORE_START, 38 GSP_SEQ_BUF_OPCODE_CORE_WAIT_FOR_HALT, 39 GSP_SEQ_BUF_OPCODE_CORE_RESUME, 40 } GSP_SEQ_BUF_OPCODE; 41 42 #define GSP_SEQUENCER_PAYLOAD_SIZE_DWORDS(opcode) \ 43 ((opcode == GSP_SEQ_BUF_OPCODE_REG_WRITE) ? (sizeof(GSP_SEQ_BUF_PAYLOAD_REG_WRITE) / sizeof(NvU32)) : \ 44 (opcode == GSP_SEQ_BUF_OPCODE_REG_MODIFY) ? (sizeof(GSP_SEQ_BUF_PAYLOAD_REG_MODIFY) / sizeof(NvU32)) : \ 45 (opcode == GSP_SEQ_BUF_OPCODE_REG_POLL) ? (sizeof(GSP_SEQ_BUF_PAYLOAD_REG_POLL) / sizeof(NvU32)) : \ 46 (opcode == GSP_SEQ_BUF_OPCODE_DELAY_US) ? (sizeof(GSP_SEQ_BUF_PAYLOAD_DELAY_US) / sizeof(NvU32)) : \ 47 (opcode == GSP_SEQ_BUF_OPCODE_REG_STORE) ? (sizeof(GSP_SEQ_BUF_PAYLOAD_REG_STORE) / sizeof(NvU32)) : \ 48 /* GSP_SEQ_BUF_OPCODE_CORE_RESET */ \ 49 /* GSP_SEQ_BUF_OPCODE_CORE_START */ \ 50 /* GSP_SEQ_BUF_OPCODE_CORE_WAIT_FOR_HALT */ \ 51 /* GSP_SEQ_BUF_OPCODE_CORE_RESUME */ \ 52 0) 53 54 typedef struct 55 { 56 NvU32 addr; 57 NvU32 val; 58 } GSP_SEQ_BUF_PAYLOAD_REG_WRITE; 59 60 typedef struct 61 { 62 NvU32 addr; 63 NvU32 mask; 64 NvU32 val; 65 } GSP_SEQ_BUF_PAYLOAD_REG_MODIFY; 66 67 typedef struct 68 { 69 NvU32 addr; 70 NvU32 mask; 71 NvU32 val; 72 NvU32 timeout; 73 NvU32 error; 74 } GSP_SEQ_BUF_PAYLOAD_REG_POLL; 75 76 typedef struct 77 { 78 NvU32 val; 79 } GSP_SEQ_BUF_PAYLOAD_DELAY_US; 80 81 typedef struct 82 { 83 NvU32 addr; 84 NvU32 index; 85 } GSP_SEQ_BUF_PAYLOAD_REG_STORE; 86 87 typedef struct GSP_SEQUENCER_BUFFER_CMD 88 { 89 GSP_SEQ_BUF_OPCODE opCode; 90 union 91 { 92 GSP_SEQ_BUF_PAYLOAD_REG_WRITE regWrite; 93 GSP_SEQ_BUF_PAYLOAD_REG_MODIFY regModify; 94 GSP_SEQ_BUF_PAYLOAD_REG_POLL regPoll; 95 GSP_SEQ_BUF_PAYLOAD_DELAY_US delayUs; 96 GSP_SEQ_BUF_PAYLOAD_REG_STORE regStore; 97 } payload; 98 } GSP_SEQUENCER_BUFFER_CMD; 99 100 #endif 101