1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 #ifndef _XE_REGS_H_ 6 #define _XE_REGS_H_ 7 8 #include "regs/xe_reg_defs.h" 9 10 #define TIMESTAMP_OVERRIDE XE_REG(0x44074) 11 #define TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK REG_GENMASK(15, 12) 12 #define TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK REG_GENMASK(9, 0) 13 14 #define GU_CNTL_PROTECTED XE_REG(0x10100C) 15 #define DRIVERINT_FLR_DIS REG_BIT(31) 16 17 #define GU_CNTL XE_REG(0x101010) 18 #define LMEM_INIT REG_BIT(7) 19 #define DRIVERFLR REG_BIT(31) 20 21 #define XEHP_CLOCK_GATE_DIS XE_REG(0x101014) 22 #define SGSI_SIDECLK_DIS REG_BIT(17) 23 24 #define GU_DEBUG XE_REG(0x101018) 25 #define DRIVERFLR_STATUS REG_BIT(31) 26 27 #define VIRTUAL_CTRL_REG XE_REG(0x10108c) 28 #define GUEST_GTT_UPDATE_EN REG_BIT(8) 29 30 #define XEHP_MTCFG_ADDR XE_REG(0x101800) 31 #define TILE_COUNT REG_GENMASK(15, 8) 32 33 #define GGC XE_REG(0x108040) 34 #define GMS_MASK REG_GENMASK(15, 8) 35 #define GGMS_MASK REG_GENMASK(7, 6) 36 37 #define DSMBASE XE_REG(0x1080C0) 38 #define BDSM_MASK REG_GENMASK64(63, 20) 39 40 #define GSMBASE XE_REG(0x108100) 41 42 #define STOLEN_RESERVED XE_REG(0x1082c0) 43 #define WOPCM_SIZE_MASK REG_GENMASK64(9, 7) 44 45 #define MTL_RP_STATE_CAP XE_REG(0x138000) 46 47 #define MTL_GT_RPE_FREQUENCY XE_REG(0x13800c) 48 49 #define MTL_MEDIAP_STATE_CAP XE_REG(0x138020) 50 #define MTL_RPN_CAP_MASK REG_GENMASK(24, 16) 51 #define MTL_RP0_CAP_MASK REG_GENMASK(8, 0) 52 53 #define MTL_MPE_FREQUENCY XE_REG(0x13802c) 54 #define MTL_RPE_MASK REG_GENMASK(8, 0) 55 56 #define VF_CAP_REG XE_REG(0x1901f8, XE_REG_OPTION_VF) 57 #define VF_CAP REG_BIT(0) 58 59 #define PVC_RP_STATE_CAP XE_REG(0x281014) 60 61 #endif 62