1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License, Version 1.0 only
6 * (the "License"). You may not use this file except in compliance
7 * with the License.
8 *
9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10 * or http://www.opensolaris.org/os/licensing.
11 * See the License for the specific language governing permissions
12 * and limitations under the License.
13 *
14 * When distributing Covered Code, include this CDDL HEADER in each
15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16 * If applicable, add the following below this CDDL HEADER, with the
17 * fields enclosed by brackets "[]" replaced with your own identifying
18 * information: Portions Copyright [yyyy] [name of copyright owner]
19 *
20 * CDDL HEADER END
21 */
22 /*
23 * Copyright 2000-2002 Sun Microsystems, Inc. All rights reserved.
24 * Use is subject to license terms.
25 */
26
27 #pragma ident "%Z%%M% %I% %E% SMI"
28
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/sunddi.h>
32 #include <sys/esunddi.h>
33 #include <sys/ddi.h>
34
35 #include <sys/platform_module.h>
36 #include <sys/errno.h>
37
38 void
startup_platform(void)39 startup_platform(void)
40 {
41 }
42
43 int
set_platform_tsb_spares()44 set_platform_tsb_spares()
45 {
46 return (0);
47 }
48
49 void
set_platform_defaults(void)50 set_platform_defaults(void)
51 {
52 }
53
54
55 /*
56 * Definitions for accessing the pci config space of the isa node
57 * of Southbridge.
58 */
59 #define GROVER_ISA_PATHNAME "/pci@1f,0/isa@7"
60 ddi_acc_handle_t grover_isa_handle; /* handle for isa pci space */
61
62 void
load_platform_drivers(void)63 load_platform_drivers(void)
64 {
65 dev_info_t *dip; /* dip of the isa driver */
66
67
68 if (i_ddi_attach_hw_nodes("power") != DDI_SUCCESS)
69 cmn_err(CE_WARN, "Failed to install \"power\" driver.");
70
71 /*
72 * It is OK to return error because 'us' driver is not available
73 * in all clusters (e.g. missing in Core cluster).
74 */
75 (void) i_ddi_attach_hw_nodes("us");
76
77 if (i_ddi_attach_hw_nodes("grbeep") != DDI_SUCCESS)
78 cmn_err(CE_WARN, "Failed to install \"beep\" driver.");
79
80 /*
81 * Install Isa driver. This is required for the southbridge IDE
82 * workaround - to reset the IDE channel during IDE bus reset.
83 * Panic the system in case ISA driver could not be loaded or
84 * any problem in accessing its pci config space. Since the register
85 * to reset the channel for IDE is in ISA config space!.
86 */
87
88 dip = e_ddi_hold_devi_by_path(GROVER_ISA_PATHNAME, 0);
89 if (dip == NULL) {
90 cmn_err(CE_PANIC, "Could not install the isa driver\n");
91 return;
92 }
93
94 if (pci_config_setup(dip, &grover_isa_handle) != DDI_SUCCESS) {
95 cmn_err(CE_PANIC, "Could not get the config space of isa\n");
96 return;
97 }
98 }
99
100 /*
101 * This routine provides a workaround for a bug in the SB chip which
102 * can cause data corruption. Will be invoked from the IDE HBA driver for
103 * Acer SouthBridge at the time of IDE bus reset.
104 */
105 /*ARGSUSED*/
106 int
plat_ide_chipreset(dev_info_t * dip,int chno)107 plat_ide_chipreset(dev_info_t *dip, int chno)
108 {
109 uint8_t val;
110 int ret = DDI_SUCCESS;
111
112 val = pci_config_get8(grover_isa_handle, 0x58);
113 /*
114 * The dip passed as the argument is not used for grover.
115 * This will be needed for platforms which have multiple on-board SB,
116 * The dip passed will be used to match the corresponding ISA node.
117 */
118 switch (chno) {
119 case 0:
120 /*
121 * First disable the primary channel then re-enable it.
122 * As per ALI no wait should be required in between have
123 * given 1ms delay in between to be on safer side.
124 * bit 2 of register 0x58 when 0 disable the channel 0.
125 * bit 2 of register 0x58 when 1 enables the channel 0.
126 */
127 pci_config_put8(grover_isa_handle, 0x58, val & 0xFB);
128 drv_usecwait(1000);
129 pci_config_put8(grover_isa_handle, 0x58, val);
130 break;
131 case 1:
132 /*
133 * bit 3 of register 0x58 when 0 disable the channel 1.
134 * bit 3 of register 0x58 when 1 enables the channel 1.
135 */
136 pci_config_put8(grover_isa_handle, 0x58, val & 0xF7);
137 drv_usecwait(1000);
138 pci_config_put8(grover_isa_handle, 0x58, val);
139 break;
140 default:
141 /*
142 * Unknown channel number passed. Return failure.
143 */
144 ret = DDI_FAILURE;
145 }
146
147 return (ret);
148 }
149
150
151
152 /*ARGSUSED*/
153 int
plat_cpu_poweron(struct cpu * cp)154 plat_cpu_poweron(struct cpu *cp)
155 {
156 return (ENOTSUP); /* not supported on this platform */
157 }
158
159 /*ARGSUSED*/
160 int
plat_cpu_poweroff(struct cpu * cp)161 plat_cpu_poweroff(struct cpu *cp)
162 {
163 return (ENOTSUP); /* not supported on this platform */
164 }
165
166 /*ARGSUSED*/
167 void
plat_freelist_process(int mnode)168 plat_freelist_process(int mnode)
169 {
170 }
171
172 char *platform_module_list[] = {
173 "grppm",
174 (char *)0
175 };
176
177 /*ARGSUSED*/
178 void
plat_tod_fault(enum tod_fault_type tod_bad)179 plat_tod_fault(enum tod_fault_type tod_bad)
180 {
181 }
182