1 /*-
2 * Copyright (c) 2015, 2019 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31 /*
32 * Synopsys® DesignWare® APB General Purpose Programming I/O
33 * (DW_apb_gpio) peripheral.
34 *
35 * Chapter 22, Cyclone V Device Handbook (CV-5V2 2014.07.22)
36 */
37
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/bus.h>
41 #include <sys/kernel.h>
42 #include <sys/module.h>
43 #include <sys/malloc.h>
44 #include <sys/rman.h>
45 #include <sys/timeet.h>
46 #include <sys/timetc.h>
47 #include <sys/watchdog.h>
48 #include <sys/mutex.h>
49 #include <sys/gpio.h>
50 #include <sys/reboot.h>
51
52 #include <dev/gpio/gpiobusvar.h>
53 #include <dev/ofw/openfirm.h>
54 #include <dev/ofw/ofw_bus.h>
55 #include <dev/ofw/ofw_bus_subr.h>
56
57 #include <machine/bus.h>
58 #include <machine/cpu.h>
59 #include <machine/intr.h>
60
61 #include "gpio_if.h"
62 #include "dwgpio_if.h"
63
64 #define READ4(_sc, _reg) DWGPIO_READ((_sc)->parent, _reg)
65 #define WRITE4(_sc, _reg, _val) DWGPIO_WRITE((_sc)->parent, _reg, _val)
66
67 #define GPIO_SWPORT_DR(n) (0x00 + 0xc * (n)) /* Port n Data Register */
68 #define GPIO_SWPORT_DDR(n) (0x04 + 0xc * (n)) /* Port n Data Direction */
69 #define GPIO_INTEN 0x30 /* Interrupt Enable Register */
70 #define GPIO_INTMASK 0x34 /* Interrupt Mask Register */
71 #define GPIO_INTTYPE_LEVEL 0x38 /* Interrupt Level Register */
72 #define GPIO_INT_POLARITY 0x3C /* Interrupt Polarity Register */
73 #define GPIO_INTSTATUS 0x40 /* Interrupt Status Register */
74 #define GPIO_RAW_INTSTATUS 0x44 /* Raw Interrupt Status Register */
75 #define GPIO_DEBOUNCE 0x48 /* Debounce Enable Register */
76 #define GPIO_PORTA_EOI 0x4C /* Clear Interrupt Register */
77 #define GPIO_EXT_PORT(n) (0x50 + 0x4 * (n)) /* External Port n */
78 #define GPIO_LS_SYNC 0x60 /* Synchronization Level Register */
79 #define GPIO_ID_CODE 0x64 /* ID Code Register */
80 #define GPIO_VER_ID_CODE 0x6C /* GPIO Version Register */
81 #define GPIO_CONFIG_REG2 0x70 /* Configuration Register 2 */
82 #define ENCODED_ID_PWIDTH_M 0x1f /* Width of GPIO Port N Mask */
83 #define ENCODED_ID_PWIDTH_S(n) (5 * n) /* Width of GPIO Port N Shift */
84 #define GPIO_CONFIG_REG1 0x74 /* Configuration Register 1 */
85
86 #define NR_GPIO_MAX 32 /* Maximum pins per port */
87
88 #define GPIO_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
89 #define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
90
91 #define DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)
92
93 /*
94 * GPIO interface
95 */
96 static device_t dwgpio_get_bus(device_t);
97 static int dwgpio_pin_max(device_t, int *);
98 static int dwgpio_pin_getcaps(device_t, uint32_t, uint32_t *);
99 static int dwgpio_pin_getname(device_t, uint32_t, char *);
100 static int dwgpio_pin_getflags(device_t, uint32_t, uint32_t *);
101 static int dwgpio_pin_setflags(device_t, uint32_t, uint32_t);
102 static int dwgpio_pin_set(device_t, uint32_t, unsigned int);
103 static int dwgpio_pin_get(device_t, uint32_t, unsigned int *);
104 static int dwgpio_pin_toggle(device_t, uint32_t pin);
105
106 struct dwgpio_softc {
107 device_t dev;
108 device_t busdev;
109 device_t parent;
110 struct mtx sc_mtx;
111 int gpio_npins;
112 struct gpio_pin gpio_pins[NR_GPIO_MAX];
113 phandle_t node;
114 int port;
115 };
116
117 static int
dwgpio_probe(device_t dev)118 dwgpio_probe(device_t dev)
119 {
120
121 if (!ofw_bus_status_okay(dev))
122 return (ENXIO);
123
124 if (!ofw_bus_is_compatible(dev, "snps,dw-apb-gpio-port"))
125 return (ENXIO);
126
127 device_set_desc(dev, "DesignWare General-Purpose I/O Interface");
128 return (BUS_PROBE_DEFAULT);
129 }
130
131 static int
dwgpio_attach(device_t dev)132 dwgpio_attach(device_t dev)
133 {
134 struct dwgpio_softc *sc;
135 int version;
136 int nr_pins;
137 int cfg2;
138 int i;
139
140 sc = device_get_softc(dev);
141 sc->parent = device_get_parent(dev);
142 sc->node = ofw_bus_get_node(dev);
143 sc->dev = dev;
144 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
145
146 if ((OF_getencprop(sc->node, "reg", &sc->port, sizeof(sc->port))) <= 0)
147 return (ENXIO);
148
149 printf("port %d\n", sc->port);
150
151 version = READ4(sc, GPIO_VER_ID_CODE);
152 if (boothowto & RB_VERBOSE)
153 device_printf(sc->dev, "Version = 0x%08x\n", version);
154
155 /* Grab number of pins from hardware. */
156 cfg2 = READ4(sc, GPIO_CONFIG_REG2);
157 nr_pins = (cfg2 >> ENCODED_ID_PWIDTH_S(sc->port)) & \
158 ENCODED_ID_PWIDTH_M;
159 sc->gpio_npins = nr_pins + 1;
160
161 for (i = 0; i < sc->gpio_npins; i++) {
162 sc->gpio_pins[i].gp_pin = i;
163 sc->gpio_pins[i].gp_caps = DEFAULT_CAPS;
164 sc->gpio_pins[i].gp_flags =
165 (READ4(sc, GPIO_SWPORT_DDR(sc->port)) & (1 << i)) ?
166 GPIO_PIN_OUTPUT: GPIO_PIN_INPUT;
167 snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME,
168 "dwgpio%d.%d", device_get_unit(dev), i);
169 }
170 sc->busdev = gpiobus_attach_bus(dev);
171 if (sc->busdev == NULL) {
172 mtx_destroy(&sc->sc_mtx);
173 return (ENXIO);
174 }
175
176 return (0);
177 }
178
179 static device_t
dwgpio_get_bus(device_t dev)180 dwgpio_get_bus(device_t dev)
181 {
182 struct dwgpio_softc *sc;
183
184 sc = device_get_softc(dev);
185
186 return (sc->busdev);
187 }
188
189 static int
dwgpio_pin_max(device_t dev,int * maxpin)190 dwgpio_pin_max(device_t dev, int *maxpin)
191 {
192 struct dwgpio_softc *sc;
193
194 sc = device_get_softc(dev);
195
196 *maxpin = sc->gpio_npins - 1;
197
198 return (0);
199 }
200
201 static int
dwgpio_pin_getname(device_t dev,uint32_t pin,char * name)202 dwgpio_pin_getname(device_t dev, uint32_t pin, char *name)
203 {
204 struct dwgpio_softc *sc;
205 int i;
206
207 sc = device_get_softc(dev);
208 for (i = 0; i < sc->gpio_npins; i++) {
209 if (sc->gpio_pins[i].gp_pin == pin)
210 break;
211 }
212
213 if (i >= sc->gpio_npins)
214 return (EINVAL);
215
216 GPIO_LOCK(sc);
217 memcpy(name, sc->gpio_pins[i].gp_name, GPIOMAXNAME);
218 GPIO_UNLOCK(sc);
219
220 return (0);
221 }
222
223 static int
dwgpio_pin_getcaps(device_t dev,uint32_t pin,uint32_t * caps)224 dwgpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
225 {
226 struct dwgpio_softc *sc;
227 int i;
228
229 sc = device_get_softc(dev);
230 for (i = 0; i < sc->gpio_npins; i++) {
231 if (sc->gpio_pins[i].gp_pin == pin)
232 break;
233 }
234
235 if (i >= sc->gpio_npins)
236 return (EINVAL);
237
238 GPIO_LOCK(sc);
239 *caps = sc->gpio_pins[i].gp_caps;
240 GPIO_UNLOCK(sc);
241
242 return (0);
243 }
244
245 static int
dwgpio_pin_getflags(device_t dev,uint32_t pin,uint32_t * flags)246 dwgpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
247 {
248 struct dwgpio_softc *sc;
249 int i;
250
251 sc = device_get_softc(dev);
252 for (i = 0; i < sc->gpio_npins; i++) {
253 if (sc->gpio_pins[i].gp_pin == pin)
254 break;
255 }
256
257 if (i >= sc->gpio_npins)
258 return (EINVAL);
259
260 GPIO_LOCK(sc);
261 *flags = sc->gpio_pins[i].gp_flags;
262 GPIO_UNLOCK(sc);
263
264 return (0);
265 }
266
267 static int
dwgpio_pin_get(device_t dev,uint32_t pin,unsigned int * val)268 dwgpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
269 {
270 struct dwgpio_softc *sc;
271 int i;
272
273 sc = device_get_softc(dev);
274 for (i = 0; i < sc->gpio_npins; i++) {
275 if (sc->gpio_pins[i].gp_pin == pin)
276 break;
277 }
278
279 if (i >= sc->gpio_npins)
280 return (EINVAL);
281
282 GPIO_LOCK(sc);
283 *val = (READ4(sc, GPIO_EXT_PORT(sc->port)) & (1 << i)) ? 1 : 0;
284 GPIO_UNLOCK(sc);
285
286 return (0);
287 }
288
289 static int
dwgpio_pin_toggle(device_t dev,uint32_t pin)290 dwgpio_pin_toggle(device_t dev, uint32_t pin)
291 {
292 struct dwgpio_softc *sc;
293 int reg;
294 int i;
295
296 sc = device_get_softc(dev);
297 for (i = 0; i < sc->gpio_npins; i++) {
298 if (sc->gpio_pins[i].gp_pin == pin)
299 break;
300 }
301
302 if (i >= sc->gpio_npins)
303 return (EINVAL);
304
305 GPIO_LOCK(sc);
306 reg = READ4(sc, GPIO_SWPORT_DR(sc->port));
307 if (reg & (1 << i))
308 reg &= ~(1 << i);
309 else
310 reg |= (1 << i);
311 WRITE4(sc, GPIO_SWPORT_DR(sc->port), reg);
312 GPIO_UNLOCK(sc);
313
314 return (0);
315 }
316
317
318 static void
dwgpio_pin_configure(struct dwgpio_softc * sc,struct gpio_pin * pin,unsigned int flags)319 dwgpio_pin_configure(struct dwgpio_softc *sc,
320 struct gpio_pin *pin, unsigned int flags)
321 {
322 int reg;
323
324 GPIO_LOCK(sc);
325
326 /*
327 * Manage input/output
328 */
329
330 reg = READ4(sc, GPIO_SWPORT_DDR(sc->port));
331 if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
332 pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT);
333 if (flags & GPIO_PIN_OUTPUT) {
334 pin->gp_flags |= GPIO_PIN_OUTPUT;
335 reg |= (1 << pin->gp_pin);
336 } else {
337 pin->gp_flags |= GPIO_PIN_INPUT;
338 reg &= ~(1 << pin->gp_pin);
339 }
340 }
341
342 WRITE4(sc, GPIO_SWPORT_DDR(sc->port), reg);
343 GPIO_UNLOCK(sc);
344 }
345
346
347 static int
dwgpio_pin_setflags(device_t dev,uint32_t pin,uint32_t flags)348 dwgpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
349 {
350 struct dwgpio_softc *sc;
351 int i;
352
353 sc = device_get_softc(dev);
354 for (i = 0; i < sc->gpio_npins; i++) {
355 if (sc->gpio_pins[i].gp_pin == pin)
356 break;
357 }
358
359 if (i >= sc->gpio_npins)
360 return (EINVAL);
361
362 dwgpio_pin_configure(sc, &sc->gpio_pins[i], flags);
363
364 return (0);
365 }
366
367 static int
dwgpio_pin_set(device_t dev,uint32_t pin,unsigned int value)368 dwgpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
369 {
370 struct dwgpio_softc *sc;
371 int reg;
372 int i;
373
374 sc = device_get_softc(dev);
375
376 for (i = 0; i < sc->gpio_npins; i++) {
377 if (sc->gpio_pins[i].gp_pin == pin)
378 break;
379 }
380
381 if (i >= sc->gpio_npins)
382 return (EINVAL);
383
384 GPIO_LOCK(sc);
385 reg = READ4(sc, GPIO_SWPORT_DR(sc->port));
386 if (value)
387 reg |= (1 << i);
388 else
389 reg &= ~(1 << i);
390 WRITE4(sc, GPIO_SWPORT_DR(sc->port), reg);
391 GPIO_UNLOCK(sc);
392
393 return (0);
394 }
395
396 static device_method_t dwgpio_methods[] = {
397 DEVMETHOD(device_probe, dwgpio_probe),
398 DEVMETHOD(device_attach, dwgpio_attach),
399
400 /* GPIO protocol */
401 DEVMETHOD(gpio_get_bus, dwgpio_get_bus),
402 DEVMETHOD(gpio_pin_max, dwgpio_pin_max),
403 DEVMETHOD(gpio_pin_getname, dwgpio_pin_getname),
404 DEVMETHOD(gpio_pin_getcaps, dwgpio_pin_getcaps),
405 DEVMETHOD(gpio_pin_getflags, dwgpio_pin_getflags),
406 DEVMETHOD(gpio_pin_get, dwgpio_pin_get),
407 DEVMETHOD(gpio_pin_toggle, dwgpio_pin_toggle),
408 DEVMETHOD(gpio_pin_setflags, dwgpio_pin_setflags),
409 DEVMETHOD(gpio_pin_set, dwgpio_pin_set),
410 { 0, 0 }
411 };
412
413 static driver_t dwgpio_driver = {
414 "gpio",
415 dwgpio_methods,
416 sizeof(struct dwgpio_softc),
417 };
418
419 DRIVER_MODULE(dwgpio, dwgpiobus, dwgpio_driver, 0, 0);
420