1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25 #include <linux/debugfs.h>
26 #include <linux/firmware.h>
27
28 #include "i915_drv.h"
29 #include "i915_reg.h"
30 #include "intel_de.h"
31 #include "intel_dmc.h"
32 #include "intel_dmc_regs.h"
33 #include "intel_step.h"
34
35 /**
36 * DOC: DMC Firmware Support
37 *
38 * From gen9 onwards we have newly added DMC (Display microcontroller) in display
39 * engine to save and restore the state of display engine when it enter into
40 * low-power state and comes back to normal.
41 */
42
43 #define INTEL_DMC_FIRMWARE_URL "https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git"
44
45 enum intel_dmc_id {
46 DMC_FW_MAIN = 0,
47 DMC_FW_PIPEA,
48 DMC_FW_PIPEB,
49 DMC_FW_PIPEC,
50 DMC_FW_PIPED,
51 DMC_FW_MAX
52 };
53
54 struct intel_dmc {
55 struct intel_display *display;
56 struct work_struct work;
57 const char *fw_path;
58 u32 max_fw_size; /* bytes */
59 u32 version;
60 struct dmc_fw_info {
61 u32 mmio_count;
62 i915_reg_t mmioaddr[20];
63 u32 mmiodata[20];
64 u32 dmc_offset;
65 u32 start_mmioaddr;
66 u32 dmc_fw_size; /*dwords */
67 u32 *payload;
68 bool present;
69 } dmc_info[DMC_FW_MAX];
70 };
71
72 /* Note: This may be NULL. */
display_to_dmc(struct intel_display * display)73 static struct intel_dmc *display_to_dmc(struct intel_display *display)
74 {
75 return display->dmc.dmc;
76 }
77
dmc_firmware_param(struct intel_display * display)78 static const char *dmc_firmware_param(struct intel_display *display)
79 {
80 const char *p = display->params.dmc_firmware_path;
81
82 return p && *p ? p : NULL;
83 }
84
dmc_firmware_param_disabled(struct intel_display * display)85 static bool dmc_firmware_param_disabled(struct intel_display *display)
86 {
87 const char *p = dmc_firmware_param(display);
88
89 /* Magic path to indicate disabled */
90 return p && !strcmp(p, "/dev/null");
91 }
92
93 #define DMC_VERSION(major, minor) ((major) << 16 | (minor))
94 #define DMC_VERSION_MAJOR(version) ((version) >> 16)
95 #define DMC_VERSION_MINOR(version) ((version) & 0xffff)
96
97 #define DMC_PATH(platform) \
98 "i915/" __stringify(platform) "_dmc.bin"
99
100 /*
101 * New DMC additions should not use this. This is used solely to remain
102 * compatible with systems that have not yet updated DMC blobs to use
103 * unversioned file names.
104 */
105 #define DMC_LEGACY_PATH(platform, major, minor) \
106 "i915/" \
107 __stringify(platform) "_dmc_ver" \
108 __stringify(major) "_" \
109 __stringify(minor) ".bin"
110
111 #define XE2LPD_DMC_MAX_FW_SIZE 0x8000
112 #define XELPDP_DMC_MAX_FW_SIZE 0x7000
113 #define DISPLAY_VER13_DMC_MAX_FW_SIZE 0x20000
114 #define DISPLAY_VER12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE
115
116 #define XE3LPD_DMC_PATH DMC_PATH(xe3lpd)
117 MODULE_FIRMWARE(XE3LPD_DMC_PATH);
118
119 #define XE2LPD_DMC_PATH DMC_PATH(xe2lpd)
120 MODULE_FIRMWARE(XE2LPD_DMC_PATH);
121
122 #define BMG_DMC_PATH DMC_PATH(bmg)
123 MODULE_FIRMWARE(BMG_DMC_PATH);
124
125 #define MTL_DMC_PATH DMC_PATH(mtl)
126 MODULE_FIRMWARE(MTL_DMC_PATH);
127
128 #define DG2_DMC_PATH DMC_LEGACY_PATH(dg2, 2, 08)
129 MODULE_FIRMWARE(DG2_DMC_PATH);
130
131 #define ADLP_DMC_PATH DMC_PATH(adlp)
132 #define ADLP_DMC_FALLBACK_PATH DMC_LEGACY_PATH(adlp, 2, 16)
133 MODULE_FIRMWARE(ADLP_DMC_PATH);
134 MODULE_FIRMWARE(ADLP_DMC_FALLBACK_PATH);
135
136 #define ADLS_DMC_PATH DMC_LEGACY_PATH(adls, 2, 01)
137 MODULE_FIRMWARE(ADLS_DMC_PATH);
138
139 #define DG1_DMC_PATH DMC_LEGACY_PATH(dg1, 2, 02)
140 MODULE_FIRMWARE(DG1_DMC_PATH);
141
142 #define RKL_DMC_PATH DMC_LEGACY_PATH(rkl, 2, 03)
143 MODULE_FIRMWARE(RKL_DMC_PATH);
144
145 #define TGL_DMC_PATH DMC_LEGACY_PATH(tgl, 2, 12)
146 MODULE_FIRMWARE(TGL_DMC_PATH);
147
148 #define ICL_DMC_PATH DMC_LEGACY_PATH(icl, 1, 09)
149 #define ICL_DMC_MAX_FW_SIZE 0x6000
150 MODULE_FIRMWARE(ICL_DMC_PATH);
151
152 #define GLK_DMC_PATH DMC_LEGACY_PATH(glk, 1, 04)
153 #define GLK_DMC_MAX_FW_SIZE 0x4000
154 MODULE_FIRMWARE(GLK_DMC_PATH);
155
156 #define KBL_DMC_PATH DMC_LEGACY_PATH(kbl, 1, 04)
157 #define KBL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE
158 MODULE_FIRMWARE(KBL_DMC_PATH);
159
160 #define SKL_DMC_PATH DMC_LEGACY_PATH(skl, 1, 27)
161 #define SKL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE
162 MODULE_FIRMWARE(SKL_DMC_PATH);
163
164 #define BXT_DMC_PATH DMC_LEGACY_PATH(bxt, 1, 07)
165 #define BXT_DMC_MAX_FW_SIZE 0x3000
166 MODULE_FIRMWARE(BXT_DMC_PATH);
167
dmc_firmware_default(struct intel_display * display,u32 * size)168 static const char *dmc_firmware_default(struct intel_display *display, u32 *size)
169 {
170 struct drm_i915_private *i915 = to_i915(display->drm);
171 const char *fw_path = NULL;
172 u32 max_fw_size = 0;
173
174 if (DISPLAY_VERx100(display) == 3000) {
175 fw_path = XE3LPD_DMC_PATH;
176 max_fw_size = XE2LPD_DMC_MAX_FW_SIZE;
177 } else if (DISPLAY_VERx100(display) == 2000) {
178 fw_path = XE2LPD_DMC_PATH;
179 max_fw_size = XE2LPD_DMC_MAX_FW_SIZE;
180 } else if (DISPLAY_VERx100(display) == 1401) {
181 fw_path = BMG_DMC_PATH;
182 max_fw_size = XELPDP_DMC_MAX_FW_SIZE;
183 } else if (DISPLAY_VERx100(display) == 1400) {
184 fw_path = MTL_DMC_PATH;
185 max_fw_size = XELPDP_DMC_MAX_FW_SIZE;
186 } else if (IS_DG2(i915)) {
187 fw_path = DG2_DMC_PATH;
188 max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE;
189 } else if (IS_ALDERLAKE_P(i915)) {
190 fw_path = ADLP_DMC_PATH;
191 max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE;
192 } else if (IS_ALDERLAKE_S(i915)) {
193 fw_path = ADLS_DMC_PATH;
194 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE;
195 } else if (IS_DG1(i915)) {
196 fw_path = DG1_DMC_PATH;
197 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE;
198 } else if (IS_ROCKETLAKE(i915)) {
199 fw_path = RKL_DMC_PATH;
200 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE;
201 } else if (IS_TIGERLAKE(i915)) {
202 fw_path = TGL_DMC_PATH;
203 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE;
204 } else if (DISPLAY_VER(display) == 11) {
205 fw_path = ICL_DMC_PATH;
206 max_fw_size = ICL_DMC_MAX_FW_SIZE;
207 } else if (IS_GEMINILAKE(i915)) {
208 fw_path = GLK_DMC_PATH;
209 max_fw_size = GLK_DMC_MAX_FW_SIZE;
210 } else if (IS_KABYLAKE(i915) ||
211 IS_COFFEELAKE(i915) ||
212 IS_COMETLAKE(i915)) {
213 fw_path = KBL_DMC_PATH;
214 max_fw_size = KBL_DMC_MAX_FW_SIZE;
215 } else if (IS_SKYLAKE(i915)) {
216 fw_path = SKL_DMC_PATH;
217 max_fw_size = SKL_DMC_MAX_FW_SIZE;
218 } else if (IS_BROXTON(i915)) {
219 fw_path = BXT_DMC_PATH;
220 max_fw_size = BXT_DMC_MAX_FW_SIZE;
221 }
222
223 *size = max_fw_size;
224
225 return fw_path;
226 }
227
228 #define DMC_DEFAULT_FW_OFFSET 0xFFFFFFFF
229 #define PACKAGE_MAX_FW_INFO_ENTRIES 20
230 #define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32
231 #define DMC_V1_MAX_MMIO_COUNT 8
232 #define DMC_V3_MAX_MMIO_COUNT 20
233 #define DMC_V1_MMIO_START_RANGE 0x80000
234
235 #define PIPE_TO_DMC_ID(pipe) (DMC_FW_PIPEA + ((pipe) - PIPE_A))
236
237 struct intel_css_header {
238 /* 0x09 for DMC */
239 u32 module_type;
240
241 /* Includes the DMC specific header in dwords */
242 u32 header_len;
243
244 /* always value would be 0x10000 */
245 u32 header_ver;
246
247 /* Not used */
248 u32 module_id;
249
250 /* Not used */
251 u32 module_vendor;
252
253 /* in YYYYMMDD format */
254 u32 date;
255
256 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
257 u32 size;
258
259 /* Not used */
260 u32 key_size;
261
262 /* Not used */
263 u32 modulus_size;
264
265 /* Not used */
266 u32 exponent_size;
267
268 /* Not used */
269 u32 reserved1[12];
270
271 /* Major Minor */
272 u32 version;
273
274 /* Not used */
275 u32 reserved2[8];
276
277 /* Not used */
278 u32 kernel_header_info;
279 } __packed;
280
281 struct intel_fw_info {
282 u8 reserved1;
283
284 /* reserved on package_header version 1, must be 0 on version 2 */
285 u8 dmc_id;
286
287 /* Stepping (A, B, C, ..., *). * is a wildcard */
288 char stepping;
289
290 /* Sub-stepping (0, 1, ..., *). * is a wildcard */
291 char substepping;
292
293 u32 offset;
294 u32 reserved2;
295 } __packed;
296
297 struct intel_package_header {
298 /* DMC container header length in dwords */
299 u8 header_len;
300
301 /* 0x01, 0x02 */
302 u8 header_ver;
303
304 u8 reserved[10];
305
306 /* Number of valid entries in the FWInfo array below */
307 u32 num_entries;
308 } __packed;
309
310 struct intel_dmc_header_base {
311 /* always value would be 0x40403E3E */
312 u32 signature;
313
314 /* DMC binary header length */
315 u8 header_len;
316
317 /* 0x01 */
318 u8 header_ver;
319
320 /* Reserved */
321 u16 dmcc_ver;
322
323 /* Major, Minor */
324 u32 project;
325
326 /* Firmware program size (excluding header) in dwords */
327 u32 fw_size;
328
329 /* Major Minor version */
330 u32 fw_version;
331 } __packed;
332
333 struct intel_dmc_header_v1 {
334 struct intel_dmc_header_base base;
335
336 /* Number of valid MMIO cycles present. */
337 u32 mmio_count;
338
339 /* MMIO address */
340 u32 mmioaddr[DMC_V1_MAX_MMIO_COUNT];
341
342 /* MMIO data */
343 u32 mmiodata[DMC_V1_MAX_MMIO_COUNT];
344
345 /* FW filename */
346 char dfile[32];
347
348 u32 reserved1[2];
349 } __packed;
350
351 struct intel_dmc_header_v3 {
352 struct intel_dmc_header_base base;
353
354 /* DMC RAM start MMIO address */
355 u32 start_mmioaddr;
356
357 u32 reserved[9];
358
359 /* FW filename */
360 char dfile[32];
361
362 /* Number of valid MMIO cycles present. */
363 u32 mmio_count;
364
365 /* MMIO address */
366 u32 mmioaddr[DMC_V3_MAX_MMIO_COUNT];
367
368 /* MMIO data */
369 u32 mmiodata[DMC_V3_MAX_MMIO_COUNT];
370 } __packed;
371
372 struct stepping_info {
373 char stepping;
374 char substepping;
375 };
376
377 #define for_each_dmc_id(__dmc_id) \
378 for ((__dmc_id) = DMC_FW_MAIN; (__dmc_id) < DMC_FW_MAX; (__dmc_id)++)
379
is_valid_dmc_id(enum intel_dmc_id dmc_id)380 static bool is_valid_dmc_id(enum intel_dmc_id dmc_id)
381 {
382 return dmc_id >= DMC_FW_MAIN && dmc_id < DMC_FW_MAX;
383 }
384
has_dmc_id_fw(struct intel_display * display,enum intel_dmc_id dmc_id)385 static bool has_dmc_id_fw(struct intel_display *display, enum intel_dmc_id dmc_id)
386 {
387 struct intel_dmc *dmc = display_to_dmc(display);
388
389 return dmc && dmc->dmc_info[dmc_id].payload;
390 }
391
intel_dmc_has_payload(struct intel_display * display)392 bool intel_dmc_has_payload(struct intel_display *display)
393 {
394 return has_dmc_id_fw(display, DMC_FW_MAIN);
395 }
396
397 static const struct stepping_info *
intel_get_stepping_info(struct intel_display * display,struct stepping_info * si)398 intel_get_stepping_info(struct intel_display *display,
399 struct stepping_info *si)
400 {
401 const char *step_name = intel_step_name(INTEL_DISPLAY_STEP(display));
402
403 si->stepping = step_name[0];
404 si->substepping = step_name[1];
405 return si;
406 }
407
gen9_set_dc_state_debugmask(struct intel_display * display)408 static void gen9_set_dc_state_debugmask(struct intel_display *display)
409 {
410 /* The below bit doesn't need to be cleared ever afterwards */
411 intel_de_rmw(display, DC_STATE_DEBUG, 0,
412 DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP);
413 intel_de_posting_read(display, DC_STATE_DEBUG);
414 }
415
disable_event_handler(struct intel_display * display,i915_reg_t ctl_reg,i915_reg_t htp_reg)416 static void disable_event_handler(struct intel_display *display,
417 i915_reg_t ctl_reg, i915_reg_t htp_reg)
418 {
419 intel_de_write(display, ctl_reg,
420 REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,
421 DMC_EVT_CTL_TYPE_EDGE_0_1) |
422 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK,
423 DMC_EVT_CTL_EVENT_ID_FALSE));
424 intel_de_write(display, htp_reg, 0);
425 }
426
disable_all_event_handlers(struct intel_display * display)427 static void disable_all_event_handlers(struct intel_display *display)
428 {
429 enum intel_dmc_id dmc_id;
430
431 /* TODO: disable the event handlers on pre-GEN12 platforms as well */
432 if (DISPLAY_VER(display) < 12)
433 return;
434
435 for_each_dmc_id(dmc_id) {
436 int handler;
437
438 if (!has_dmc_id_fw(display, dmc_id))
439 continue;
440
441 for (handler = 0; handler < DMC_EVENT_HANDLER_COUNT_GEN12; handler++)
442 disable_event_handler(display,
443 DMC_EVT_CTL(display, dmc_id, handler),
444 DMC_EVT_HTP(display, dmc_id, handler));
445 }
446 }
447
adlp_pipedmc_clock_gating_wa(struct intel_display * display,bool enable)448 static void adlp_pipedmc_clock_gating_wa(struct intel_display *display, bool enable)
449 {
450 enum pipe pipe;
451
452 /*
453 * Wa_16015201720:adl-p,dg2
454 * The WA requires clock gating to be disabled all the time
455 * for pipe A and B.
456 * For pipe C and D clock gating needs to be disabled only
457 * during initializing the firmware.
458 */
459 if (enable)
460 for (pipe = PIPE_A; pipe <= PIPE_D; pipe++)
461 intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe),
462 0, PIPEDMC_GATING_DIS);
463 else
464 for (pipe = PIPE_C; pipe <= PIPE_D; pipe++)
465 intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe),
466 PIPEDMC_GATING_DIS, 0);
467 }
468
mtl_pipedmc_clock_gating_wa(struct intel_display * display)469 static void mtl_pipedmc_clock_gating_wa(struct intel_display *display)
470 {
471 /*
472 * Wa_16015201720
473 * The WA requires clock gating to be disabled all the time
474 * for pipe A and B.
475 */
476 intel_de_rmw(display, GEN9_CLKGATE_DIS_0, 0,
477 MTL_PIPEDMC_GATING_DIS_A | MTL_PIPEDMC_GATING_DIS_B);
478 }
479
pipedmc_clock_gating_wa(struct intel_display * display,bool enable)480 static void pipedmc_clock_gating_wa(struct intel_display *display, bool enable)
481 {
482 if (DISPLAY_VER(display) >= 14 && enable)
483 mtl_pipedmc_clock_gating_wa(display);
484 else if (DISPLAY_VER(display) == 13)
485 adlp_pipedmc_clock_gating_wa(display, enable);
486 }
487
intel_dmc_enable_pipe(struct intel_display * display,enum pipe pipe)488 void intel_dmc_enable_pipe(struct intel_display *display, enum pipe pipe)
489 {
490 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe);
491
492 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id))
493 return;
494
495 if (DISPLAY_VER(display) >= 14)
496 intel_de_rmw(display, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe));
497 else
498 intel_de_rmw(display, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE);
499 }
500
intel_dmc_disable_pipe(struct intel_display * display,enum pipe pipe)501 void intel_dmc_disable_pipe(struct intel_display *display, enum pipe pipe)
502 {
503 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe);
504
505 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id))
506 return;
507
508 if (DISPLAY_VER(display) >= 14)
509 intel_de_rmw(display, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0);
510 else
511 intel_de_rmw(display, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0);
512 }
513
is_dmc_evt_ctl_reg(struct intel_display * display,enum intel_dmc_id dmc_id,i915_reg_t reg)514 static bool is_dmc_evt_ctl_reg(struct intel_display *display,
515 enum intel_dmc_id dmc_id, i915_reg_t reg)
516 {
517 u32 offset = i915_mmio_reg_offset(reg);
518 u32 start = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, 0));
519 u32 end = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12));
520
521 return offset >= start && offset < end;
522 }
523
is_dmc_evt_htp_reg(struct intel_display * display,enum intel_dmc_id dmc_id,i915_reg_t reg)524 static bool is_dmc_evt_htp_reg(struct intel_display *display,
525 enum intel_dmc_id dmc_id, i915_reg_t reg)
526 {
527 u32 offset = i915_mmio_reg_offset(reg);
528 u32 start = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, 0));
529 u32 end = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12));
530
531 return offset >= start && offset < end;
532 }
533
disable_dmc_evt(struct intel_display * display,enum intel_dmc_id dmc_id,i915_reg_t reg,u32 data)534 static bool disable_dmc_evt(struct intel_display *display,
535 enum intel_dmc_id dmc_id,
536 i915_reg_t reg, u32 data)
537 {
538 struct drm_i915_private *i915 = to_i915(display->drm);
539
540 if (!is_dmc_evt_ctl_reg(display, dmc_id, reg))
541 return false;
542
543 /* keep all pipe DMC events disabled by default */
544 if (dmc_id != DMC_FW_MAIN)
545 return true;
546
547 /* also disable the flip queue event on the main DMC on TGL */
548 if (IS_TIGERLAKE(i915) &&
549 REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == DMC_EVT_CTL_EVENT_ID_CLK_MSEC)
550 return true;
551
552 /* also disable the HRR event on the main DMC on TGL/ADLS */
553 if ((IS_TIGERLAKE(i915) || IS_ALDERLAKE_S(i915)) &&
554 REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == DMC_EVT_CTL_EVENT_ID_VBLANK_A)
555 return true;
556
557 return false;
558 }
559
dmc_mmiodata(struct intel_display * display,struct intel_dmc * dmc,enum intel_dmc_id dmc_id,int i)560 static u32 dmc_mmiodata(struct intel_display *display,
561 struct intel_dmc *dmc,
562 enum intel_dmc_id dmc_id, int i)
563 {
564 if (disable_dmc_evt(display, dmc_id,
565 dmc->dmc_info[dmc_id].mmioaddr[i],
566 dmc->dmc_info[dmc_id].mmiodata[i]))
567 return REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,
568 DMC_EVT_CTL_TYPE_EDGE_0_1) |
569 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK,
570 DMC_EVT_CTL_EVENT_ID_FALSE);
571 else
572 return dmc->dmc_info[dmc_id].mmiodata[i];
573 }
574
575 /**
576 * intel_dmc_load_program() - write the firmware from memory to register.
577 * @display: display instance
578 *
579 * DMC firmware is read from a .bin file and kept in internal memory one time.
580 * Everytime display comes back from low power state this function is called to
581 * copy the firmware from internal memory to registers.
582 */
intel_dmc_load_program(struct intel_display * display)583 void intel_dmc_load_program(struct intel_display *display)
584 {
585 struct drm_i915_private *i915 __maybe_unused = to_i915(display->drm);
586 struct i915_power_domains *power_domains = &display->power.domains;
587 struct intel_dmc *dmc = display_to_dmc(display);
588 enum intel_dmc_id dmc_id;
589 u32 i;
590
591 if (!intel_dmc_has_payload(display))
592 return;
593
594 pipedmc_clock_gating_wa(display, true);
595
596 disable_all_event_handlers(display);
597
598 assert_rpm_wakelock_held(&i915->runtime_pm);
599
600 preempt_disable();
601
602 for_each_dmc_id(dmc_id) {
603 for (i = 0; i < dmc->dmc_info[dmc_id].dmc_fw_size; i++) {
604 intel_de_write_fw(display,
605 DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, i),
606 dmc->dmc_info[dmc_id].payload[i]);
607 }
608 }
609
610 preempt_enable();
611
612 for_each_dmc_id(dmc_id) {
613 for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) {
614 intel_de_write(display, dmc->dmc_info[dmc_id].mmioaddr[i],
615 dmc_mmiodata(display, dmc, dmc_id, i));
616 }
617 }
618
619 power_domains->dc_state = 0;
620
621 gen9_set_dc_state_debugmask(display);
622
623 pipedmc_clock_gating_wa(display, false);
624 }
625
626 /**
627 * intel_dmc_disable_program() - disable the firmware
628 * @display: display instance
629 *
630 * Disable all event handlers in the firmware, making sure the firmware is
631 * inactive after the display is uninitialized.
632 */
intel_dmc_disable_program(struct intel_display * display)633 void intel_dmc_disable_program(struct intel_display *display)
634 {
635 if (!intel_dmc_has_payload(display))
636 return;
637
638 pipedmc_clock_gating_wa(display, true);
639 disable_all_event_handlers(display);
640 pipedmc_clock_gating_wa(display, false);
641 }
642
assert_dmc_loaded(struct intel_display * display)643 void assert_dmc_loaded(struct intel_display *display)
644 {
645 struct intel_dmc *dmc = display_to_dmc(display);
646
647 drm_WARN_ONCE(display->drm, !dmc, "DMC not initialized\n");
648 drm_WARN_ONCE(display->drm, dmc &&
649 !intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
650 "DMC program storage start is NULL\n");
651 drm_WARN_ONCE(display->drm, !intel_de_read(display, DMC_SSP_BASE),
652 "DMC SSP Base Not fine\n");
653 drm_WARN_ONCE(display->drm, !intel_de_read(display, DMC_HTP_SKL),
654 "DMC HTP Not fine\n");
655 }
656
fw_info_matches_stepping(const struct intel_fw_info * fw_info,const struct stepping_info * si)657 static bool fw_info_matches_stepping(const struct intel_fw_info *fw_info,
658 const struct stepping_info *si)
659 {
660 if ((fw_info->substepping == '*' && si->stepping == fw_info->stepping) ||
661 (si->stepping == fw_info->stepping && si->substepping == fw_info->substepping) ||
662 /*
663 * If we don't find a more specific one from above two checks, we
664 * then check for the generic one to be sure to work even with
665 * "broken firmware"
666 */
667 (si->stepping == '*' && si->substepping == fw_info->substepping) ||
668 (fw_info->stepping == '*' && fw_info->substepping == '*'))
669 return true;
670
671 return false;
672 }
673
674 /*
675 * Search fw_info table for dmc_offset to find firmware binary: num_entries is
676 * already sanitized.
677 */
dmc_set_fw_offset(struct intel_dmc * dmc,const struct intel_fw_info * fw_info,unsigned int num_entries,const struct stepping_info * si,u8 package_ver)678 static void dmc_set_fw_offset(struct intel_dmc *dmc,
679 const struct intel_fw_info *fw_info,
680 unsigned int num_entries,
681 const struct stepping_info *si,
682 u8 package_ver)
683 {
684 struct intel_display *display = dmc->display;
685 enum intel_dmc_id dmc_id;
686 unsigned int i;
687
688 for (i = 0; i < num_entries; i++) {
689 dmc_id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id;
690
691 if (!is_valid_dmc_id(dmc_id)) {
692 drm_dbg(display->drm, "Unsupported firmware id: %u\n", dmc_id);
693 continue;
694 }
695
696 /* More specific versions come first, so we don't even have to
697 * check for the stepping since we already found a previous FW
698 * for this id.
699 */
700 if (dmc->dmc_info[dmc_id].present)
701 continue;
702
703 if (fw_info_matches_stepping(&fw_info[i], si)) {
704 dmc->dmc_info[dmc_id].present = true;
705 dmc->dmc_info[dmc_id].dmc_offset = fw_info[i].offset;
706 }
707 }
708 }
709
dmc_mmio_addr_sanity_check(struct intel_dmc * dmc,const u32 * mmioaddr,u32 mmio_count,int header_ver,enum intel_dmc_id dmc_id)710 static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc,
711 const u32 *mmioaddr, u32 mmio_count,
712 int header_ver, enum intel_dmc_id dmc_id)
713 {
714 struct intel_display *display = dmc->display;
715 u32 start_range, end_range;
716 int i;
717
718 if (header_ver == 1) {
719 start_range = DMC_MMIO_START_RANGE;
720 end_range = DMC_MMIO_END_RANGE;
721 } else if (dmc_id == DMC_FW_MAIN) {
722 start_range = TGL_MAIN_MMIO_START;
723 end_range = TGL_MAIN_MMIO_END;
724 } else if (DISPLAY_VER(display) >= 13) {
725 start_range = ADLP_PIPE_MMIO_START;
726 end_range = ADLP_PIPE_MMIO_END;
727 } else if (DISPLAY_VER(display) >= 12) {
728 start_range = TGL_PIPE_MMIO_START(dmc_id);
729 end_range = TGL_PIPE_MMIO_END(dmc_id);
730 } else {
731 drm_warn(display->drm, "Unknown mmio range for sanity check");
732 return false;
733 }
734
735 for (i = 0; i < mmio_count; i++) {
736 if (mmioaddr[i] < start_range || mmioaddr[i] > end_range)
737 return false;
738 }
739
740 return true;
741 }
742
parse_dmc_fw_header(struct intel_dmc * dmc,const struct intel_dmc_header_base * dmc_header,size_t rem_size,enum intel_dmc_id dmc_id)743 static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
744 const struct intel_dmc_header_base *dmc_header,
745 size_t rem_size, enum intel_dmc_id dmc_id)
746 {
747 struct intel_display *display = dmc->display;
748 struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id];
749 unsigned int header_len_bytes, dmc_header_size, payload_size, i;
750 const u32 *mmioaddr, *mmiodata;
751 u32 mmio_count, mmio_count_max, start_mmioaddr;
752 u8 *payload;
753
754 BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
755 ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
756
757 /*
758 * Check if we can access common fields, we will checkc again below
759 * after we have read the version
760 */
761 if (rem_size < sizeof(struct intel_dmc_header_base))
762 goto error_truncated;
763
764 /* Cope with small differences between v1 and v3 */
765 if (dmc_header->header_ver == 3) {
766 const struct intel_dmc_header_v3 *v3 =
767 (const struct intel_dmc_header_v3 *)dmc_header;
768
769 if (rem_size < sizeof(struct intel_dmc_header_v3))
770 goto error_truncated;
771
772 mmioaddr = v3->mmioaddr;
773 mmiodata = v3->mmiodata;
774 mmio_count = v3->mmio_count;
775 mmio_count_max = DMC_V3_MAX_MMIO_COUNT;
776 /* header_len is in dwords */
777 header_len_bytes = dmc_header->header_len * 4;
778 start_mmioaddr = v3->start_mmioaddr;
779 dmc_header_size = sizeof(*v3);
780 } else if (dmc_header->header_ver == 1) {
781 const struct intel_dmc_header_v1 *v1 =
782 (const struct intel_dmc_header_v1 *)dmc_header;
783
784 if (rem_size < sizeof(struct intel_dmc_header_v1))
785 goto error_truncated;
786
787 mmioaddr = v1->mmioaddr;
788 mmiodata = v1->mmiodata;
789 mmio_count = v1->mmio_count;
790 mmio_count_max = DMC_V1_MAX_MMIO_COUNT;
791 header_len_bytes = dmc_header->header_len;
792 start_mmioaddr = DMC_V1_MMIO_START_RANGE;
793 dmc_header_size = sizeof(*v1);
794 } else {
795 drm_err(display->drm, "Unknown DMC fw header version: %u\n",
796 dmc_header->header_ver);
797 return 0;
798 }
799
800 if (header_len_bytes != dmc_header_size) {
801 drm_err(display->drm, "DMC firmware has wrong dmc header length "
802 "(%u bytes)\n", header_len_bytes);
803 return 0;
804 }
805
806 /* Cache the dmc header info. */
807 if (mmio_count > mmio_count_max) {
808 drm_err(display->drm, "DMC firmware has wrong mmio count %u\n", mmio_count);
809 return 0;
810 }
811
812 if (!dmc_mmio_addr_sanity_check(dmc, mmioaddr, mmio_count,
813 dmc_header->header_ver, dmc_id)) {
814 drm_err(display->drm, "DMC firmware has Wrong MMIO Addresses\n");
815 return 0;
816 }
817
818 drm_dbg_kms(display->drm, "DMC %d:\n", dmc_id);
819 for (i = 0; i < mmio_count; i++) {
820 dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]);
821 dmc_info->mmiodata[i] = mmiodata[i];
822
823 drm_dbg_kms(display->drm, " mmio[%d]: 0x%x = 0x%x%s%s\n",
824 i, mmioaddr[i], mmiodata[i],
825 is_dmc_evt_ctl_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_CTL)" :
826 is_dmc_evt_htp_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_HTP)" : "",
827 disable_dmc_evt(display, dmc_id, dmc_info->mmioaddr[i],
828 dmc_info->mmiodata[i]) ? " (disabling)" : "");
829 }
830 dmc_info->mmio_count = mmio_count;
831 dmc_info->start_mmioaddr = start_mmioaddr;
832
833 rem_size -= header_len_bytes;
834
835 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
836 payload_size = dmc_header->fw_size * 4;
837 if (rem_size < payload_size)
838 goto error_truncated;
839
840 if (payload_size > dmc->max_fw_size) {
841 drm_err(display->drm, "DMC FW too big (%u bytes)\n", payload_size);
842 return 0;
843 }
844 dmc_info->dmc_fw_size = dmc_header->fw_size;
845
846 dmc_info->payload = kmalloc(payload_size, GFP_KERNEL);
847 if (!dmc_info->payload)
848 return 0;
849
850 payload = (u8 *)(dmc_header) + header_len_bytes;
851 memcpy(dmc_info->payload, payload, payload_size);
852
853 return header_len_bytes + payload_size;
854
855 error_truncated:
856 drm_err(display->drm, "Truncated DMC firmware, refusing.\n");
857 return 0;
858 }
859
860 static u32
parse_dmc_fw_package(struct intel_dmc * dmc,const struct intel_package_header * package_header,const struct stepping_info * si,size_t rem_size)861 parse_dmc_fw_package(struct intel_dmc *dmc,
862 const struct intel_package_header *package_header,
863 const struct stepping_info *si,
864 size_t rem_size)
865 {
866 struct intel_display *display = dmc->display;
867 u32 package_size = sizeof(struct intel_package_header);
868 u32 num_entries, max_entries;
869 const struct intel_fw_info *fw_info;
870
871 if (rem_size < package_size)
872 goto error_truncated;
873
874 if (package_header->header_ver == 1) {
875 max_entries = PACKAGE_MAX_FW_INFO_ENTRIES;
876 } else if (package_header->header_ver == 2) {
877 max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES;
878 } else {
879 drm_err(display->drm, "DMC firmware has unknown header version %u\n",
880 package_header->header_ver);
881 return 0;
882 }
883
884 /*
885 * We should always have space for max_entries,
886 * even if not all are used
887 */
888 package_size += max_entries * sizeof(struct intel_fw_info);
889 if (rem_size < package_size)
890 goto error_truncated;
891
892 if (package_header->header_len * 4 != package_size) {
893 drm_err(display->drm, "DMC firmware has wrong package header length "
894 "(%u bytes)\n", package_size);
895 return 0;
896 }
897
898 num_entries = package_header->num_entries;
899 if (WARN_ON(package_header->num_entries > max_entries))
900 num_entries = max_entries;
901
902 fw_info = (const struct intel_fw_info *)
903 ((u8 *)package_header + sizeof(*package_header));
904 dmc_set_fw_offset(dmc, fw_info, num_entries, si,
905 package_header->header_ver);
906
907 /* dmc_offset is in dwords */
908 return package_size;
909
910 error_truncated:
911 drm_err(display->drm, "Truncated DMC firmware, refusing.\n");
912 return 0;
913 }
914
915 /* Return number of bytes parsed or 0 on error */
parse_dmc_fw_css(struct intel_dmc * dmc,struct intel_css_header * css_header,size_t rem_size)916 static u32 parse_dmc_fw_css(struct intel_dmc *dmc,
917 struct intel_css_header *css_header,
918 size_t rem_size)
919 {
920 struct intel_display *display = dmc->display;
921
922 if (rem_size < sizeof(struct intel_css_header)) {
923 drm_err(display->drm, "Truncated DMC firmware, refusing.\n");
924 return 0;
925 }
926
927 if (sizeof(struct intel_css_header) !=
928 (css_header->header_len * 4)) {
929 drm_err(display->drm, "DMC firmware has wrong CSS header length "
930 "(%u bytes)\n",
931 (css_header->header_len * 4));
932 return 0;
933 }
934
935 dmc->version = css_header->version;
936
937 return sizeof(struct intel_css_header);
938 }
939
parse_dmc_fw(struct intel_dmc * dmc,const struct firmware * fw)940 static int parse_dmc_fw(struct intel_dmc *dmc, const struct firmware *fw)
941 {
942 struct intel_display *display = dmc->display;
943 struct intel_css_header *css_header;
944 struct intel_package_header *package_header;
945 struct intel_dmc_header_base *dmc_header;
946 struct stepping_info display_info = { '*', '*'};
947 const struct stepping_info *si = intel_get_stepping_info(display, &display_info);
948 enum intel_dmc_id dmc_id;
949 u32 readcount = 0;
950 u32 r, offset;
951
952 if (!fw)
953 return -EINVAL;
954
955 /* Extract CSS Header information */
956 css_header = (struct intel_css_header *)fw->data;
957 r = parse_dmc_fw_css(dmc, css_header, fw->size);
958 if (!r)
959 return -EINVAL;
960
961 readcount += r;
962
963 /* Extract Package Header information */
964 package_header = (struct intel_package_header *)&fw->data[readcount];
965 r = parse_dmc_fw_package(dmc, package_header, si, fw->size - readcount);
966 if (!r)
967 return -EINVAL;
968
969 readcount += r;
970
971 for_each_dmc_id(dmc_id) {
972 if (!dmc->dmc_info[dmc_id].present)
973 continue;
974
975 offset = readcount + dmc->dmc_info[dmc_id].dmc_offset * 4;
976 if (offset > fw->size) {
977 drm_err(display->drm, "Reading beyond the fw_size\n");
978 continue;
979 }
980
981 dmc_header = (struct intel_dmc_header_base *)&fw->data[offset];
982 parse_dmc_fw_header(dmc, dmc_header, fw->size - offset, dmc_id);
983 }
984
985 if (!intel_dmc_has_payload(display)) {
986 drm_err(display->drm, "DMC firmware main program not found\n");
987 return -ENOENT;
988 }
989
990 return 0;
991 }
992
intel_dmc_runtime_pm_get(struct intel_display * display)993 static void intel_dmc_runtime_pm_get(struct intel_display *display)
994 {
995 struct drm_i915_private *i915 = to_i915(display->drm);
996
997 drm_WARN_ON(display->drm, display->dmc.wakeref);
998 display->dmc.wakeref = intel_display_power_get(i915, POWER_DOMAIN_INIT);
999 }
1000
intel_dmc_runtime_pm_put(struct intel_display * display)1001 static void intel_dmc_runtime_pm_put(struct intel_display *display)
1002 {
1003 struct drm_i915_private *i915 = to_i915(display->drm);
1004 intel_wakeref_t wakeref __maybe_unused =
1005 fetch_and_zero(&display->dmc.wakeref);
1006
1007 intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref);
1008 }
1009
dmc_fallback_path(struct intel_display * display)1010 static const char *dmc_fallback_path(struct intel_display *display)
1011 {
1012 struct drm_i915_private *i915 = to_i915(display->drm);
1013
1014 if (IS_ALDERLAKE_P(i915))
1015 return ADLP_DMC_FALLBACK_PATH;
1016
1017 return NULL;
1018 }
1019
dmc_load_work_fn(struct work_struct * work)1020 static void dmc_load_work_fn(struct work_struct *work)
1021 {
1022 struct intel_dmc *dmc = container_of(work, typeof(*dmc), work);
1023 struct intel_display *display = dmc->display;
1024 const struct firmware *fw = NULL;
1025 const char *fallback_path;
1026 int err;
1027
1028 err = request_firmware(&fw, dmc->fw_path, display->drm->dev);
1029
1030 if (err == -ENOENT && !dmc_firmware_param(display)) {
1031 fallback_path = dmc_fallback_path(display);
1032 if (fallback_path) {
1033 drm_dbg_kms(display->drm, "%s not found, falling back to %s\n",
1034 dmc->fw_path, fallback_path);
1035 err = request_firmware(&fw, fallback_path, display->drm->dev);
1036 if (err == 0)
1037 dmc->fw_path = fallback_path;
1038 }
1039 }
1040
1041 if (err) {
1042 drm_notice(display->drm,
1043 "Failed to load DMC firmware %s (%pe). Disabling runtime power management.\n",
1044 dmc->fw_path, ERR_PTR(err));
1045 drm_notice(display->drm, "DMC firmware homepage: %s",
1046 INTEL_DMC_FIRMWARE_URL);
1047 return;
1048 }
1049
1050 err = parse_dmc_fw(dmc, fw);
1051 if (err) {
1052 drm_notice(display->drm,
1053 "Failed to parse DMC firmware %s (%pe). Disabling runtime power management.\n",
1054 dmc->fw_path, ERR_PTR(err));
1055 goto out;
1056 }
1057
1058 intel_dmc_load_program(display);
1059 intel_dmc_runtime_pm_put(display);
1060
1061 drm_info(display->drm, "Finished loading DMC firmware %s (v%u.%u)\n",
1062 dmc->fw_path, DMC_VERSION_MAJOR(dmc->version),
1063 DMC_VERSION_MINOR(dmc->version));
1064
1065 out:
1066 release_firmware(fw);
1067 }
1068
1069 /**
1070 * intel_dmc_init() - initialize the firmware loading.
1071 * @display: display instance
1072 *
1073 * This function is called at the time of loading the display driver to read
1074 * firmware from a .bin file and copied into a internal memory.
1075 */
intel_dmc_init(struct intel_display * display)1076 void intel_dmc_init(struct intel_display *display)
1077 {
1078 struct drm_i915_private *i915 = to_i915(display->drm);
1079 struct intel_dmc *dmc;
1080
1081 if (!HAS_DMC(display))
1082 return;
1083
1084 /*
1085 * Obtain a runtime pm reference, until DMC is loaded, to avoid entering
1086 * runtime-suspend.
1087 *
1088 * On error, we return with the rpm wakeref held to prevent runtime
1089 * suspend as runtime suspend *requires* a working DMC for whatever
1090 * reason.
1091 */
1092 intel_dmc_runtime_pm_get(display);
1093
1094 dmc = kzalloc(sizeof(*dmc), GFP_KERNEL);
1095 if (!dmc)
1096 return;
1097
1098 dmc->display = display;
1099
1100 INIT_WORK(&dmc->work, dmc_load_work_fn);
1101
1102 dmc->fw_path = dmc_firmware_default(display, &dmc->max_fw_size);
1103
1104 if (dmc_firmware_param_disabled(display)) {
1105 drm_info(display->drm, "Disabling DMC firmware and runtime PM\n");
1106 goto out;
1107 }
1108
1109 if (dmc_firmware_param(display))
1110 dmc->fw_path = dmc_firmware_param(display);
1111
1112 if (!dmc->fw_path) {
1113 drm_dbg_kms(display->drm,
1114 "No known DMC firmware for platform, disabling runtime PM\n");
1115 goto out;
1116 }
1117
1118 display->dmc.dmc = dmc;
1119
1120 drm_dbg_kms(display->drm, "Loading %s\n", dmc->fw_path);
1121 queue_work(i915->unordered_wq, &dmc->work);
1122
1123 return;
1124
1125 out:
1126 kfree(dmc);
1127 }
1128
1129 /**
1130 * intel_dmc_suspend() - prepare DMC firmware before system suspend
1131 * @display: display instance
1132 *
1133 * Prepare the DMC firmware before entering system suspend. This includes
1134 * flushing pending work items and releasing any resources acquired during
1135 * init.
1136 */
intel_dmc_suspend(struct intel_display * display)1137 void intel_dmc_suspend(struct intel_display *display)
1138 {
1139 struct intel_dmc *dmc = display_to_dmc(display);
1140
1141 if (!HAS_DMC(display))
1142 return;
1143
1144 if (dmc)
1145 flush_work(&dmc->work);
1146
1147 /* Drop the reference held in case DMC isn't loaded. */
1148 if (!intel_dmc_has_payload(display))
1149 intel_dmc_runtime_pm_put(display);
1150 }
1151
1152 /**
1153 * intel_dmc_resume() - init DMC firmware during system resume
1154 * @display: display instance
1155 *
1156 * Reinitialize the DMC firmware during system resume, reacquiring any
1157 * resources released in intel_dmc_suspend().
1158 */
intel_dmc_resume(struct intel_display * display)1159 void intel_dmc_resume(struct intel_display *display)
1160 {
1161 if (!HAS_DMC(display))
1162 return;
1163
1164 /*
1165 * Reacquire the reference to keep RPM disabled in case DMC isn't
1166 * loaded.
1167 */
1168 if (!intel_dmc_has_payload(display))
1169 intel_dmc_runtime_pm_get(display);
1170 }
1171
1172 /**
1173 * intel_dmc_fini() - unload the DMC firmware.
1174 * @display: display instance
1175 *
1176 * Firmmware unloading includes freeing the internal memory and reset the
1177 * firmware loading status.
1178 */
intel_dmc_fini(struct intel_display * display)1179 void intel_dmc_fini(struct intel_display *display)
1180 {
1181 struct intel_dmc *dmc = display_to_dmc(display);
1182 enum intel_dmc_id dmc_id;
1183
1184 if (!HAS_DMC(display))
1185 return;
1186
1187 intel_dmc_suspend(display);
1188 drm_WARN_ON(display->drm, display->dmc.wakeref);
1189
1190 if (dmc) {
1191 for_each_dmc_id(dmc_id)
1192 kfree(dmc->dmc_info[dmc_id].payload);
1193
1194 kfree(dmc);
1195 display->dmc.dmc = NULL;
1196 }
1197 }
1198
1199 struct intel_dmc_snapshot {
1200 bool initialized;
1201 bool loaded;
1202 u32 version;
1203 };
1204
intel_dmc_snapshot_capture(struct intel_display * display)1205 struct intel_dmc_snapshot *intel_dmc_snapshot_capture(struct intel_display *display)
1206 {
1207 struct intel_dmc *dmc = display_to_dmc(display);
1208 struct intel_dmc_snapshot *snapshot;
1209
1210 if (!HAS_DMC(display))
1211 return NULL;
1212
1213 snapshot = kzalloc(sizeof(*snapshot), GFP_ATOMIC);
1214 if (!snapshot)
1215 return NULL;
1216
1217 snapshot->initialized = dmc;
1218 snapshot->loaded = intel_dmc_has_payload(display);
1219 if (dmc)
1220 snapshot->version = dmc->version;
1221
1222 return snapshot;
1223 }
1224
intel_dmc_snapshot_print(const struct intel_dmc_snapshot * snapshot,struct drm_printer * p)1225 void intel_dmc_snapshot_print(const struct intel_dmc_snapshot *snapshot, struct drm_printer *p)
1226 {
1227 if (!snapshot)
1228 return;
1229
1230 drm_printf(p, "DMC initialized: %s\n", str_yes_no(snapshot->initialized));
1231 drm_printf(p, "DMC loaded: %s\n", str_yes_no(snapshot->loaded));
1232 if (snapshot->initialized)
1233 drm_printf(p, "DMC fw version: %d.%d\n",
1234 DMC_VERSION_MAJOR(snapshot->version),
1235 DMC_VERSION_MINOR(snapshot->version));
1236 }
1237
intel_dmc_debugfs_status_show(struct seq_file * m,void * unused)1238 static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
1239 {
1240 struct intel_display *display = m->private;
1241 struct drm_i915_private *i915 = to_i915(display->drm);
1242 struct intel_dmc *dmc = display_to_dmc(display);
1243 intel_wakeref_t wakeref;
1244 i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG;
1245
1246 if (!HAS_DMC(display))
1247 return -ENODEV;
1248
1249 wakeref = intel_runtime_pm_get(&i915->runtime_pm);
1250
1251 seq_printf(m, "DMC initialized: %s\n", str_yes_no(dmc));
1252 seq_printf(m, "fw loaded: %s\n",
1253 str_yes_no(intel_dmc_has_payload(display)));
1254 seq_printf(m, "path: %s\n", dmc ? dmc->fw_path : "N/A");
1255 seq_printf(m, "Pipe A fw needed: %s\n",
1256 str_yes_no(DISPLAY_VER(display) >= 12));
1257 seq_printf(m, "Pipe A fw loaded: %s\n",
1258 str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEA)));
1259 seq_printf(m, "Pipe B fw needed: %s\n",
1260 str_yes_no(IS_ALDERLAKE_P(i915) ||
1261 DISPLAY_VER(display) >= 14));
1262 seq_printf(m, "Pipe B fw loaded: %s\n",
1263 str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEB)));
1264
1265 if (!intel_dmc_has_payload(display))
1266 goto out;
1267
1268 seq_printf(m, "version: %d.%d\n", DMC_VERSION_MAJOR(dmc->version),
1269 DMC_VERSION_MINOR(dmc->version));
1270
1271 if (DISPLAY_VER(display) >= 12) {
1272 i915_reg_t dc3co_reg;
1273
1274 if (IS_DGFX(i915) || DISPLAY_VER(display) >= 14) {
1275 dc3co_reg = DG1_DMC_DEBUG3;
1276 dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
1277 } else {
1278 dc3co_reg = TGL_DMC_DEBUG3;
1279 dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
1280 dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
1281 }
1282
1283 seq_printf(m, "DC3CO count: %d\n",
1284 intel_de_read(display, dc3co_reg));
1285 } else {
1286 dc5_reg = IS_BROXTON(i915) ? BXT_DMC_DC3_DC5_COUNT :
1287 SKL_DMC_DC3_DC5_COUNT;
1288 if (!IS_GEMINILAKE(i915) && !IS_BROXTON(i915))
1289 dc6_reg = SKL_DMC_DC5_DC6_COUNT;
1290 }
1291
1292 seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg));
1293 if (i915_mmio_reg_valid(dc6_reg))
1294 seq_printf(m, "DC5 -> DC6 count: %d\n",
1295 intel_de_read(display, dc6_reg));
1296
1297 seq_printf(m, "program base: 0x%08x\n",
1298 intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
1299
1300 out:
1301 seq_printf(m, "ssp base: 0x%08x\n",
1302 intel_de_read(display, DMC_SSP_BASE));
1303 seq_printf(m, "htp: 0x%08x\n", intel_de_read(display, DMC_HTP_SKL));
1304
1305 intel_runtime_pm_put(&i915->runtime_pm, wakeref);
1306
1307 return 0;
1308 }
1309
1310 DEFINE_SHOW_ATTRIBUTE(intel_dmc_debugfs_status);
1311
intel_dmc_debugfs_register(struct intel_display * display)1312 void intel_dmc_debugfs_register(struct intel_display *display)
1313 {
1314 struct drm_minor *minor = display->drm->primary;
1315
1316 debugfs_create_file("i915_dmc_info", 0444, minor->debugfs_root,
1317 display, &intel_dmc_debugfs_status_fops);
1318 }
1319