1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 /* Copyright (c) 2017 - 2021 Intel Corporation */ 3 #ifndef ICRDMA_HW_H 4 #define ICRDMA_HW_H 5 6 #include "irdma.h" 7 8 #define VFPE_CQPTAIL1 0x0000a000 9 #define VFPE_CQPDB1 0x0000bc00 10 #define VFPE_CCQPSTATUS1 0x0000b800 11 #define VFPE_CCQPHIGH1 0x00009800 12 #define VFPE_CCQPLOW1 0x0000ac00 13 #define VFPE_CQARM1 0x0000b400 14 #define VFPE_CQARM1 0x0000b400 15 #define VFPE_CQACK1 0x0000b000 16 #define VFPE_AEQALLOC1 0x0000a400 17 #define VFPE_CQPERRCODES1 0x00009c00 18 #define VFPE_WQEALLOC1 0x0000c000 19 #define VFINT_DYN_CTLN(_i) (0x00003800 + ((_i) * 4)) /* _i=0...63 */ 20 21 #define PFPE_CQPTAIL 0x00500880 22 #define PFPE_CQPDB 0x00500800 23 #define PFPE_CCQPSTATUS 0x0050a000 24 #define PFPE_CCQPHIGH 0x0050a100 25 #define PFPE_CCQPLOW 0x0050a080 26 #define PFPE_CQARM 0x00502c00 27 #define PFPE_CQACK 0x00502c80 28 #define PFPE_AEQALLOC 0x00502d00 29 #define GLINT_DYN_CTL(_INT) (0x00160000 + ((_INT) * 4)) /* _i=0...2047 */ 30 #define GLPCI_LBARCTRL 0x0009de74 31 #define GLPE_CPUSTATUS0 0x0050ba5c 32 #define GLPE_CPUSTATUS1 0x0050ba60 33 #define GLPE_CPUSTATUS2 0x0050ba64 34 #define PFINT_AEQCTL 0x0016cb00 35 #define PFPE_CQPERRCODES 0x0050a200 36 #define PFPE_WQEALLOC 0x00504400 37 #define GLINT_CEQCTL(_INT) (0x0015c000 + ((_INT) * 4)) /* _i=0...2047 */ 38 #define VSIQF_PE_CTL1(_VSI) (0x00414000 + ((_VSI) * 4)) /* _i=0...767 */ 39 #define PFHMC_PDINV 0x00520300 40 #define GLHMC_VFPDINV(_i) (0x00528300 + ((_i) * 4)) /* _i=0...31 */ 41 #define GLPE_CRITERR 0x00534000 42 #define GLINT_RATE(_INT) (0x0015A000 + ((_INT) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */ 43 44 #define ICRDMA_DB_ADDR_OFFSET (8 * 1024 * 1024 - 64 * 1024) 45 46 #define ICRDMA_VF_DB_ADDR_OFFSET (64 * 1024) 47 48 /* shifts/masks for FLD_[LS/RS]_64 macros used in device table */ 49 #define ICRDMA_CCQPSTATUS_CCQP_DONE_S 0 50 #define ICRDMA_CCQPSTATUS_CCQP_DONE BIT_ULL(0) 51 #define ICRDMA_CCQPSTATUS_CCQP_ERR_S 31 52 #define ICRDMA_CCQPSTATUS_CCQP_ERR BIT_ULL(31) 53 #define ICRDMA_CQPSQ_STAG_PDID_S 46 54 #define ICRDMA_CQPSQ_STAG_PDID GENMASK_ULL(63, 46) 55 #define ICRDMA_CQPSQ_CQ_CEQID_S 22 56 #define ICRDMA_CQPSQ_CQ_CEQID GENMASK_ULL(31, 22) 57 #define ICRDMA_CQPSQ_CQ_CQID_S 0 58 #define ICRDMA_CQPSQ_CQ_CQID GENMASK_ULL(18, 0) 59 #define ICRDMA_COMMIT_FPM_CQCNT_S 0 60 #define ICRDMA_COMMIT_FPM_CQCNT GENMASK_ULL(19, 0) 61 62 enum icrdma_device_caps_const { 63 ICRDMA_MAX_STATS_COUNT = 128, 64 65 ICRDMA_MAX_IRD_SIZE = 127, 66 ICRDMA_MAX_ORD_SIZE = 255, 67 ICRDMA_MIN_WQ_SIZE = 8 /* WQEs */, 68 69 }; 70 71 void icrdma_init_hw(struct irdma_sc_dev *dev); 72 #endif /* ICRDMA_HW_H*/ 73