1 /*- 2 * Copyright (c) 2015 The FreeBSD Foundation 3 * 4 * This software was developed by Semihalf under 5 * the sponsorship of the FreeBSD Foundation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _GIC_V3_VAR_H_ 30 #define _GIC_V3_VAR_H_ 31 32 #include <arm/arm/gic_common.h> 33 34 #define GIC_V3_DEVSTR "ARM Generic Interrupt Controller v3.0" 35 36 DECLARE_CLASS(gic_v3_driver); 37 38 struct gic_v3_irqsrc; 39 40 struct redist_pcpu { 41 struct resource *res; /* mem resource for redist */ 42 vm_offset_t pend_base; 43 bus_size_t offset; 44 bool lpi_enabled; /* redist LPI configured? */ 45 }; 46 47 struct gic_redists { 48 /* 49 * Re-Distributor region description. 50 * We will have few of those depending 51 * on the #redistributor-regions property in FDT. 52 */ 53 struct resource ** regions; 54 /* Number of Re-Distributor regions */ 55 u_int nregions; 56 /* 57 * Whether to treat each region as a single Re-Distributor page or a 58 * series of contiguous pages (i.e. from each ACPI MADT GICC's GICR 59 * Base Address field) 60 */ 61 bool single; 62 /* Per-CPU Re-Distributor data */ 63 struct redist_pcpu *pcpu; 64 }; 65 66 #define GIC_V3_FLAGS_FORCE_NOSHAREABLE 0x0000001 67 68 struct gic_v3_softc { 69 device_t dev; 70 struct resource ** gic_res; 71 struct mtx gic_mtx; 72 /* Distributor */ 73 struct resource * gic_dist; 74 /* Re-Distributors */ 75 struct gic_redists gic_redists; 76 77 /* Message Based Interrupts */ 78 u_int gic_mbi_start; 79 u_int gic_mbi_end; 80 struct mtx gic_mbi_mtx; 81 82 uint32_t gic_pidr2; 83 u_int gic_bus; 84 85 u_int gic_nirqs; 86 u_int gic_idbits; 87 88 boolean_t gic_registered; 89 90 int gic_nchildren; 91 device_t *gic_children; 92 struct intr_pic *gic_pic; 93 struct gic_v3_irqsrc *gic_irqs; 94 95 int nranges; 96 struct arm_gic_range * ranges; 97 98 uint32_t gic_flags; 99 }; 100 101 struct gic_v3_devinfo { 102 int gic_domain; 103 int msi_xref; 104 int is_vgic; 105 }; 106 107 #define GIC_INTR_ISRC(sc, irq) (&sc->gic_irqs[irq].gi_isrc) 108 109 MALLOC_DECLARE(M_GIC_V3); 110 111 /* ivars */ 112 #define GICV3_IVAR_NIRQS 1000 113 /* 1001 was GICV3_IVAR_REDIST_VADDR */ 114 #define GICV3_IVAR_REDIST 1002 115 #define GICV3_IVAR_FLAGS 1003 116 117 __BUS_ACCESSOR(gicv3, nirqs, GICV3, NIRQS, u_int); 118 __BUS_ACCESSOR(gicv3, redist, GICV3, REDIST, void *); 119 __BUS_ACCESSOR(gicv3, flags, GICV3, FLAGS, uint32_t); 120 121 /* Device methods */ 122 int gic_v3_attach(device_t dev); 123 int gic_v3_detach(device_t dev); 124 int arm_gic_v3_intr(void *); 125 126 uint32_t gic_r_read_4(device_t, bus_size_t); 127 uint64_t gic_r_read_8(device_t, bus_size_t); 128 void gic_r_write_4(device_t, bus_size_t, uint32_t var); 129 void gic_r_write_8(device_t, bus_size_t, uint64_t var); 130 131 /* 132 * GIC Distributor accessors. 133 * Notice that only GIC sofc can be passed. 134 */ 135 #define gic_d_read(sc, len, reg) \ 136 ({ \ 137 bus_read_##len(sc->gic_dist, reg); \ 138 }) 139 140 #define gic_d_write(sc, len, reg, val) \ 141 ({ \ 142 bus_write_##len(sc->gic_dist, reg, val);\ 143 }) 144 145 /* GIC Re-Distributor accessors (per-CPU) */ 146 #define gic_r_read(sc, len, reg) \ 147 ({ \ 148 u_int cpu = PCPU_GET(cpuid); \ 149 \ 150 bus_read_##len( \ 151 (sc)->gic_redists.pcpu[cpu].res, \ 152 (sc)->gic_redists.pcpu[cpu].offset + (reg)); \ 153 }) 154 155 #define gic_r_write(sc, len, reg, val) \ 156 ({ \ 157 u_int cpu = PCPU_GET(cpuid); \ 158 \ 159 bus_write_##len( \ 160 (sc)->gic_redists.pcpu[cpu].res, \ 161 (sc)->gic_redists.pcpu[cpu].offset + (reg), \ 162 (val)); \ 163 }) 164 165 #endif /* _GIC_V3_VAR_H_ */ 166