1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2022 Scott Long 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * Thunderbolt3/USB4 config space register definitions 29 * 30 * $FreeBSD$ 31 */ 32 33 #ifndef _TBCFG_REG_H 34 #define _TBCFG_REG_H 35 36 /* Config space read request, 6.4.2.3 */ 37 struct tb_cfg_read { 38 tb_route_t route; 39 uint32_t addr_attrs; 40 #define TB_CFG_ADDR_SHIFT 0 41 #define TB_CFG_ADDR_MASK GENMASK(12,0) 42 #define TB_CFG_SIZE_SHIFT 13 43 #define TB_CFG_SIZE_MASK GENMASK(18,13) 44 #define TB_CFG_ADAPTER_SHIFT 19 45 #define TB_CFG_ADAPTER_MASK GENMASK(24,19) 46 #define TB_CFG_CS_PATH (0x00 << 25) 47 #define TB_CFG_CS_ADAPTER (0x01 << 25) 48 #define TB_CFG_CS_ROUTER (0x02 << 25) 49 #define TB_CFG_CS_COUNTERS (0x03 << 25) 50 #define TB_CFG_SEQ_SHIFT 27 51 #define TB_CFG_SEQ_MASK (28,27) 52 uint32_t crc; 53 }; 54 55 /* Config space read request, 6.4.2.4 */ 56 struct tb_cfg_read_resp { 57 tb_route_t route; 58 uint32_t addr_attrs; 59 uint32_t data[0]; /* Up to 60 dwords */ 60 /* uint32_t crc is at the end */ 61 } __packed; 62 63 /* Config space write request, 6.4.2.5 */ 64 struct tb_cfg_write { 65 tb_route_t route; 66 uint32_t addr_attrs; 67 uint32_t data[0]; /* Up to 60 dwords */ 68 /* uint32_t crc is at the end */ 69 } __packed; 70 71 /* Config space write response, 6.4.2.6 */ 72 struct tb_cfg_write_resp { 73 tb_route_t route; 74 uint32_t addr_attrs; 75 uint32_t crc; 76 } __packed; 77 78 /* Config space event, 6.4.2.7 */ 79 struct tb_cfg_notify { 80 tb_route_t route; 81 uint32_t event_adap; 82 #define TB_CFG_EVENT_MASK GENMASK(7,0) 83 #define GET_NOTIFY_EVENT(n) ((n)->event_adap & TB_CFG_EVENT_MASK) 84 #define TB_CFG_ERR_CONN 0x00 85 #define TB_CFG_ERR_LINK 0x01 86 #define TB_CFG_ERR_ADDR 0x02 87 #define TB_CFG_ERR_ADP 0x04 88 #define TB_CFG_ERR_ENUM 0x08 89 #define TB_CFG_ERR_NUA 0x09 90 #define TB_CFG_ERR_LEN 0x0b 91 #define TB_CFG_ERR_HEC 0x0c 92 #define TB_CFG_ERR_FC 0x0d 93 #define TB_CFG_ERR_PLUG 0x0e 94 #define TB_CFG_ERR_LOCK 0x0f 95 #define TB_CFG_HP_ACK 0x07 96 #define TB_CFG_DP_BW 0x20 97 #define TB_CFG_EVENT_ADAPTER_SHIFT 8 98 #define TB_CFG_EVENT_ADAPTER_MASK GENMASK(13,8) 99 #define GET_NOTIFY_ADAPTER(n) (((n)->event_adap & \ 100 TB_CFG_EVENT_ADAPTER_MASK) >> \ 101 TB_CFG_EVENT_ADAPTER_SHIFT) 102 #define TB_CFG_PG_NONE 0x00000000 103 #define TB_CFG_PG_PLUG 0x80000000 104 #define TB_CFG_PG_UNPLUG 0xc0000000 105 uint32_t crc; 106 } __packed; 107 108 /* Config space event acknowledgement, 6.4.2.8 */ 109 struct tb_cfg_notify_ack { 110 tb_route_t route; 111 uint32_t crc; 112 } __packed; 113 114 /* Config space hot plug event, 6.4.2.10 */ 115 struct tb_cfg_hotplug { 116 tb_route_t route; 117 uint32_t adapter_attrs; 118 #define TB_CFG_ADPT_MASK GENMASK(5,0) 119 #define TB_CFG_UPG_PLUG (0x0 << 31) 120 #define TB_CFG_UPG_UNPLUG (0x1 << 31) 121 uint32_t crc; 122 } __packed; 123 124 /* Config space inter-domain request, 6.4.2.11 */ 125 struct tb_cfg_xdomain { 126 tb_route_t route; 127 uint32_t data[0]; 128 /* uint32_t crc is at the end */ 129 } __packed; 130 131 /* Config space inter-domain response, 6.4.2.12 */ 132 struct tb_cfg_xdomain_resp { 133 tb_route_t route; 134 uint32_t data[0]; 135 /* uint32_t crc is at the end */ 136 } __packed; 137 138 /* Config space router basic registers 8.2.1.1 */ 139 struct tb_cfg_router { 140 uint16_t vendor_id; /* ROUTER_CS_0 */ 141 uint16_t product_id; 142 uint32_t router_cs_1; /* ROUTER_CS_1 */ 143 #define ROUTER_CS1_NEXT_CAP_MASK GENMASK(7,0) 144 #define GET_ROUTER_CS_NEXT_CAP(r) (r->router_cs_1 & \ 145 ROUTER_CS1_NEXT_CAP_MASK) 146 #define ROUTER_CS1_UPSTREAM_SHIFT 8 147 #define ROUTER_CS1_UPSTREAM_MASK GENMASK(13,8) 148 #define GET_ROUTER_CS_UPSTREAM_ADAP(r) ((r->router_cs_1 & \ 149 ROUTER_CS1_UPSTREAM_MASK) >> \ 150 ROUTER_CS1_UPSTREAM_SHIFT) 151 #define ROUTER_CS1_MAX_SHIFT 14 152 #define ROUTER_CS1_MAX_MASK GENMASK(19,14) 153 #define GET_ROUTER_CS_MAX_ADAP(r) ((r->router_cs_1 & \ 154 ROUTER_CS1_MAX_MASK) >> \ 155 ROUTER_CS1_MAX_SHIFT) 156 #define ROUTER_CS1_MAX_ADAPTERS 64 157 #define ROUTER_CS1_DEPTH_SHIFT 20 158 #define ROUTER_CS1_DEPTH_MASK GENMASK(22,20) 159 #define GET_ROUTER_CS_DEPTH(r) ((r->router_cs_1 & \ 160 ROUTER_CS1_DEPTH_MASK) >> \ 161 ROUTER_CS1_DEPTH_SHIFT) 162 #define ROUTER_CS1_REVISION_SHIFT 24 163 #define ROUTER_CS1_REVISION_MASK GENMASK(31,24) 164 #define GET_ROUTER_CS_REVISION ((r->router_cs_1 & \ 165 ROUTER_CS1_REVISION_MASK) >> \ 166 ROUTER_CS1_REVISION_SHIFT) 167 uint32_t topology_lo; /* ROUTER_CS_2 */ 168 uint32_t topology_hi; /* ROUTER_CS_3 */ 169 #define CFG_TOPOLOGY_VALID (1 << 31) 170 uint8_t notification_timeout; /* ROUTER_CS_4 */ 171 uint8_t cm_version; 172 #define CFG_CM_USB4 0x10 173 uint8_t rsrvd1; 174 uint8_t usb4_version; 175 #define CFG_USB4_V1_0 0x10 176 uint32_t flags_cs5; /* ROUTER_CS_5 */ 177 #define CFG_CS5_SLP (1 << 0) 178 #define CFG_CS5_WOP (1 << 1) 179 #define CFG_CS5_WOU (1 << 2) 180 #define CFG_CS5_DP (1 << 3) 181 #define CFG_CS5_C3S (1 << 23) 182 #define CFG_CS5_PTO (1 << 24) 183 #define CFG_CS5_UTO (1 << 25) 184 #define CFG_CS5_HCO (1 << 26) 185 #define CFG_CS5_CV (1 << 31) 186 uint32_t flags_cs6; /* ROUTER_CS_6 */ 187 #define CFG_CS6_SLPR (1 << 0) 188 #define CFG_CS6_TNS (1 << 1) 189 #define CFG_CS6_WAKE_PCIE (1 << 2) 190 #define CFG_CS6_WAKE_USB3 (1 << 3) 191 #define CFG_CS6_WAKE_DP (1 << 4) 192 #define CFG_CS6_HCI (1 << 18) 193 #define CFG_CS6_RR (1 << 24) 194 #define CFG_CS6_CR (1 << 25) 195 uint32_t uuid_hi; /* ROUTER_CS_7 */ 196 uint32_t uuid_lo; /* ROUTER_CS_8 */ 197 uint32_t data[16]; /* ROUTER_CS_9-24 */ 198 uint32_t metadata; /* ROUTER_CS_25 */ 199 uint32_t opcode_status; /* ROUTER_CS_26 */ 200 /* TBD: Opcodes and status */ 201 #define CFG_ONS (1 << 30) 202 #define CFG_OV (1 << 31) 203 } __packed; 204 205 #define TB_CFG_CAP_OFFSET_MAX 0xfff 206 207 /* Config space router capability header 8.2.1.3/8.2.1.4 */ 208 struct tb_cfg_cap_hdr { 209 uint8_t next_cap; 210 uint8_t cap_id; 211 } __packed; 212 213 /* Config space router TMU registers 8.2.1.2 */ 214 struct tb_cfg_cap_tmu { 215 struct tb_cfg_cap_hdr hdr; 216 #define TB_CFG_CAP_TMU 0x03 217 } __packed; 218 219 struct tb_cfg_vsc_cap { 220 struct tb_cfg_cap_hdr hdr; 221 #define TB_CFG_CAP_VSC 0x05 222 uint8_t vsc_id; 223 uint8_t len; 224 } __packed; 225 226 struct tb_cfg_vsec_cap { 227 struct tb_cfg_cap_hdr hdr; 228 #define TB_CFG_CAP_VSEC 0x05 229 uint8_t vsec_id; 230 uint8_t len; 231 uint16_t vsec_next_cap; 232 uint16_t vsec_len; 233 } __packed; 234 235 union tb_cfg_cap { 236 struct tb_cfg_cap_hdr hdr; 237 struct tb_cfg_cap_tmu tmu; 238 struct tb_cfg_vsc_cap vsc; 239 struct tb_cfg_vsec_cap vsec; 240 } __packed; 241 242 #define TB_CFG_VSC_PLUG 0x01 /* Hot Plug and DROM */ 243 244 #define TB_CFG_VSEC_LC 0x06 /* Link Controller */ 245 #define TB_LC_DESC 0x02 /* LC Descriptor fields */ 246 #define TB_LC_DESC_NUM_LC_MASK GENMASK(3, 0) 247 #define TB_LC_DESC_SIZE_SHIFT 8 248 #define TB_LC_DESC_SIZE_MASK GENMASK(15, 8) 249 #define TB_LC_DESC_PORT_SHIFT 16 250 #define TB_LC_DESC_PORT_MASK GENMASK(27, 16) 251 #define TB_LC_UUID 0x03 252 #define TB_LC_DP_SINK 0x10 /* Display Port config */ 253 #define TB_LC_PORT_ATTR 0x8d /* Port attributes */ 254 #define TB_LC_PORT_ATTR_BE (1 << 12) /* Bonding enabled */ 255 #define TB_LC_SX_CTRL 0x96 /* Sleep control */ 256 #define TB_LC_SX_CTRL_WOC (1 << 1) 257 #define TB_LC_SX_CTRL_WOD (1 << 2) 258 #define TB_LC_SX_CTRL_WOU4 (1 << 5) 259 #define TB_LC_SX_CTRL_WOP (1 << 6) 260 #define TB_LC_SX_CTRL_L1C (1 << 16) 261 #define TB_LC_SX_CTRL_L1D (1 << 17) 262 #define TB_LC_SX_CTRL_L2C (1 << 20) 263 #define TB_LC_SX_CTRL_L2D (1 << 21) 264 #define TB_LC_SX_CTRL_UFP (1 << 30) 265 #define TB_LC_SX_CTRL_SLP (1 << 31) 266 #define TB_LC_POWER 0x740 267 268 /* Config space adapter basic registers 8.2.2.1 */ 269 struct tb_cfg_adapter { 270 uint16_t vendor_id; /* ADP CS0 */ 271 uint16_t product_id; 272 uint32_t adp_cs1; /* ADP CS1 */ 273 #define ADP_CS1_NEXT_CAP_MASK GENMASK(7,0) 274 #define GET_ADP_CS_NEXT_CAP(a) (a->adp_cs1 & \ 275 ADP_CS1_NEXT_CAP_MASK) 276 #define ADP_CS1_COUNTER_SHIFT 8 277 #define ADP_CS1_COUNTER_MASK GENMASK(18,8) 278 #define GET_ADP_CS_MAX_COUNTERS(a) ((a->adp_cs1 & \ 279 ADP_CS1_COUNTER_MASK) >> \ 280 ADP_CS1_COUNTER_SHIFT) 281 #define CFG_COUNTER_CONFIG_FLAG (1 << 19) 282 uint32_t adp_cs2; /* ADP CS2 */ 283 #define ADP_CS2_TYPE_MASK GENMASK(23,0) 284 #define GET_ADP_CS_TYPE(a) (a->adp_cs2 & ADP_CS2_TYPE_MASK) 285 #define ADP_CS2_UNSUPPORTED 0x000000 286 #define ADP_CS2_LANE 0x000001 287 #define ADP_CS2_HOSTIF 0x000002 288 #define ADP_CS2_PCIE_DFP 0x100101 289 #define ADP_CS2_PCIE_UFP 0x100102 290 #define ADP_CS2_DP_OUT 0x0e0102 291 #define ADP_CS2_DP_IN 0x0e0101 292 #define ADP_CS2_USB3_DFP 0x200101 293 #define ADP_CS2_USB3_UFP 0x200102 294 uint32_t adp_cs3; /* ADP CS 3 */ 295 #define ADP_CS3_ADP_NUM_SHIFT 20 296 #define ADP_CS3_ADP_NUM_MASK GENMASK(25,20) 297 #define GET_ADP_CS_ADP_NUM(a) ((a->adp_cs3 & \ 298 ADP_CS3_ADP_NUM_MASK) >> \ 299 ADP_CS3_ADP_NUM_SHIFT) 300 #define CFG_ADP_HEC_ERROR (1 << 29) 301 #define CFG_ADP_FC_ERROR (1 << 30) 302 #define CFG_ADP_SBC (1 << 31) 303 } __packed; 304 305 /* Config space lane adapter capability 8.2.2.3 */ 306 struct tb_cfg_cap_lane { 307 struct tb_cfg_cap_hdr hdr; /* LANE_ADP_CS_0 */ 308 #define TB_CFG_CAP_LANE 0x01 309 /* Supported link/width/power */ 310 uint16_t supp_lwp; 311 #define CAP_LANE_LINK_MASK GENMASK(3,0) 312 #define CAP_LANE_LINK_GEN3 0x0004 313 #define CAP_LANE_LINK_GEN2 0x0008 314 #define CAP_LANE_WIDTH_MASK GENMASK(9,4) 315 #define CAP_LANE_WIDTH_1X 0x0010 316 #define CAP_LANE_WIDTH_2X 0x0020 317 #define CAP_LANE_POWER_CL0 0x0400 318 #define CAP_LANE_POWER_CL1 0x0800 319 #define CAP_LANE_POWER_CL2 0x1000 320 /* Target link/width/power */ 321 uint16_t targ_lwp; /* LANE_ADP_CS_1 */ 322 #define CAP_LANE_TARGET_GEN2 0x0008 323 #define CAP_LANE_TARGET_GEN3 0x000c 324 #define CAP_LANE_TARGET_SINGLE 0x0010 325 #define CAP_LANE_TARGET_DUAL 0x0030 326 #define CAP_LANE_DISABLE 0x4000 327 #define CAP_LANE_BONDING 0x8000 328 /* Current link/width/state */ 329 uint16_t current_lws; 330 /* Same definitions a supp_lwp for bits 0 - 9 */ 331 #define CAP_LANE_STATE_SHIFT 10 332 #define CAP_LANE_STATE_MASK GENMASK(13,10) 333 #define CAP_LANE_STATE_DISABLE (0x0 << CAP_LANE_STATE_SHIFT) 334 #define CAP_LANE_STATE_TRAINING (0x1 << CAP_LANE_STATE_SHIFT) 335 #define CAP_LANE_STATE_CL0 (0x2 << CAP_LANE_STATE_SHIFT) 336 #define CAP_LANE_STATE_TXCL0 (0x3 << CAP_LANE_STATE_SHIFT) 337 #define CAP_LANE_STATE_RXCL0 (0x4 << CAP_LANE_STATE_SHIFT) 338 #define CAP_LANE_STATE_CL1 (0x5 << CAP_LANE_STATE_SHIFT) 339 #define CAP_LANE_STATE_CL2 (0x6 << CAP_LANE_STATE_SHIFT) 340 #define CAP_LANE_STATE_CLD (0x7 << CAP_LANE_STATE_SHIFT) 341 #define CAP_LANE_PMS 0x4000 342 /* Logical Layer Errors */ 343 uint16_t lle; /* LANE_ADP_CS_2 */ 344 #define CAP_LANE_LLE_MASK GENMASK(6,0) 345 #define CAP_LANE_LLE_ALE 0x01 346 #define CAP_LANE_LLE_OSE 0x02 347 #define CAP_LANE_LLE_TE 0x04 348 #define CAP_LANE_LLE_EBE 0x08 349 #define CAP_LANE_LLE_DBE 0x10 350 #define CAP_LANE_LLE_RDE 0x20 351 #define CAP_LANE_LLE_RST 0x40 352 uint16_t lle_enable; 353 } __packed; 354 355 /* Config space path registers 8.2.3.1 */ 356 struct tb_cfg_path { 357 } __packed; 358 359 /* Config space counter registers 8.2.4 */ 360 struct tb_cfg_counters { 361 } __packed; 362 363 #endif /* _TBCFG_REG_H */ 364