1 /*- 2 * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 * 24 * This software is derived from software provide by Kwikbyte who specifically 25 * disclaimed copyright on the code. 26 * 27 * $FreeBSD$ 28 */ 29 30 //*--------------------------------------------------------------------------- 31 //* ATMEL Microcontroller Software Support - ROUSSET - 32 //*--------------------------------------------------------------------------- 33 //* The software is delivered "AS IS" without warranty or condition of any 34 //* kind, either express, implied or statutory. This includes without 35 //* limitation any warranty or condition with respect to merchantability or 36 //* fitness for any particular purpose, or against the infringements of 37 //* intellectual property rights of others. 38 //*--------------------------------------------------------------------------- 39 //* File Name : AT91C_MCI_Device.h 40 //* Object : Data Flash Atmel Description File 41 //* Translator : 42 //* 43 //* 1.0 26/11/02 FB : Creation 44 //*--------------------------------------------------------------------------- 45 46 #ifndef __MCI_Device_h 47 #define __MCI_Device_h 48 49 #include <sys/types.h> 50 51 typedef unsigned int AT91S_MCIDeviceStatus; 52 53 /////////////////////////////////////////////////////////////////////////////// 54 55 #define AT91C_CARD_REMOVED 0 56 #define AT91C_MMC_CARD_INSERTED 1 57 #define AT91C_SD_CARD_INSERTED 2 58 59 #define AT91C_NO_ARGUMENT 0x0 60 61 #define AT91C_FIRST_RCA 0xCAFE 62 #define AT91C_MAX_MCI_CARDS 10 63 64 #define AT91C_BUS_WIDTH_1BIT 0x00 65 #define AT91C_BUS_WIDTH_4BITS 0x02 66 67 /* Driver State */ 68 #define AT91C_MCI_IDLE 0x0 69 #define AT91C_MCI_TIMEOUT_ERROR 0x1 70 #define AT91C_MCI_RX_SINGLE_BLOCK 0x2 71 #define AT91C_MCI_RX_MULTIPLE_BLOCK 0x3 72 #define AT91C_MCI_RX_STREAM 0x4 73 #define AT91C_MCI_TX_SINGLE_BLOCK 0x5 74 #define AT91C_MCI_TX_MULTIPLE_BLOCK 0x6 75 #define AT91C_MCI_TX_STREAM 0x7 76 77 /* TimeOut */ 78 #define AT91C_TIMEOUT_CMDRDY 30 79 80 81 82 /////////////////////////////////////////////////////////////////////////////// 83 // MMC & SDCard Structures 84 /////////////////////////////////////////////////////////////////////////////// 85 86 /*---------------------------------------------*/ 87 /* MCI Device Structure Definition */ 88 /*---------------------------------------------*/ 89 typedef struct _AT91S_MciDevice 90 { 91 volatile unsigned char state; 92 unsigned char SDCard_bus_width; 93 unsigned char IsSDv2; 94 unsigned char IsSDHC; 95 unsigned int RCA; // RCA 96 unsigned int READ_BL_LEN; 97 #ifdef REPORT_SIZE 98 unsigned int Memory_Capacity; 99 #endif 100 } AT91S_MciDevice; 101 102 #include <dev/mmc/mmcreg.h> 103 104 /////////////////////////////////////////////////////////////////////////////// 105 // Functions returnals 106 /////////////////////////////////////////////////////////////////////////////// 107 #define AT91C_CMD_SEND_OK 0 // Command ok 108 #define AT91C_CMD_SEND_ERROR -1 // Command failed 109 #define AT91C_INIT_OK 2 // Init Successful 110 #define AT91C_INIT_ERROR 3 // Init Failed 111 #define AT91C_READ_OK 4 // Read Successful 112 #define AT91C_READ_ERROR 5 // Read Failed 113 #define AT91C_WRITE_OK 6 // Write Successful 114 #define AT91C_WRITE_ERROR 7 // Write Failed 115 #define AT91C_ERASE_OK 8 // Erase Successful 116 #define AT91C_ERASE_ERROR 9 // Erase Failed 117 #define AT91C_CARD_SELECTED_OK 10 // Card Selection Successful 118 #define AT91C_CARD_SELECTED_ERROR 11 // Card Selection Failed 119 120 #define AT91C_MCI_SR_ERROR (AT91C_MCI_UNRE | AT91C_MCI_OVRE | AT91C_MCI_DTOE | \ 121 AT91C_MCI_DCRCE | AT91C_MCI_RTOE | AT91C_MCI_RENDE | AT91C_MCI_RCRCE | \ 122 AT91C_MCI_RDIRE | AT91C_MCI_RINDE) 123 124 #define MMC_CMDNB (0x1Fu << 0) // Command Number 125 #define MMC_RSPTYP (0x3u << 6) // Response Type 126 #define MMC_RSPTYP_NO (0x0u << 6) // No response 127 #define MMC_RSPTYP_48 (0x1u << 6) // 48-bit response 128 #define MMC_RSPTYP_136 (0x2u << 6) // 136-bit response 129 #define MMC_SPCMD (0x7u << 8) // Special CMD 130 #define MMC_SPCMD_NONE (0x0u << 8) // Not a special CMD 131 #define MMC_SPCMD_INIT (0x1u << 8) // Initialization CMD 132 #define MMC_SPCMD_SYNC (0x2u << 8) // Synchronized CMD 133 #define MMC_SPCMD_IT_CMD (0x4u << 8) // Interrupt command 134 #define MMC_SPCMD_IT_REP (0x5u << 8) // Interrupt response 135 #define MMC_OPDCMD (0x1u << 11) // Open Drain Command 136 #define MMC_MAXLAT (0x1u << 12) // Maximum Latency for Command to respond 137 #define MMC_TRCMD (0x3u << 16) // Transfer CMD 138 #define MMC_TRCMD_NO (0x0u << 16) // No transfer 139 #define MMC_TRCMD_START (0x1u << 16) // Start transfer 140 #define MMC_TRCMD_STOP (0x2u << 16) // Stop transfer 141 #define MMC_TRDIR (0x1u << 18) // Transfer Direction 142 #define MMC_TRTYP (0x3u << 19) // Transfer Type 143 #define MMC_TRTYP_BLOCK (0x0u << 19) // Block Transfer type 144 #define MMC_TRTYP_MULTIPLE (0x1u << 19) // Multiple Block transfer type 145 #define MMC_TRTYP_STREAM (0x2u << 19) // Stream transfer type 146 147 /////////////////////////////////////////////////////////////////////////////// 148 // MCI_CMD Register Value 149 /////////////////////////////////////////////////////////////////////////////// 150 #define POWER_ON_INIT \ 151 (0 | MMC_TRCMD_NO | MMC_SPCMD_INIT | MMC_OPDCMD) 152 153 ///////////////////////////////////////////////////////////////// 154 // Class 0 & 1 commands: Basic commands and Read Stream commands 155 ///////////////////////////////////////////////////////////////// 156 157 #define GO_IDLE_STATE_CMD \ 158 (0 | MMC_TRCMD_NO | MMC_SPCMD_NONE ) 159 #define MMC_GO_IDLE_STATE_CMD \ 160 (0 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_OPDCMD) 161 #define MMC_SEND_OP_COND_CMD \ 162 (1 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_48 | \ 163 MMC_OPDCMD) 164 165 #define ALL_SEND_CID_CMD \ 166 (2 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_136) 167 #define MMC_ALL_SEND_CID_CMD \ 168 (2 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_136 | \ 169 MMC_OPDCMD) 170 171 #define SET_RELATIVE_ADDR_CMD \ 172 (3 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_48 | \ 173 MMC_MAXLAT) 174 #define MMC_SET_RELATIVE_ADDR_CMD \ 175 (3 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_48 | \ 176 MMC_MAXLAT | MMC_OPDCMD) 177 178 #define SET_DSR_CMD \ 179 (4 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_NO | \ 180 MMC_MAXLAT) // no tested 181 182 #define SEL_DESEL_CARD_CMD \ 183 (7 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_48 | \ 184 MMC_MAXLAT) 185 #define SEND_CSD_CMD \ 186 (9 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_136 | \ 187 MMC_MAXLAT) 188 #define SEND_CID_CMD \ 189 (10 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_136 | \ 190 MMC_MAXLAT) 191 #define MMC_READ_DAT_UNTIL_STOP_CMD \ 192 (11 | MMC_TRTYP_STREAM | MMC_SPCMD_NONE | \ 193 MMC_RSPTYP_48 | MMC_TRDIR | MMC_TRCMD_START | \ 194 MMC_MAXLAT) 195 196 #define STOP_TRANSMISSION_CMD \ 197 (12 | MMC_TRCMD_STOP | MMC_SPCMD_NONE | MMC_RSPTYP_48 | \ 198 MMC_MAXLAT) 199 #define STOP_TRANSMISSION_SYNC_CMD \ 200 (12 | MMC_TRCMD_STOP | MMC_SPCMD_SYNC | MMC_RSPTYP_48 | \ 201 MMC_MAXLAT) 202 #define SEND_STATUS_CMD \ 203 (13 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_48 | \ 204 MMC_MAXLAT) 205 #define GO_INACTIVE_STATE_CMD \ 206 (15 | MMC_RSPTYP_NO) 207 #define SD_SEND_IF_COND_CMD \ 208 (8 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_48 | \ 209 MMC_MAXLAT) 210 //*------------------------------------------------ 211 //* Class 2 commands: Block oriented Read commands 212 //*------------------------------------------------ 213 214 #define SET_BLOCKLEN_CMD (16 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_MAXLAT ) 215 #define READ_SINGLE_BLOCK_CMD (17 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_START | MMC_TRTYP_BLOCK | MMC_TRDIR | MMC_MAXLAT) 216 #define READ_MULTIPLE_BLOCK_CMD (18 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_START | MMC_TRTYP_MULTIPLE | MMC_TRDIR | MMC_MAXLAT) 217 218 //*-------------------------------------------- 219 //* Class 3 commands: Sequential write commands 220 //*-------------------------------------------- 221 222 #define MMC_WRITE_DAT_UNTIL_STOP_CMD (20 | MMC_TRTYP_STREAM| MMC_SPCMD_NONE | MMC_RSPTYP_48 & ~(MMC_TRDIR) | MMC_TRCMD_START | MMC_MAXLAT ) // MMC 223 224 //*------------------------------------------------ 225 //* Class 4 commands: Block oriented write commands 226 //*------------------------------------------------ 227 228 #define WRITE_BLOCK_CMD (24 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_START | (MMC_TRTYP_BLOCK & ~(MMC_TRDIR)) | MMC_MAXLAT) 229 #define WRITE_MULTIPLE_BLOCK_CMD (25 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_START | (MMC_TRTYP_MULTIPLE & ~(MMC_TRDIR)) | MMC_MAXLAT) 230 #define PROGRAM_CSD_CMD (27 | MMC_RSPTYP_48 ) 231 232 233 //*---------------------------------------- 234 //* Class 6 commands: Group Write protect 235 //*---------------------------------------- 236 237 #define SET_WRITE_PROT_CMD (28 | MMC_RSPTYP_48 ) 238 #define CLR_WRITE_PROT_CMD (29 | MMC_RSPTYP_48 ) 239 #define SEND_WRITE_PROT_CMD (30 | MMC_RSPTYP_48 ) 240 241 242 //*---------------------------------------- 243 //* Class 5 commands: Erase commands 244 //*---------------------------------------- 245 246 #define TAG_SECTOR_START_CMD (32 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT) 247 #define TAG_SECTOR_END_CMD (33 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT) 248 #define MMC_UNTAG_SECTOR_CMD (34 | MMC_RSPTYP_48 ) 249 #define MMC_TAG_ERASE_GROUP_START_CMD (35 | MMC_RSPTYP_48 ) 250 #define MMC_TAG_ERASE_GROUP_END_CMD (36 | MMC_RSPTYP_48 ) 251 #define MMC_UNTAG_ERASE_GROUP_CMD (37 | MMC_RSPTYP_48 ) 252 #define ERASE_CMD (38 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT ) 253 254 //*---------------------------------------- 255 //* Class 7 commands: Lock commands 256 //*---------------------------------------- 257 258 #define LOCK_UNLOCK (42 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT) // no tested 259 260 //*----------------------------------------------- 261 // Class 8 commands: Application specific commands 262 //*----------------------------------------------- 263 264 #define APP_CMD (55 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT) 265 #define GEN_CMD (56 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT) // no tested 266 267 #define SDCARD_SET_BUS_WIDTH_CMD (6 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT) 268 #define SDCARD_STATUS_CMD (13 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT) 269 #define SDCARD_SEND_NUM_WR_BLOCKS_CMD (22 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT) 270 #define SDCARD_SET_WR_BLK_ERASE_COUNT_CMD (23 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT) 271 #define SDCARD_APP_OP_COND_CMD (41 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT) 272 #define SDCARD_SET_CLR_CARD_DETECT_CMD (42 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT) 273 #define SDCARD_SEND_SCR_CMD (51 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT) 274 275 #define SDCARD_APP_ALL_CMD (SDCARD_SET_BUS_WIDTH_CMD +\ 276 SDCARD_STATUS_CMD +\ 277 SDCARD_SEND_NUM_WR_BLOCKS_CMD +\ 278 SDCARD_SET_WR_BLK_ERASE_COUNT_CMD +\ 279 SDCARD_APP_OP_COND_CMD +\ 280 SDCARD_SET_CLR_CARD_DETECT_CMD +\ 281 SDCARD_SEND_SCR_CMD) 282 283 //*---------------------------------------- 284 //* Class 9 commands: IO Mode commands 285 //*---------------------------------------- 286 287 #define MMC_FAST_IO_CMD (39 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_MAXLAT) 288 #define MMC_GO_IRQ_STATE_CMD (40 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT) 289 290 /////////////////////////////////////////////////////////////////////////////// 291 // OCR Register 292 /////////////////////////////////////////////////////////////////////////////// 293 #define AT91C_VDD_16_17 (1 << 4) 294 #define AT91C_VDD_17_18 (1 << 5) 295 #define AT91C_VDD_18_19 (1 << 6) 296 #define AT91C_VDD_19_20 (1 << 7) 297 #define AT91C_VDD_20_21 (1 << 8) 298 #define AT91C_VDD_21_22 (1 << 9) 299 #define AT91C_VDD_22_23 (1 << 10) 300 #define AT91C_VDD_23_24 (1 << 11) 301 #define AT91C_VDD_24_25 (1 << 12) 302 #define AT91C_VDD_25_26 (1 << 13) 303 #define AT91C_VDD_26_27 (1 << 14) 304 #define AT91C_VDD_27_28 (1 << 15) 305 #define AT91C_VDD_28_29 (1 << 16) 306 #define AT91C_VDD_29_30 (1 << 17) 307 #define AT91C_VDD_30_31 (1 << 18) 308 #define AT91C_VDD_31_32 (1 << 19) 309 #define AT91C_VDD_32_33 (1 << 20) 310 #define AT91C_VDD_33_34 (1 << 21) 311 #define AT91C_VDD_34_35 (1 << 22) 312 #define AT91C_VDD_35_36 (1 << 23) 313 #define AT91C_CCS (1 << 30) 314 #define AT91C_CARD_POWER_UP_DONE (1U << 31) 315 316 #define AT91C_MMC_HOST_VOLTAGE_RANGE (AT91C_VDD_27_28 | AT91C_VDD_28_29 | \ 317 AT91C_VDD_29_30 | AT91C_VDD_30_31 | AT91C_VDD_31_32 | AT91C_VDD_32_33) 318 319 /////////////////////////////////////////////////////////////////////////////// 320 // CURRENT_STATE & READY_FOR_DATA in SDCard Status Register definition (response type R1) 321 /////////////////////////////////////////////////////////////////////////////// 322 #define AT91C_SR_READY_FOR_DATA (1 << 8) // corresponds to buffer empty signalling on the bus 323 #define AT91C_SR_IDLE (0 << 9) 324 #define AT91C_SR_READY (1 << 9) 325 #define AT91C_SR_IDENT (2 << 9) 326 #define AT91C_SR_STBY (3 << 9) 327 #define AT91C_SR_TRAN (4 << 9) 328 #define AT91C_SR_DATA (5 << 9) 329 #define AT91C_SR_RCV (6 << 9) 330 #define AT91C_SR_PRG (7 << 9) 331 #define AT91C_SR_DIS (8 << 9) 332 333 #define AT91C_SR_CARD_SELECTED (AT91C_SR_READY_FOR_DATA + AT91C_SR_TRAN) 334 335 #define MMC_FIRST_RCA 0xCAFE 336 337 /////////////////////////////////////////////////////////////////////////////// 338 // MMC CSD register header File 339 // CSD_x_xxx_S for shift value for word x 340 // CSD_x_xxx_M for mask value for word x 341 /////////////////////////////////////////////////////////////////////////////// 342 343 // First Response INT <=> CSD[3] : bits 0 to 31 344 #define CSD_3_BIT0_S 0 // [0:0] 345 #define CSD_3_BIT0_M 0x01 346 #define CSD_3_CRC_S 1 // [7:1] 347 #define CSD_3_CRC_M 0x7F 348 #define CSD_3_MMC_ECC_S 8 // [9:8] reserved for MMC compatibility 349 #define CSD_3_MMC_ECC_M 0x03 350 #define CSD_3_FILE_FMT_S 10 // [11:10] 351 #define CSD_3_FILE_FMT_M 0x03 352 #define CSD_3_TMP_WP_S 12 // [12:12] 353 #define CSD_3_TMP_WP_M 0x01 354 #define CSD_3_PERM_WP_S 13 // [13:13] 355 #define CSD_3_PERM_WP_M 0x01 356 #define CSD_3_COPY_S 14 // [14:14] 357 #define CSD_3_COPY_M 0x01 358 #define CSD_3_FILE_FMT_GRP_S 15 // [15:15] 359 #define CSD_3_FILE_FMT_GRP_M 0x01 360 // reserved 16 // [20:16] 361 // reserved 0x1F 362 #define CSD_3_WBLOCK_P_S 21 // [21:21] 363 #define CSD_3_WBLOCK_P_M 0x01 364 #define CSD_3_WBLEN_S 22 // [25:22] 365 #define CSD_3_WBLEN_M 0x0F 366 #define CSD_3_R2W_F_S 26 // [28:26] 367 #define CSD_3_R2W_F_M 0x07 368 #define CSD_3_MMC_DEF_ECC_S 29 // [30:29] reserved for MMC compatibility 369 #define CSD_3_MMC_DEF_ECC_M 0x03 370 #define CSD_3_WP_GRP_EN_S 31 // [31:31] 371 #define CSD_3_WP_GRP_EN_M 0x01 372 373 // Seconde Response INT <=> CSD[2] : bits 32 to 63 374 #define CSD_2_v21_WP_GRP_SIZE_S 0 // [38:32] 375 #define CSD_2_v21_WP_GRP_SIZE_M 0x7F 376 #define CSD_2_v21_SECT_SIZE_S 7 // [45:39] 377 #define CSD_2_v21_SECT_SIZE_M 0x7F 378 #define CSD_2_v21_ER_BLEN_EN_S 14 // [46:46] 379 #define CSD_2_v21_ER_BLEN_EN_M 0x01 380 381 #define CSD_2_v22_WP_GRP_SIZE_S 0 // [36:32] 382 #define CSD_2_v22_WP_GRP_SIZE_M 0x1F 383 #define CSD_2_v22_ER_GRP_SIZE_S 5 // [41:37] 384 #define CSD_2_v22_ER_GRP_SIZE_M 0x1F 385 #define CSD_2_v22_SECT_SIZE_S 10 // [46:42] 386 #define CSD_2_v22_SECT_SIZE_M 0x1F 387 388 #define CSD_2_C_SIZE_M_S 15 // [49:47] 389 #define CSD_2_C_SIZE_M_M 0x07 390 #define CSD_2_VDD_WMAX_S 18 // [52:50] 391 #define CSD_2_VDD_WMAX_M 0x07 392 #define CSD_2_VDD_WMIN_S 21 // [55:53] 393 #define CSD_2_VDD_WMIN_M 0x07 394 #define CSD_2_RCUR_MAX_S 24 // [58:56] 395 #define CSD_2_RCUR_MAX_M 0x07 396 #define CSD_2_RCUR_MIN_S 27 // [61:59] 397 #define CSD_2_RCUR_MIN_M 0x07 398 #define CSD_2_CSIZE_L_S 30 // [63:62] <=> 2 LSB of CSIZE 399 #define CSD_2_CSIZE_L_M 0x03 400 401 // Third Response INT <=> CSD[1] : bits 64 to 95 402 #define CSD_1_CSIZE_H_S 0 // [73:64] <=> 10 MSB of CSIZE 403 #define CSD_1_CSIZE_H_M 0x03FF 404 // reserved 10 // [75:74] 405 // reserved 0x03 406 #define CSD_1_DSR_I_S 12 // [76:76] 407 #define CSD_1_DSR_I_M 0x01 408 #define CSD_1_RD_B_MIS_S 13 // [77:77] 409 #define CSD_1_RD_B_MIS_M 0x01 410 #define CSD_1_WR_B_MIS_S 14 // [78:78] 411 #define CSD_1_WR_B_MIS_M 0x01 412 #define CSD_1_RD_B_PAR_S 15 // [79:79] 413 #define CSD_1_RD_B_PAR_M 0x01 414 #define CSD_1_RD_B_LEN_S 16 // [83:80] 415 #define CSD_1_RD_B_LEN_M 0x0F 416 #define CSD_1_CCC_S 20 // [95:84] 417 #define CSD_1_CCC_M 0x0FFF 418 419 // Fourth Response INT <=> CSD[0] : bits 96 to 127 420 #define CSD_0_TRANS_SPEED_S 0 // [103:96] 421 #define CSD_0_TRANS_SPEED_M 0xFF 422 #define CSD_0_NSAC_S 8 // [111:104] 423 #define CSD_0_NSAC_M 0xFF 424 #define CSD_0_TAAC_S 16 // [119:112] 425 #define CSD_0_TAAC_M 0xFF 426 // reserved 24 // [121:120] 427 // reserved 0x03 428 #define CSD_0_MMC_SPEC_VERS_S 26 // [125:122] reserved for MMC compatibility 429 #define CSD_0_MMC_SPEC_VERS_M 0x0F 430 #define CSD_0_STRUCT_S 30 // [127:126] 431 #define CSD_0_STRUCT_M 0x03 432 433 /////////////////////////////////////////////////////////////////////////////// 434 #endif 435